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"FPGA Design for Timing Yield Under Process Variations."

Akhilesh Kumar, Mohab Anis (2010)

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DOI: 10.1109/TVLSI.2008.2011555

access: closed

type: Journal Article

metadata version: 2020-03-11

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Akhilesh Kumar, Mohab Anis:
FPGA Design for Timing Yield Under Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 423-435 (2010)

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