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"A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based ..."

Meng Ni et al. (2021)

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DOI: 10.1109/TVLSI.2021.3078689

access: closed

type: Journal Article

metadata version: 2021-09-16

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Meng Ni, Xiao Wang, Fule Li, Zhihua Wang:
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1416-1427 (2021)

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