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"BDD decomposition for delay oriented pass transistor logic synthesis."

Rupesh S. Shelar, Sachin S. Sapatnekar (2005)

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DOI: 10.1109/TVLSI.2005.853601

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/ShelarS05
Rupesh S. Shelar, Sachin S. Sapatnekar:
BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 957-970 (2005)

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