Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation ..."

Rahul Shrestha (2021)

> Home

Details and statistics

DOI: 10.1109/TVLSI.2020.3031001

access: closed

type: Journal Article

metadata version: 2021-02-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/Shrestha21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/Shrestha21
Rahul Shrestha:
A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 65-75 (2021)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.