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"Generation of design verification tests from behavioral VHDL programs ..."

Ranga Vemuri, R. Kalyanaraman (1995)

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DOI: 10.1109/92.386221

access: closed

type: Journal Article

metadata version: 2022-04-09

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Ranga Vemuri, R. Kalyanaraman:
Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 201-214 (1995)

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