"A Modified Approach to Test Plan Generation for Combinational Logic Blocks."

Anupam Basu et al. (1996)

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DOI: 10.1155/1996/37648

access: open

type: Journal Article

metadata version: 2022-11-07

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  - https://dblp.org/rec/journals/vlsi/BasuBBWM96
Anupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia:
A Modified Approach to Test Plan Generation for Combinational Logic Blocks. VLSI Design 4(3): 243-256 (1996)

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