"Two-Symbol FPGA Architecture for Fast Arithmetic Encoding in JPEG 2000."

Nandini Ramesh Kumar, Wei Xiang, Yafeng Wang (2012)

> Home

Details and statistics

DOI: 10.1007/S11265-011-0655-1

access: closed

type: Journal Article

metadata version: 2021-04-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/vlsisp/KumarXW12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsisp/KumarXW12
Nandini Ramesh Kumar, Wei Xiang, Yafeng Wang:
Two-Symbol FPGA Architecture for Fast Arithmetic Encoding in JPEG 2000. J. Signal Process. Syst. 69(2): 213-224 (2012)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.