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"High Reliability Soft Error Hardened Latch Designfor Nanoscale CMOS ..."
T. Dhanushya, T. Latha (2023)
- T. Dhanushya, T. Latha:
High Reliability Soft Error Hardened Latch Designfor Nanoscale CMOS Technology using PVT Variation. Wirel. Pers. Commun. 128(2): 1471-1487 (2023)
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