"High-Speed, Low-Power 54-B X 54-B Digital Multiplier Architecture Using ..."

Yun Kim (2001)

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type: Book or Thesis

metadata version: 2023-09-07

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Yun Kim:
High-Speed, Low-Power 54-B X 54-B Digital Multiplier Architecture Using Redundant Binary. University of Illinois Urbana-Champaign, USA, 2001

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