Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSearch dblp for Publications
export results for "stream:streams/conf/mtdt:"
download as .bib file
@inproceedings{DBLP:conf/mtdt/Azimane06,
author = {Mohamed Azimane},
title = {High-Quality Memory Test},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.17},
doi = {10.1109/MTDT.2006.17},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Azimane06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/GyonjyanHV06,
author = {T. A. Gyonjyan and
Gurgen Harutunyan and
Valery A. Vardanian},
title = {A March-Based Algorithm for Location and Full Diagnosis of All Unlinked
Static Faults},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {9--14},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.5},
doi = {10.1109/MTDT.2006.5},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/GyonjyanHV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HsiaoCTC06,
author = {Shen{-}Fu Hsiao and
Yo{-}Chi Chen and
Ming{-}Yu Tsai and
Tze{-}Chong Cheng},
title = {Novel Memory Organization and Circuit Designs for Efficient Data Access
in Applications of 3D Graphics and Multimedia Coding},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {34--42},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.22},
doi = {10.1109/MTDT.2006.22},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/HsiaoCTC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Hsu06,
author = {Charles Hsu},
title = {Future Prospective of Programmable Logic Non-volatile Device},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.16},
doi = {10.1109/MTDT.2006.16},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Hsu06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HsuHYW06,
author = {Mu{-}Hsien Hsu and
Yu{-}Tsao Hsing and
Jen{-}Chieh Yeh and
Cheng{-}Wen Wu},
title = {Fault-Pattern Oriented Defect Diagnosis for Flash Memory},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {3--8},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.13},
doi = {10.1109/MTDT.2006.13},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/HsuHYW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KuoCKLHKCWHP06,
author = {Victor Chao{-}Wei Kuo and
Chih{-}Ming Chao and
Chih{-}Kai Kang and
Li{-}Wei Liu and
Tzung{-}Bin Huang and
Liang{-}Tai Kuo and
Shi{-}Hsien Chen and
Houng{-}Chi Wei and
Hann{-}Ping Hwang and
Saysamone Pittikoun},
title = {Detailed Comparisons of Program, Erase and Data Retention Characteristics
between {P+-} and N+-Poly {SONOS} {NAND} Flash Memory},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {77--79},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.10},
doi = {10.1109/MTDT.2006.10},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KuoCKLHKCWHP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KwaiCCYCHLLSLH06,
author = {Ding{-}Ming Kwai and
Yung{-}Fa Chou and
Meng{-}Fan Chang and
Su{-}Meng Yang and
Ding{-}Sheng Chen and
Min{-}Chung Hsu and
Yu{-}Zhen Liao and
Shiao{-}Yi Lin and
Yu{-}Ling Sung and
Chia{-}Hsin Lee and
Hsin{-}Kun Hsu},
title = {FlexiVia {ROM} Compiler Programmable on Different Via Layers Based
on Top Metal Assignment},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {28--33},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.14},
doi = {10.1109/MTDT.2006.14},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KwaiCCYCHLLSLH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KwaiHKCHCSPLCC06,
author = {Ding{-}Ming Kwai and
Ching{-}Hua Hsiao and
Chung{-}Ping Kuo and
Chi{-}Hsien Chuang and
Min{-}Chung Hsu and
Yi{-}Chun Chen and
Yu{-}Ling Sung and
Hsien{-}Yu Pan and
Chia{-}Hsin Lee and
Meng{-}Fan Chang and
Yung{-}Fa Chou},
title = {{SRAM} Cell Current in Low Leakage Design},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {65--70},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.28},
doi = {10.1109/MTDT.2006.28},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KwaiHKCHCSPLCC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Lai06,
author = {Jordan Lai},
title = {{SRAM} Design Techniques for Sub-nano {CMOS} Technology},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.29},
doi = {10.1109/MTDT.2006.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Lai06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LiangT06,
author = {Hsing{-}Chung Liang and
Le{-}Quen Tzeng},
title = {Improved Representatives for Unrepairability Judging and Economic
Repair Solutions of Memories},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {15},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.18},
doi = {10.1109/MTDT.2006.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LiangT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LinC06,
author = {Jyi{-}Tsong Lin and
Mike Chang},
title = {A New 1T {DRAM} Cell With Enhanced Floating Body Ef},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {23--27},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.6},
doi = {10.1109/MTDT.2006.6},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LinC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Lu06,
author = {Chih{-}Yuan Lu},
title = {Non-volatile Semiconductor Memory Technology in Nanotech Era},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.21},
doi = {10.1109/MTDT.2006.21},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Lu06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Muhmenthaler06,
author = {Peter Muhmenthaler},
title = {New on-Chip {DFT} and {ATE} Features for Efficient Embedded Memory
Test},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.20},
doi = {10.1109/MTDT.2006.20},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Muhmenthaler06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Pai06,
author = {Pei{-}Lin Pai},
title = {{DRAM} Industry Trend},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.11},
doi = {10.1109/MTDT.2006.11},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Pai06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SharifkhaniJS06,
author = {Mohammad Sharifkhani and
Shah M. Jahinuzzaman and
Manoj Sachdev},
title = {Dynamic Data Stability in {SRAM} Cells and Its Implications on Data
Stability Tests},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {55--64},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.12},
doi = {10.1109/MTDT.2006.12},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SharifkhaniJS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ShimizuAHSKYAITI06,
author = {Yuui Shimizu and
Hisanori Aikawa and
Keiji Hosotani and
Naoharu Shimomura and
Tadashi Kai and
Yoshihiro Ueda and
Yoshiaki Asao and
Yoshihisa Iwata and
Kenji Tsuchida and
Sumio Ikegawa},
title = {{MRAM} Write Error Categorization with {QCKB}},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {43--48},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.19},
doi = {10.1109/MTDT.2006.19},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ShimizuAHSKYAITI06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Shirota06,
author = {Riichiro Shirota},
title = {Roadmap of the Flash Memory},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.27},
doi = {10.1109/MTDT.2006.27},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Shirota06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/VollrathSGSJ06,
author = {J{\"{o}}rg E. Vollrath and
J{\"{u}}rg Schwizer and
Marcin Gnat and
Ralf Schneider and
Bret Johnson},
title = {{DDR2} {DRAM} Output Timing Optimization},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {49--54},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.9},
doi = {10.1109/MTDT.2006.9},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/VollrathSGSJ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/WangMCD06,
author = {Hua Wang and
Miguel Miranda and
Francky Catthoor and
Wim Dehaene},
title = {On the Combined Impact of Soft and Medium Gate Oxide Breakdown and
Process Variability on the Parametric Figures of {SRAM} components},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {71--76},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.23},
doi = {10.1109/MTDT.2006.23},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/WangMCD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/WuCLWLWCHPCK06,
author = {Jia{-}Lin Wu and
Hua{-}Ching Chien and
Chien{-}Wei Liao and
Cheng{-}Yen Wu and
Chih{-}Yuan Lee and
Houng{-}Chi Wei and
Shih{-}Hsien Chen and
Hann{-}Ping Hwang and
Saysamone Pittikoun and
Travis Cho and
Chin{-}Hsing Kao},
title = {Comparison of Electrical and Reliability Characteristics of Different
Tunnel Oxides in {SONOS} Flash Memory},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
pages = {80--84},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.8},
doi = {10.1109/MTDT.2006.8},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/WuCLWLWCHPCK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/X06,
title = {Foreword},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.15},
doi = {10.1109/MTDT.2006.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/X06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/X06a,
title = {Organizing Committee},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.24},
doi = {10.1109/MTDT.2006.24},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/X06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/X06b,
title = {Program Committee},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.25},
doi = {10.1109/MTDT.2006.25},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/X06b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/X06c,
title = {Reviewers},
booktitle = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTDT.2006.26},
doi = {10.1109/MTDT.2006.26},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/X06c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtdt/2006,
title = {14th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2006), 2-4 August 2006, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://ieeexplore.ieee.org/xpl/conhome/11003/proceeding},
isbn = {0-7695-2572-5},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/2006.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/BanerjeeCB05,
author = {Shibaji Banerjee and
Dipanwita Roy Chowdhury and
Bhargab B. Bhattacharya},
title = {A programmable built-in self-test for embedded DRAMs},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {58--63},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.14},
doi = {10.1109/MTDT.2005.14},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/BanerjeeCB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/BreitwischLJMZ05,
author = {Matthew J. Breitwisch and
Chung Hon Lam and
Jeffrey B. Johnson and
Steven W. Mittl and
Jian W. Zhu},
title = {A novel {CMOS} compatible embedded nonvolatile memory with zero process
adder},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {9--12},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.12},
doi = {10.1109/MTDT.2005.12},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/BreitwischLJMZ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ChangWK05,
author = {Meng{-}Fan Chang and
Kuei{-}Ann Wen and
Ding{-}Ming Kwai},
title = {Via-programmable read-only memory design for full code coverage using
a dynamic bit-line shielding technique},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {16--21},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.36},
doi = {10.1109/MTDT.2005.36},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ChangWK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ChengH05,
author = {Shin{-}Pao Cheng and
Shi{-}Yu Huang},
title = {A low-power {SRAM} design using quiet-bitline architecture},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {135--139},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.10},
doi = {10.1109/MTDT.2005.10},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ChengH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/DuMCR05,
author = {Xiaogang Du and
Nilanjan Mukherjee and
Wu{-}Tung Cheng and
Sudhakar M. Reddy},
title = {Full-speed field programmable memory {BIST} supporting multi-level
looping},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {67--71},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.25},
doi = {10.1109/MTDT.2005.25},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/DuMCR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HamdiouiAGW05,
author = {Said Hamdioui and
Zaid Al{-}Ars and
Ad J. van de Goor and
Rob Wadsworth},
title = {Impact of stresses on the fault coverage of memory tests},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {103--108},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.26},
doi = {10.1109/MTDT.2005.26},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/HamdiouiAGW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HsiaoK05,
author = {Ching{-}Hua Hsiao and
Ding{-}Ming Kwai},
title = {Measurement and characterization of 6T {SRAM} cell current},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {140--145},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.28},
doi = {10.1109/MTDT.2005.28},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/HsiaoK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HuaCH05,
author = {Chung{-}Hsien Hua and
Tung{-}Shuan Cheng and
Wei Hwang},
title = {Distributed data-retention power gating techniques for column and
row co-controlled embedded {SRAM}},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {129--134},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.21},
doi = {10.1109/MTDT.2005.21},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/HuaCH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KushidaOHT05,
author = {Keiichi Kushida and
Nobuaki Otsuka and
Osamu Hirabayashi and
Yasuhisa Takeyama},
title = {{DFT} techniques for memory macro with built-in {ECC}},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {109--114},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.19},
doi = {10.1109/MTDT.2005.19},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KushidaOHT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LeeJSTCL05,
author = {Yang{-}Han Lee and
Yih{-}Guang Jan and
Jei{-}Jung Shen and
Shian{-}Wei Tzeng and
Ming{-}Hsueh Chuang and
Jheng{-}Yao Lin},
title = {{DFT} architecture for a dynamic fault model of the embedded mask
{ROM} of {SOC}},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {78--82},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.8},
doi = {10.1109/MTDT.2005.8},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LeeJSTCL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LeeWK05,
author = {Kung{-}Hong Lee and
Shih{-}Chen Wang and
Ya{-}Chin King},
title = {Novel self-convergent scheme logic-process-based multilevel/analog
{EEPROM} memory},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {3--8},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.29},
doi = {10.1109/MTDT.2005.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LeeWK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LiH05,
author = {Jin{-}Fu Li and
Yu{-}Jane Huang},
title = {An error detection and correction scheme for RAMs with partial-write
function},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {115--120},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.16},
doi = {10.1109/MTDT.2005.16},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/LiH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LiSWLS05,
author = {Simon C. Li and
J. P. Su and
T.{-}H. Wu and
J. M. Lee and
M. F. Shu},
title = {Dielectric tunnel parameters of CoFe/Al-O/CoFe in {MTJ} for 1T1MTJ
{MRAM} applications},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {29--34},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.20},
doi = {10.1109/MTDT.2005.20},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LiSWLS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LinLHLLHWHLH05,
author = {Ching{-}Yuan Lin and
Chung{-}Hung Lin and
Chien{-}Hung Ho and
Wei{-}Wu Liao and
Shu{-}Yueh Lee and
Ming{-}Chou Ho and
Shih{-}Chen Wang and
Shih{-}Chan Huang and
Yuan{-}Tai Lin and
Charles Ching{-}Hsiang Hsu},
title = {Embedded {OTP} fuse in {CMOS} logic process},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {13--15},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.22},
doi = {10.1109/MTDT.2005.22},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LinLHLLHWHLH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LinesMOPDPCNMPM05,
author = {Valerie Lines and
Robert McKenzie and
Hakjune Oh and
Hong{-}Beom Pyeon and
Matthew Dunn and
Susan Palapar and
Susan Coleman and
Peter Nyasulu and
Tony Mai and
Seanna Pike and
John McCready and
Jody Defazio and
Jin{-}Ki Kim and
Robert Penchuk and
Zvika Greenfield and
Fredy Lange and
Alberto Mandler and
Eric C. Jones and
Matthew Silverstein},
title = {A 1GHz embedded {DRAM} macro and fully programmable {BIST} with at-speed
bitmap capability},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {47--51},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.5},
doi = {10.1109/MTDT.2005.5},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LinesMOPDPCNMPM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LuTH05,
author = {Shyue{-}Kung Lu and
Yu{-}Cheng Tsai and
Shih{-}Chang Huang},
title = {A {BIRA} algorithm for embedded memories with 2D redundancy},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {121--126},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.6},
doi = {10.1109/MTDT.2005.6},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LuTH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/McGaughyWH05,
author = {Bruce McGaughy and
S. W{\"{u}}nsche and
K. K. Hung},
title = {Advanced simulation technology and its application in memory design
and verification},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {xv--xx},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.27},
doi = {10.1109/MTDT.2005.27},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/McGaughyWH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/OkhoninFJ05,
author = {Serguei Okhonin and
Pierre Fazan and
Mark{-}Eric Jones},
title = {Zero capacitor embedded memory technology for system on chip},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {xxi--xxv},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.4655409},
doi = {10.1109/MTDT.2005.4655409},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/OkhoninFJ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/RaiterC05,
author = {Kamlesh R. Raiter and
Bruce F. Cockburn},
title = {An investigation into three-level ferroelectric memory},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {38--43},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.17},
doi = {10.1109/MTDT.2005.17},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/RaiterC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ShenHCL05,
author = {Sheng{-}Chih Shen and
Hung{-}Ming Hsu and
Yi{-}Wei Chang and
Kuen{-}Jong Lee},
title = {A high speed {BIST} architecture for {DDR-SDRAM} testing},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {52--57},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.9},
doi = {10.1109/MTDT.2005.9},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ShenHCL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SinghBD05,
author = {Amandeep Singh and
Debashish Bose and
Sandeep Darisala},
title = {Software based in-system memory test for highly available systems},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {89--94},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.34},
doi = {10.1109/MTDT.2005.34},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SinghBD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SungCC05,
author = {Star Sung and
Thomas Chang and
Juei Lung Chen},
title = {A nor-type {MLC} {ROM} with novel sensing scheme for embedded applications},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {22--25},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.11},
doi = {10.1109/MTDT.2005.11},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SungCC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/TsaiWC05,
author = {Po{-}Chang Tsai and
Sying{-}Jyan Wang and
Feng{-}Ming Chang},
title = {FSM-based programmable memory {BIST} with macro command},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {72--77},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.24},
doi = {10.1109/MTDT.2005.24},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/TsaiWC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/WangL05,
author = {Wei{-}Lun Wang and
Kuen{-}Jong Lee},
title = {A complete memory address generator for scan based March algorithms},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {83--88},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.7},
doi = {10.1109/MTDT.2005.7},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/WangL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/WeyLQ05,
author = {Chin{-}Long Wey and
Meng{-}Yao Liu and
Shaolei Quan},
title = {Reliability enhancement of {CMOS} SRAMs},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {146--151},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.32},
doi = {10.1109/MTDT.2005.32},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/WeyLQ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/WuFK05,
author = {Meng{-}Yi Wu and
Shin{-}Chang Feng and
Ya{-}Chin King},
title = {A novel single poly-silicon {EEPROM} using trench floating gate},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {35--37},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.13},
doi = {10.1109/MTDT.2005.13},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/WuFK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/YehKWHC05,
author = {Jen{-}Chieh Yeh and
Shyr{-}Fen Kuo and
Cheng{-}Wen Wu and
Chih{-}Tsun Huang and
Chao{-}Hsun Chen},
title = {A systematic approach to reducing semiconductor memory test time in
mass production},
booktitle = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
pages = {97--102},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTDT.2005.15},
doi = {10.1109/MTDT.2005.15},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/YehKWHC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtdt/2005,
title = {13th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2005), 3-5 August 2005, Taipei, Taiwan},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://ieeexplore.ieee.org/xpl/conhome/10032/proceeding},
isbn = {0-7695-2313-7},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/2005.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/AdamsABBM04,
author = {R. Dean Adams and
Robert Abbott and
Xiaoliang Bai and
Dwayne Burek and
Eric MacDonald},
title = {An Integrated Memory Self Test and {EDA} Solution},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {92--95},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.5},
doi = {10.1109/MTDT.2004.5},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/AdamsABBM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/AdhamN04,
author = {Saman Adham and
Benoit Nadeau{-}Dostie},
title = {A {BIST} Algorithm for Bit/Group Write Enable Faults in SRAMs},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {98--101},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.1},
doi = {10.1109/MTDT.2004.1},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/AdhamN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Aitken04,
author = {Robert C. Aitken},
title = {Redundancy {\&} It's Not Just for Defects Anymore},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {117--120},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.19},
doi = {10.1109/MTDT.2004.19},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Aitken04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/AkaabouneBA04,
author = {Adil Akaaboune and
Nazeih Botros and
Jaafar Alghazo},
title = {Tag Skipping Technique Using {WTS} Buffer for Optimal Low Power Cache
Design},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {13--18},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.21},
doi = {10.1109/MTDT.2004.21},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/AkaabouneBA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Al-ArsHSG04,
author = {Zaid Al{-}Ars and
Martin Herzog and
Ivo Schanstra and
Ad J. van de Goor},
title = {Influence of Bit Line Twisting on the Faulty Behavior of DRAMs},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {32--37},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.12},
doi = {10.1109/MTDT.2004.12},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Al-ArsHSG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/AlghazoAB04,
author = {Jaafar Alghazo and
Adil Akaaboune and
Nazeih Botros},
title = {{SF-LRU} Cache Replacement Algorithm},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {19--24},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.20},
doi = {10.1109/MTDT.2004.20},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/AlghazoAB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Bahl04,
author = {Swapnil Bahl},
title = {A Novel Method for Silicon Configurable Test Flow and Algorithms for
Testing, Debugging and Characterizing Different Types of Embedded
Memories through a Shared Controller},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {78--83},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.2},
doi = {10.1109/MTDT.2004.2},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Bahl04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Cockburn04,
author = {Bruce F. Cockburn},
title = {Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access
Memory},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {46--51},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.24},
doi = {10.1109/MTDT.2004.24},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Cockburn04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/DenqHWCW04,
author = {Li{-}Ming Denq and
Rei{-}Fu Huang and
Cheng{-}Wen Wu and
Yeong{-}Jar Chang and
Wen Ching Wu},
title = {A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {65--69},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.3},
doi = {10.1109/MTDT.2004.3},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/DenqHWCW04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/DerhacobianVZ04,
author = {N. Derhacobian and
Valery A. Vardanian and
Yervant Zorian},
title = {Embedded Memory Reliability: The {SER} Challenge},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {104--110},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.10},
doi = {10.1109/MTDT.2004.10},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/DerhacobianVZ04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/GoorHA04,
author = {Ad J. van de Goor and
Said Hamdioui and
Zaid Al{-}Ars},
title = {The Effectiveness of the Scan Test and Its New Variants},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {26--31},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.22},
doi = {10.1109/MTDT.2004.22},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/GoorHA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HamdiouiGG04,
author = {Said Hamdioui and
Georgi Gaydadjiev and
Ad J. van de Goor},
title = {The State-of-Art and Future Trends in Testing Embedded Memories},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {54--59},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.23},
doi = {10.1109/MTDT.2004.23},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/HamdiouiGG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LuH04,
author = {Shyue{-}Kung Lu and
Shih{-}Chang Huang},
title = {Built-in Self-Test and Repair {(BISTR)} Techniques for Embedded RAMs},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {60--64},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.7},
doi = {10.1109/MTDT.2004.7},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LuH04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/OuY04,
author = {Elaine Ou and
Woodward Yang},
title = {Fast Error-Correcting Circuits for Fault-Tolerant Memory},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {8--12},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.11},
doi = {10.1109/MTDT.2004.11},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/OuY04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SchianoOL04,
author = {Luca Schiano and
Marco Ottavi and
Fabrizio Lombardi},
title = {Markov Models of Fault-Tolerant Memory Systems under {SEU}},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {38--43},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.13},
doi = {10.1109/MTDT.2004.13},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SchianoOL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SelvaTRZCMA04,
author = {Carolina Selva and
Cosimo Torelli and
Danilo Rimondi and
Rita Zappa and
Stefano Corbani and
Giovanni Mastrodomenico and
Lara Albani},
title = {A Programmable Built-in Self-Diagnosis for Embedded {SRAM}},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {84--89},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.4},
doi = {10.1109/MTDT.2004.4},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SelvaTRZCMA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SpicaM04,
author = {Michael Spica and
T. M. Mak},
title = {Do We Need Anything More Than Single Bit Error Correction (ECC)?},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {111--116},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.9},
doi = {10.1109/MTDT.2004.9},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SpicaM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ZappaSRTCMA04,
author = {Rita Zappa and
Carolina Selva and
Danilo Rimondi and
Cosimo Torelli and
M. Crestan and
Giovanni Mastrodomenico and
Lara Albani},
title = {Micro Programmable Built-In Self Repair for SRAMs},
booktitle = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
pages = {72--77},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.2004.14},
doi = {10.1109/MTDT.2004.14},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ZappaSRTCMA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtdt/2004,
title = {12th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2004), 9-10 August 2004, San Jose, CA, {USA}},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://ieeexplore.ieee.org/xpl/conhome/9251/proceeding},
isbn = {0-7695-2193-2},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/2004.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Aitken03,
author = {Robert C. Aitken},
title = {Applying Defect-Based Test to Embedded Memories in a {COT} Model},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {72},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222364},
doi = {10.1109/MTDT.2003.1222364},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Aitken03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Al-ArsG03,
author = {Zaid Al{-}Ars and
Ad J. van de Goor},
title = {Systematic Memory Test Generation for {DRAM} Defects Causing Two Floating
Nodes},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {27--32},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222357},
doi = {10.1109/MTDT.2003.1222357},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Al-ArsG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Al-ArsHG03,
author = {Zaid Al{-}Ars and
Said Hamdioui and
Ad J. van de Goor},
title = {A Fault Primitive Based Analysis of Linked Faults in RAMs},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {33},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222358},
doi = {10.1109/MTDT.2003.1222358},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Al-ArsHG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Barth03,
author = {Roger Barth},
title = {{ITRS} Commodity Memory Roadmap},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {61--63},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222362},
doi = {10.1109/MTDT.2003.1222362},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Barth03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ChoiPLKP03,
author = {Minsu Choi and
Nohpill Park and
Fabrizio Lombardi and
Yong{-}Bin Kim and
Vincenzo Piuri},
title = {Optimal Spare Utilization in Repairable and Reliable Memory Cores},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {64--71},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222363},
doi = {10.1109/MTDT.2003.1222363},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ChoiPLKP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/CockburnTE03,
author = {Bruce F. Cockburn and
Jes{\'{u}}s Hern{\'{a}}ndez Tapia and
Duncan G. Elliott},
title = {A Multilevel {DRAM} with Hierarchical Bitlines and Serial Sensing},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {14--19},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222355},
doi = {10.1109/MTDT.2003.1222355},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/CockburnTE03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/DagaPRCSG03,
author = {Jean Michel Daga and
Caroline Papaix and
Emmanuel Racape and
Marylene Combe and
Vincent Sialelli and
Jeanine Guichaoua},
title = {A 40ns Random Access Time Low Voltage 2Mbits {EEPROM} Memory for Embedded
Applications},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {81--85},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222365},
doi = {10.1109/MTDT.2003.1222365},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/DagaPRCSG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HuangDWL03,
author = {Rei{-}Fu Huang and
Li{-}Ming Denq and
Cheng{-}Wen Wu and
Jin{-}Fu Li},
title = {A Testability-Driven Optimizer and Wrapper Generator for Embedded
Memories},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {53},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222361},
doi = {10.1109/MTDT.2003.1222361},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/HuangDWL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Prince03,
author = {Betty Prince},
title = {Application Specific DRAMs Today},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {7--13},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222354},
doi = {10.1109/MTDT.2003.1222354},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Prince03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SalamonC03,
author = {Daniel Salamon and
Bruce F. Cockburn},
title = {An Electrical Simulation Model for the Chalcogenide Phase-Change Memory
Cell},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {86},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222366},
doi = {10.1109/MTDT.2003.1222366},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SalamonC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Vollrath03,
author = {J{\"{o}}rg E. Vollrath},
title = {Output Timing Measurement Using an Idd Method},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {43--46},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222359},
doi = {10.1109/MTDT.2003.1222359},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Vollrath03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/WangYI03,
author = {Baosheng Wang and
Josh Yang and
Andr{\'{e}} Ivanov},
title = {Reducing Test Time of Embedded SRAMs},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {47--52},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222360},
doi = {10.1109/MTDT.2003.1222360},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/WangYI03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ZendaNF03,
author = {Youhei Zenda and
Koji Nakamae and
Hiromu Fujioka},
title = {Cost Optimum Embedded {DRAM} Design by Yield Analysis},
booktitle = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
pages = {20},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTDT.2003.1222356},
doi = {10.1109/MTDT.2003.1222356},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ZendaNF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtdt/2003,
title = {11th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2003), 28-29 July 2003, San Jose, CA, {USA}},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://ieeexplore.ieee.org/xpl/conhome/8664/proceeding},
isbn = {0-7695-2004-9},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/2003.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/AppelloFTCRR02,
author = {Davide Appello and
Alessandra Fudoli and
Vincenzo Tancorre and
Fulvio Corno and
Maurizio Rebaudengo and
Matteo Sonza Reorda},
title = {A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting
Image Processing Techniques},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {12--16},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029757},
doi = {10.1109/MTDT.2002.1029757},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/AppelloFTCRR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Bied-CharretonGJ02,
author = {D. Bied{-}Charreton and
D. Guillon and
B. Jacques},
title = {The {YATE} Fail-Safe Interface: The User's Point of View},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {39--43},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029761},
doi = {10.1109/MTDT.2002.1029761},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Bied-CharretonGJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/CasuF02,
author = {Mario R. Casu and
Philippe Flatresse},
title = {Converting an Embedded Low-Power {SRAM} from Bulk to {PD-SOI}},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {163--167},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029780},
doi = {10.1109/MTDT.2002.1029780},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/CasuF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Cockburn02,
author = {Bruce F. Cockburn},
title = {Panel on Advanced Embedded Memory Technologies},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {177--178},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029782},
doi = {10.1109/MTDT.2002.1029782},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Cockburn02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ColomaDH02,
author = {Bernard Coloma and
Patrick Delaunay and
Olivier Husson},
title = {High Speed 15 ns 4 Mbits {SRAM} for Space Application},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {32--38},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029760},
doi = {10.1109/MTDT.2002.1029760},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ColomaDH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/DevoivreLJCFTVGBHVTRGPTGRBPNPDLHH02,
author = {Thierry Devoivre and
M. Lunenborg and
C. Julien and
J.{-}P. Carrere and
P. Ferreira and
W. J. Toren and
A. VandeGoor and
P. Gayet and
T. Berger and
O. Hinsinger and
P. Vannier and
Y. Trouiller and
Y. Rody and
P.{-}J. Goirand and
R. Palla and
I. Thomas and
F. Guyader and
David Roy and
B. Borot and
Nicolas Planes and
Sylvie Naudet and
F. Pico and
D. Duca and
F. Lalanne and
D. Heslinga and
M. Haond},
title = {Validated 90nm {CMOS} Technology Platform with Low-k Copper Interconnects
for Advanced System-on-Chip (SoC)},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {157--162},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029778},
doi = {10.1109/MTDT.2002.1029778},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/DevoivreLJCFTVGBHVTRGPTGRBPNPDLHH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/DrayG02,
author = {Cyrille Dray and
Philippe Gendrier},
title = {A Novel Memory Array Based on an Annular Single-Poly {EPROM} Cell
for Use in Standard {CMOS} Technology},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {143--148},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029775},
doi = {10.1109/MTDT.2002.1029775},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/DrayG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/GibbinsAEOW02,
author = {Robert Gibbins and
R. Dean Adams and
Thomas J. Eckenrode and
Michael Ouellette and
Yuejian Wu},
title = {Design and Test of a 9-port {SRAM} for a 100Gb/s {STS-1} Switch},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {83},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029767},
doi = {10.1109/MTDT.2002.1029767},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/GibbinsAEOW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HamdiouiGR02,
author = {Said Hamdioui and
Ad J. van de Goor and
Mike Rodgers},
title = {March {SS:} {A} Test for All Static Simple {RAM} Faults},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {95--100},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029769},
doi = {10.1109/MTDT.2002.1029769},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/HamdiouiGR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Hashimoto02,
author = {Masashi Hashimoto},
title = {Adder Merged {DRAM} Architecture},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {88--94},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029768},
doi = {10.1109/MTDT.2002.1029768},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Hashimoto02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HuangLYW02,
author = {Rei{-}Fu Huang and
Jin{-}Fu Li and
Jen{-}Chieh Yeh and
Cheng{-}Wen Wu},
title = {A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable
Embedded Memories},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {68},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029766},
doi = {10.1109/MTDT.2002.1029766},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/HuangLYW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Jee02,
author = {Alvin Jee},
title = {Defect-Oriented Analysis of Memory {BIST} Tests},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {7--11},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029756},
doi = {10.1109/MTDT.2002.1029756},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Jee02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Kablanian02,
author = {A. Kablanian},
title = {Embedded Memory Test and Repair},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
publisher = {{IEEE} Computer Society},
year = {2002},
timestamp = {Mon, 15 Dec 2003 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Kablanian02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KarimiL02,
author = {Farzin Karimi and
Fabrizio Lombardi},
title = {A Scan-Bist Environment for Testing Embedded Memories},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {17},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029758},
doi = {10.1109/MTDT.2002.1029758},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KarimiL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KarimiML02,
author = {Farzin Karimi and
Fred J. Meyer and
Fabrizio Lombardi},
title = {Random Testing of Multi-Port Static Random Access Memories},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {101--108},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029770},
doi = {10.1109/MTDT.2002.1029770},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KarimiML02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KayaSMO02,
author = {Toshiyuki Kaya and
Isao Shirakawa and
Ryusuke Miyamoto and
Takao Onoye},
title = {Design of Embedded System for Video Coding with Logic-Enhanced {DRAM}
and Configurable Process},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
publisher = {{IEEE} Computer Society},
year = {2002},
timestamp = {Thu, 12 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/KayaSMO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LaffontRCBM02,
author = {Romain Laffont and
J. Razafindramora and
Pierre Canet and
Rachid Bouchakour and
Jean{-}Michel Mirabel},
title = {Decreasing {EEPROM} Programming Bias With Negative Voltage, Reliability
Impact},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {168--176},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029781},
doi = {10.1109/MTDT.2002.1029781},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/LaffontRCBM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Magarshack02,
author = {Philippe Magarshack},
title = {SoC's Trends and Challenges going to 0.10{\(\mathrm{\mu}\)}m},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
publisher = {{IEEE} Computer Society},
year = {2002},
timestamp = {Mon, 15 Dec 2003 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Magarshack02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ManzoneC02,
author = {Alberto Manzone and
Diego De Costantini},
title = {Fault Tolerant Insertion and Verification: {A} Case Study},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {44--48},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029762},
doi = {10.1109/MTDT.2002.1029762},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ManzoneC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Nicolaidis02,
author = {Michael Nicolaidis},
title = {Soft Error Protection for Embedded Memories},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
publisher = {{IEEE} Computer Society},
year = {2002},
timestamp = {Mon, 15 Dec 2003 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Nicolaidis02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/PapaixD02,
author = {Caroline Papaix and
Jean Michel Daga},
title = {A New Single Ended Sense Amplifier for Low Voltage Embedded {EEPROM}
Non Volatile Memories},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {149--156},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029776},
doi = {10.1109/MTDT.2002.1029776},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/PapaixD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/PortalFAN02,
author = {Jean{-}Michel Portal and
L. Forli and
Hassen Aziza and
Didier N{\'{e}}e},
title = {An Automated Design Methodology for {EEPROM} Cell {(ADE)}},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {137--142},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029774},
doi = {10.1109/MTDT.2002.1029774},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/PortalFAN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/RedekerCE02,
author = {Michael Redeker and
Bruce F. Cockburn and
Duncan G. Elliott},
title = {An Investigation into Crosstalk Noise in {DRAM} Structures},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {123},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029773},
doi = {10.1109/MTDT.2002.1029773},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/RedekerCE02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/RedekerCEXU02,
author = {Michael Redeker and
Bruce F. Cockburn and
Duncan G. Elliott and
Yunan Xiang and
Sue Ann Ung},
title = {Fault Modeling and Pattern-Sensitivity Testing for a Multilevel {DRAM}},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {117--122},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029772},
doi = {10.1109/MTDT.2002.1029772},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/RedekerCEXU02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/RondeyTB02,
author = {Emmanuel Rondey and
Yann Tellier and
Simone Borri},
title = {A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs
with Different Redundancy Scenarios},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {57--61},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029764},
doi = {10.1109/MTDT.2002.1029764},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/RondeyTB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/RossiMR02,
author = {Daniele Rossi and
Cecilia Metra and
Bruno Ricc{\`{o}}},
title = {Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash
Memories},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {27--31},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029759},
doi = {10.1109/MTDT.2002.1029759},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/RossiMR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SchianoMM02,
author = {Luca Schiano and
Cecilia Metra and
Diego Marino},
title = {Design and Implementation of a Self-Checking Scheme for Railway Trackside
Systems},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {49--56},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029763},
doi = {10.1109/MTDT.2002.1029763},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SchianoMM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Templeton02,
author = {M. Templeton},
title = {Challenges and Opportunities Created by the SoC Shockwave},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
publisher = {{IEEE} Computer Society},
year = {2002},
timestamp = {Mon, 15 Dec 2003 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Templeton02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/VardanianZ02,
author = {Valery A. Vardanian and
Yervant Zorian},
title = {A March-Based Fault Location Algorithm for Static Random Access Memories},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {62--67},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029765},
doi = {10.1109/MTDT.2002.1029765},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/VardanianZ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/VenkateshKPS02,
author = {Raja Venkatesh and
Sailesh Kumar and
Joji Philip and
Sunil Shukla},
title = {A Fault Modeling Technique to Test Memory {BIST} Algorithms},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {109--116},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029771},
doi = {10.1109/MTDT.2002.1029771},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/VenkateshKPS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtdt/2002,
title = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://ieeexplore.ieee.org/xpl/conhome/8004/proceeding},
isbn = {0-7695-1617-3},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/2002.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Al-ArsAG01,
author = {Zaid Al{-}Ars and
Ad J. van de Goor},
title = {Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {59--64},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945229},
doi = {10.1109/MTDT.2001.945229},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Al-ArsAG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/GregoriTKM01,
author = {Stefano Gregori and
Guido Torelli and
Osama Khouri and
Rino Micheloni},
title = {An Error Control Code Scheme for Multilevel Flash Memories},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {45--50},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945227},
doi = {10.1109/MTDT.2001.945227},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/GregoriTKM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HamdiouiGER01,
author = {Said Hamdioui and
Ad J. van de Goor and
David Eastwick and
Mike Rodgers},
title = {Realistic Fault Models and Test Procedures for Multi-Port SRAMs},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {65--72},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945230},
doi = {10.1109/MTDT.2001.945230},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/HamdiouiGER01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Harling01,
author = {G. Harling},
title = {A {DRAM} Compiler for Fully Optimized Memory Instances},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {3--8},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945221},
doi = {10.1109/MTDT.2001.945221},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Harling01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KarimiLIC01,
author = {Farzin Karimi and
Fabrizio Lombardi and
V. Swamy Irrinki and
T. Crosby},
title = {A Parallel Approach for Testing Multi-Port Static Random Access Memories},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {73},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945233},
doi = {10.1109/MTDT.2001.945233},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KarimiLIC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KesslerDMMK01,
author = {Brian R. Kessler and
Jeffrey H. Dreibelbis and
Tim McMahon and
Joshua S. McCloy and
Rex Kho},
title = {BIST-Based Bitfail Mapping of an Embedded {DRAM}},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {29},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945225},
doi = {10.1109/MTDT.2001.945225},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KesslerDMMK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KhouriGSTM01,
author = {Osama Khouri and
Stefano Gregori and
Dario Soltesz and
Guido Torelli and
Rino Micheloni},
title = {Low Output Resistance Charge Pump for Flash Memory Programming},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {99},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945236},
doi = {10.1109/MTDT.2001.945236},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KhouriGSTM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KimRL01,
author = {Kyung{-}Saeng Kim and
KwangMyoung Rho and
Kwyro Lee},
title = {Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line
To Bit-Line Contact Scheme},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {9--12},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945222},
doi = {10.1109/MTDT.2001.945222},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KimRL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KoranneWBWKV01,
author = {Sandeep Koranne and
Tom Waayers and
Robert Beurze and
Clemens Wouters and
Sunil Kumar and
G. S. Visweswara},
title = {A {P1500} Compliant Programable BistShell for Embedded Memories},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {21--28},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945224},
doi = {10.1109/MTDT.2001.945224},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KoranneWBWKV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/MatarreseF01,
author = {Stella Matarrese and
Luca Fasoli},
title = {A Method to Caculate Redundancy Coverage for {FLASH} Memory},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {41--44},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945226},
doi = {10.1109/MTDT.2001.945226},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/MatarreseF01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/NapperY01,
author = {Simon Napper and
Dian Yang},
title = {Equivalence Checking a 256MB {SDRAM}},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {85--90},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945234},
doi = {10.1109/MTDT.2001.945234},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/NapperY01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ShoukourianVZ01,
author = {Samvel K. Shoukourian and
Valery A. Vardanian and
Yervant Zorian},
title = {An Approach for Evaluation of Redunancy Analysis Algorithms},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {51},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945228},
doi = {10.1109/MTDT.2001.945228},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ShoukourianVZ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SunXT01,
author = {Xiaoling Sun and
Jian Xu and
Pieter M. Trouborst},
title = {Testing Carry Logic Modules of SRAM-based FPGAs},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {91--98},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945235},
doi = {10.1109/MTDT.2001.945235},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SunXT01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SungKBEC01,
author = {Raymond J. Sung and
John C. Koob and
Tyler L. Brandon and
Duncan G. Elliott and
Bruce F. Cockburn},
title = {Design of an Embedded Fully-Depleted {SOI} {SRAM}},
booktitle = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
pages = {13},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/MTDT.2001.945223},
doi = {10.1109/MTDT.2001.945223},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SungKBEC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtdt/2001,
title = {9th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2001), 6-7 August 2001, San Jose, CA, {USA}},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://ieeexplore.ieee.org/xpl/conhome/7514/proceeding},
isbn = {0-7695-1242-9},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/2001.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/DagaPMRMGA00,
author = {Jean Michel Daga and
Caroline Papaix and
Marc Merandat and
Stephane Ricard and
Giuseppe Medulla and
Jeanine Guichaoua and
Daniel Auvergne},
title = {Design Techniques for Embedded {EEPROM} Memories in Portable {ASIC}
and {ASSP} Solutions},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {39--46},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868614},
doi = {10.1109/MTDT.2000.868614},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/DagaPMRMGA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/FreyGITS00,
author = {Christophe Frey and
F. Genevaux and
C. Issartel and
D. Turgis and
Jean{-}Pierre Schoellkopf},
title = {A Low Voltage Embedded Single Port {SRAM} Generator in a 0.18{\(\mathrm{\mu}\)}m
Standard {CMOS} Process},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {106--112},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868623},
doi = {10.1109/MTDT.2000.868623},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/FreyGITS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/HamdiouiGRE00,
author = {Said Hamdioui and
Ad J. van de Goor and
Mike Rodgers and
David Eastwick},
title = {March Tests for Realistic Faults in Two-Port Memories},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {73--78},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868618},
doi = {10.1109/MTDT.2000.868618},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/HamdiouiGRE00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Haythornthwaite00,
author = {Ray Haythornthwaite},
title = {Failure Mechanisms in Semiconductor Memory Circuits},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {7--13},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868609},
doi = {10.1109/MTDT.2000.868609},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Haythornthwaite00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/JeeCIP00,
author = {Alvin Jee and
Jonathon E. Colburn and
V. Swamy Irrinki and
Mukesh Puri},
title = {Optimizing Memory Tests by Analyzing Defect Coverage},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {20--28},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868611},
doi = {10.1109/MTDT.2000.868611},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/JeeCIP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/KhouriMGT00,
author = {Osama Khouri and
Rino Micheloni and
Stefano Gregori and
Guido Torelli},
title = {Fast Voltage Regulator for Multilevel Flash Memories},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {34--38},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868613},
doi = {10.1109/MTDT.2000.868613},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/KhouriMGT00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LinesAMMMKM00,
author = {Valerie Lines and
Abdullah Ahmed and
Peter Ma and
Stanley Ma and
Robert McKenzie and
Hong{-}Seok Kim and
Cynthia Mar},
title = {66MHz 2.3M Ternary Dynamic Content Addressable Memory},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {101--105},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868622},
doi = {10.1109/MTDT.2000.868622},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LinesAMMMKM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/MicheloniZCKT00,
author = {Rino Micheloni and
Matteo Zammattio and
Giovanni Campardo and
Osama Khouri and
Guido Torelli},
title = {Hierarchical Sector Biasing Organization for Flash Memories},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {29--33},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868612},
doi = {10.1109/MTDT.2000.868612},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/MicheloniZCKT00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/NiggemeyerRR00,
author = {Dirk Niggemeyer and
Elizabeth M. Rudnick and
Michael Redeker},
title = {Diagnostic Testing of Embedded Memories Based on Output Tracing},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {113--118},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868624},
doi = {10.1109/MTDT.2000.868624},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/NiggemeyerRR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Rajkanan00,
author = {Kamal Rajkanan},
title = {Yield Analysis Methodology for Low Defectivity Wafer Fabs},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {65--72},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868617},
doi = {10.1109/MTDT.2000.868617},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Rajkanan00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/RedekerRLN00,
author = {Michael Redeker and
Markus Rudack and
Thomas Lobbe and
Dirk Niggemeyer},
title = {Using GLFSRs for Pseudo-Random Memory {BIST}},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {85--94},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868620},
doi = {10.1109/MTDT.2000.868620},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/RedekerRLN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Shiue00,
author = {Wen{-}Tsong Shiue},
title = {Optimizing Memory Bandwidth with {ILP} Based Memory Exploration and
Assignment for Low Power Embedded Systems},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {95--100},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868621},
doi = {10.1109/MTDT.2000.868621},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Shiue00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Truong00,
author = {Khoan Truong},
title = {A Simple Built-In Self Test For Dual Ported SRAMs},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {79--84},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868619},
doi = {10.1109/MTDT.2000.868619},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Truong00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Vollrath00,
author = {J{\"{o}}rg E. Vollrath},
title = {Synchronous Dynamic Memory Test Construction: {A} Field Approach},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {59--64},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868616},
doi = {10.1109/MTDT.2000.868616},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Vollrath00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/YangM00,
author = {Zemo Yang and
Samiha Mourad},
title = {Crosstalk in Deep Submicron DRAMs},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {125--130},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868626},
doi = {10.1109/MTDT.2000.868626},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/YangM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ZarrinehAD00,
author = {Kamran Zarrineh and
R. Dean Adams and
Aneesha P. Deo},
title = {Defect Analysis and Realistic Fault Model Extensions for Static Random
Access Memories},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {119--124},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868625},
doi = {10.1109/MTDT.2000.868625},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ZarrinehAD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ZhangBH00,
author = {Ruili Zhang and
William C. Black Jr. and
Marwan M. Hassoun},
title = {Windowed {MRAM} Sensing Scheme},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {47--58},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868615},
doi = {10.1109/MTDT.2000.868615},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ZhangBH00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ZhaoML00,
author = {Jun Zhao and
Fred J. Meyer and
Fabrizio Lombardi},
title = {Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under
Restricted and General Fault Models},
booktitle = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
pages = {14--19},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/MTDT.2000.868610},
doi = {10.1109/MTDT.2000.868610},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ZhaoML00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtdt/2000,
title = {8th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2000), 7-8 August 2000, San Jose, CA, {USA}},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://ieeexplore.ieee.org/xpl/conhome/6973/proceeding},
isbn = {0-7695-0689-5},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/2000.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/BirkEC99,
author = {Gershom Birk and
Duncan G. Elliott and
Bruce F. Cockburn},
title = {A Comparative Simulation Study of Four Multilevel DRAMs},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {102--109},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782690},
doi = {10.1109/MTDT.1999.782690},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/BirkEC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/BrehobE99,
author = {Mark Brehob and
Richard J. Enbody},
title = {The Potential of Carbon-Based Memory Systems},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {110--114},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782691},
doi = {10.1109/MTDT.1999.782691},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/BrehobE99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/BrownCGJH99,
author = {Sue Brown and
Jeff Campbell and
Sherri Griffin and
Dick James and
Ray Haythornthwaite},
title = {Failure Mechanisms Detected in Memory Chips during Routine Construction
Analysis},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {34--39},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782681},
doi = {10.1109/MTDT.1999.782681},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/BrownCGJH99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/CoraorLHD99,
author = {Luke Roth and
Lee D. Coraor and
David L. Landis and
Paul T. Hulina and
Scott Deno},
title = {Computing in Memory Architectures for Digital Image Processing},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {8--15},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782678},
doi = {10.1109/MTDT.1999.782678},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/CoraorLHD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/FenstermakerKLN99,
author = {Larry Fenstermaker and
Ilyoung Kim and
Jim L. Lewandowski and
Jeffrey J. Nagy},
title = {Built In Self Test for Ring Addressed FIFOs with Transparent Latches},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {72--77},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782686},
doi = {10.1109/MTDT.1999.782686},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/FenstermakerKLN99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Khubchandani99,
author = {Raju Khubchandani},
title = {A Fast Test to Generate Flash Memory Threshold Voltage Distribution
Map},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {78--82},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782687},
doi = {10.1109/MTDT.1999.782687},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Khubchandani99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/LipovskiY99,
author = {G. Jack Lipovski and
Clement T. Yu},
title = {The Dynamic Associative Access Memory Chip and Its Application to
{SIMD} Processing and Full-Text Database Retrieval},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {24},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782680},
doi = {10.1109/MTDT.1999.782680},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/LipovskiY99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Malone99,
author = {Doug Malone},
title = {Design Validation of .18 um 1 Ghz Cache and Register Arrays},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {54},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782684},
doi = {10.1109/MTDT.1999.782684},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Malone99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Margala99,
author = {Martin Margala},
title = {Low Power SRAMs for Battery Operation},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {6},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.ieeecomputersociety.org/10.1109/MTDT.1999.10000},
doi = {10.1109/MTDT.1999.10000},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Margala99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Margala99a,
author = {Martin Margala},
title = {Low-Power {SRAM} Circuit Design},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {115--122},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782692},
doi = {10.1109/MTDT.1999.782692},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Margala99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Prince99,
author = {Betty Prince},
title = {A Tribute to Graphics Drams},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {123},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782693},
doi = {10.1109/MTDT.1999.782693},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Prince99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/RhodesW99,
author = {David L. Rhodes and
Wayne H. Wolf},
title = {Unbalanced Cache Systems},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {16--23},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782679},
doi = {10.1109/MTDT.1999.782679},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/RhodesW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/SegalBCKHS99,
author = {Julie D. Segal and
Sergei Bakarian and
Jonathon E. Colburn and
Madan Kumar and
Chang Hong and
Alex Shubat},
title = {Determining Redundancy Requirements for Memory Arrays with Critical
Area Analysis},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {48--53},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782683},
doi = {10.1109/MTDT.1999.782683},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/SegalBCKHS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Sidorowicz99,
author = {Piotr R. Sidorowicz},
title = {Modeling and Testing Transistor Faults in Content-Addressable Memories},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {83--90},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782688},
doi = {10.1109/MTDT.1999.782688},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Sidorowicz99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/VeldeG99,
author = {Daniel P. Van der Velde and
Ad J. van de Goor},
title = {Designing a Memory Module Tester},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {91},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782689},
doi = {10.1109/MTDT.1999.782689},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/VeldeG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/Vollrath99,
author = {J{\"{o}}rg E. Vollrath},
title = {Tutorial: Characterizing {SDRAMS}},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {62},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782685},
doi = {10.1109/MTDT.1999.782685},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/Vollrath99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/ZhaoML99,
author = {Jun Zhao and
Fred J. Meyer and
Fabrizio Lombardi},
title = {Interconnect Diagnosis of Bus-Connected Multi-RAM Systems},
booktitle = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
pages = {40--47},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/MTDT.1999.782682},
doi = {10.1109/MTDT.1999.782682},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/ZhaoML99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtdt/1999,
title = {7th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} '99), August 9-10, 1999, San Jose, CA, {USA}},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://ieeexplore.ieee.org/xpl/conhome/6351/proceeding},
isbn = {0-7695-0259-8},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtdt/1999.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
retrieved on 2024-04-23 20:14 CEST from data curated by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
