Search dblp for Publications

export results for "stream:streams/conf/vdat:"

 download as .bib file

@inproceedings{DBLP:conf/vdat/Acharya0BC19,
  author    = {Moumita Acharya and
               Samik Basu and
               Biranchi Narayan Behera and
               Amlan Chakrabarti},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Approximate Computing Based Adder Design for {DWT} Application},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {150--163},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_13},
  doi       = {10.1007/978-981-32-9767-8\_13},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/Acharya0BC19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AgrawalDGTM19,
  author    = {Purvi Agrawal and
               Ruchi Dhamnani and
               Ananya Garg and
               Shrivishal Tripathi and
               Manoj Kumar Majumder},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {An Efficient Wireless Charging Technique Using Inductive and Resonant
               Circuits},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {164--170},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_14},
  doi       = {10.1007/978-981-32-9767-8\_14},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AgrawalDGTM19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AmbulkerMN19,
  author    = {Sunanda Ambulker and
               Jitendra Kumar Mishra and
               Sangeeta Nakhate},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A {CMOS} Low Noise Amplifier with Improved Gain},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {215--223},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_19},
  doi       = {10.1007/978-981-32-9767-8\_19},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AmbulkerMN19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AmuruZA19,
  author    = {Deepthi Amuru and
               Andleeb Zahra and
               Zia Abbas},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Statistical Variation Aware Leakage and Total Power Estimation of
               16 nm {VLSI} Digital Circuits Based on Regression Models},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {565--578},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_47},
  doi       = {10.1007/978-981-32-9767-8\_47},
  timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AmuruZA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AryaRP019,
  author    = {Neelam Arya and
               Anil Kumar Rajput and
               Manisha Pattanaik and
               G. K. Sharma},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Quality Driven Energy Aware Approximated Core Transform Architecture
               for {HEVC} Standard},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {398--412},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_34},
  doi       = {10.1007/978-981-32-9767-8\_34},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AryaRP019.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BajpaiGC19,
  author    = {Govind Bajpai and
               Aniket Gupta and
               Nitanshu Chauhan},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Real Time Implementation of Convolutional Neural Network to Detect
               Plant Diseases Using Internet of Things},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {510--522},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_42},
  doi       = {10.1007/978-981-32-9767-8\_42},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BajpaiGC19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BansalK19,
  author    = {Rajul Bansal and
               Abhijit Karmakar},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Efficient Closely-Coupled Integration of {AES} Coprocessor with {LEON3}
               Processor},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {345--356},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_30},
  doi       = {10.1007/978-981-32-9767-8\_30},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BansalK19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Basiri19,
  author    = {M. Mohamed Asan Basiri},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Flexible Adaptive {FIR} Filter Designs Using {LMS} Algorithm},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {61--71},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_6},
  doi       = {10.1007/978-981-32-9767-8\_6},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Basiri19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Basiri19a,
  author    = {M. Mohamed Asan Basiri},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Asynchronous Hardware Design for Floating Point Multiply-Accumulate
               Circuit},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {247--257},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_22},
  doi       = {10.1007/978-981-32-9767-8\_22},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Basiri19a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BeoharRRVSRV19,
  author    = {Ankur Beohar and
               Gopal Raut and
               Gunjan Rajput and
               Abhinav Vishwakarma and
               Ambika Prasad Shah and
               Bhupendra Singh Reniwal and
               Santosh Kumar Vishvakarma},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Compact Spiking Neural Network System with SiGe Based Cylindrical
               Tunneling Transistor for Low Power Applications},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {655--663},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_54},
  doi       = {10.1007/978-981-32-9767-8\_54},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BeoharRRVSRV19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BhanuKAJC19,
  author    = {P. Veda Bhanu and
               Pranav Venkatesh Kulkarni and
               Sai Pranavi Avadhanam and
               Soumya J. and
               Linga Reddy Cenkeramaddi},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Multi-application Based Fault-Tolerant Network-on-Chip Design for
               Mesh Topology Using Reconfigurable Architecture},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {442--454},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_37},
  doi       = {10.1007/978-981-32-9767-8\_37},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BhanuKAJC19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BhoiMCA19,
  author    = {Bandan Kumar Bhoi and
               Neeraj Kumar Misra and
               Shailesh Singh Chouhan and
               Sarthak Acharya},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Analyzing Design Parameters of Nano-Magnetic Technology Based Converter
               Circuit},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {36--46},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_4},
  doi       = {10.1007/978-981-32-9767-8\_4},
  timestamp = {Sun, 09 Feb 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BhoiMCA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BoranYI19,
  author    = {Nirmal Kumar Boran and
               Dinesh Kumar Yadav and
               Rishabh Iyer},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA
               Multi-core Architectures},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {702--715},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_58},
  doi       = {10.1007/978-981-32-9767-8\_58},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BoranYI19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasCC19,
  author    = {Chandan Das and
               Sarit Chakraborty and
               Susanta Chakraborty},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {An Efficient Test and Fault Tolerance Technique for Paper-Based {DMFB}},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {72--86},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_7},
  doi       = {10.1007/978-981-32-9767-8\_7},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasCC19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DattaAKRRB19,
  author    = {Debanjana Datta and
               Sweta Agarwal and
               Vikash Kumar and
               Mayank Raj and
               Baidyanath Ray and
               Ayan Banerjee},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {47--60},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_5},
  doi       = {10.1007/978-981-32-9767-8\_5},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DattaAKRRB19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DuttaMDP19,
  author    = {Amartya Dutta and
               Riya Majumder and
               Debasis Dhal and
               Rajat Kumar Pal},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A Generalized Technique of Automated Pin Sharing on Hexagonal Electrode
               Based Digital Microfluidic Biochip Along with Its Design Methodology},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {87--101},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_8},
  doi       = {10.1007/978-981-32-9767-8\_8},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DuttaMDP19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DwivediSV19,
  author    = {Varun Kumar Dwivedi and
               Madhvi Sharma and
               Chandaka Venu},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Automations and Methodologies for Efficient and Quality Conscious
               Analog Layout Implementation},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {3--13},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_1},
  doi       = {10.1007/978-981-32-9767-8\_1},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DwivediSV19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GaggaturC19,
  author    = {Javed S. Gaggatur and
               Abhishek Chaturvedi},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A 1.25-20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes
               Application},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {23--35},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_3},
  doi       = {10.1007/978-981-32-9767-8\_3},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GaggaturC19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GangurdeK19,
  author    = {Saurabh Gangurde and
               Binod Kumar},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A Unified Methodology for Hardware Obfuscation and {IP} Watermarking},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {258--271},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_23},
  doi       = {10.1007/978-981-32-9767-8\_23},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GangurdeK19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GoswamiCS19,
  author    = {Mrinal Goswami and
               Mayukh Roy Choudhury and
               Bibhash Sen},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot
               Cellular Automata},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {455--467},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_38},
  doi       = {10.1007/978-981-32-9767-8\_38},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GoswamiCS19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GoyalA19,
  author    = {Harshil Goyal and
               Vishwani D. Agrawal},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Technology Characterization Model and Scaling for Energy Management},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {679--693},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_56},
  doi       = {10.1007/978-981-32-9767-8\_56},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GoyalA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuptaGKVV19,
  author    = {Neha Gupta and
               Tanisha Gupta and
               Sajid Khan and
               Abhinav Vishwakarma and
               Santosh Kumar Vishvakarma},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Low Leakage Highly Stable Robust Ultra Low Power 8T {SRAM} Cell},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {643--654},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_53},
  doi       = {10.1007/978-981-32-9767-8\_53},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GuptaGKVV19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuptaPKRV19,
  author    = {Neha Gupta and
               Jitesh Prasad and
               Rana Sagar Kumar and
               Gunjan Rajput and
               Santosh Kumar Vishvakarma},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T
               {SRAM} Cell},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {630--642},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_52},
  doi       = {10.1007/978-981-32-9767-8\_52},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GuptaPKRV19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/HotaS19,
  author    = {Aditya Kumar Hota and
               Kabiraj Sethi},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Design of 635 MHz Bandpass Filter Using High-Q Floating Active Inductor},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {115--125},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_10},
  doi       = {10.1007/978-981-32-9767-8\_10},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/HotaS19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KammariP19,
  author    = {Raviteja Kammari and
               Vijaya Sankara Rao Pasupureddi},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A Widely Linear, Power Efficient, Charge Controlled Delay Element
               for Multi-phase Clock Generation in 1.2 V, 65 nm {CMOS}},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {202--214},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_18},
  doi       = {10.1007/978-981-32-9767-8\_18},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KammariP19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KhanGRRPV19,
  author    = {Sajid Khan and
               Neha Gupta and
               Gopal Raut and
               Gunjan Rajput and
               Jai Gopal Pandey and
               Santosh Kumar Vishvakarma},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {An Ultra Low Power {AES} Architecture for IoT},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {334--344},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_29},
  doi       = {10.1007/978-981-32-9767-8\_29},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KhanGRRPV19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KhanGVCPV19,
  author    = {Sajid Khan and
               Neha Gupta and
               Abhinav Vishvakarma and
               Shailesh Singh Chouhan and
               Jai Gopal Pandey and
               Santosh Kumar Vishvakarma},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Dual-Edge Triggered Lightweight Implementation of {AES} for IoT Security},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {298--307},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_26},
  doi       = {10.1007/978-981-32-9767-8\_26},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KhanGVCPV19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumbharePM19,
  author    = {Vijay Rao Kumbhare and
               Punya Prasanna Paltani and
               Manoj Kumar Majumder},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Novel Approach for Improved Signal Integrity and Power Dissipation
               Using {MLGNR} Interconnects},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {617--629},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_51},
  doi       = {10.1007/978-981-32-9767-8\_51},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumbharePM19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KuntharaNJSWJ19,
  author    = {Rose George Kunthara and
               K. Neethu and
               Rekha K. James and
               Simi Zerine Sleeba and
               Tripti S. Warrier and
               John Jose},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {2L-2D Routing for Buffered Mesh Network-on-Chip},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {308--320},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_27},
  doi       = {10.1007/978-981-32-9767-8\_27},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KuntharaNJSWJ19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/LouisP19,
  author    = {Victor Jeffry Louis and
               Jai Gopal Pandey},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A Novel Design of {SRAM} Using Memristors at 45 nm Technology},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {579--589},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_48},
  doi       = {10.1007/978-981-32-9767-8\_48},
  timestamp = {Mon, 13 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/LouisP19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Majumdar19,
  author    = {Swatilekha Majumdar},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep
               Sub-micron Technology},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {171--179},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_15},
  doi       = {10.1007/978-981-32-9767-8\_15},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Majumdar19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ManasaN19,
  author    = {Sistla Lakshmi Manasa and
               G. Lakshmi Narayanan},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A Latency and Throughput Efficient Successive Cancellation Decoding
               of Polar Codes},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {741--748},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_61},
  doi       = {10.1007/978-981-32-9767-8\_61},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ManasaN19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MekkattillamMM19,
  author    = {Yadukrishnan Mekkattillam and
               Satyajit Mohapatra and
               Nihar R. Mohapatra},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Design and Calibration of 14-bit 10 KS/s Low Power {SAR} {ADC} for
               Bio-medical Applications},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {590--604},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_49},
  doi       = {10.1007/978-981-32-9767-8\_49},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MekkattillamMM19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MohanMD19,
  author    = {Arun Mohan and
               Saroj Mondal and
               Surya Shankar Dan},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {On-Chip Threshold Compensated Voltage Doubler for {RF} Energy Harvesting},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {180--189},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_16},
  doi       = {10.1007/978-981-32-9767-8\_16},
  timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MohanMD19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MondalBSPBR19,
  author    = {Bappaditya Mondal and
               Anirban Bhattacharjee and
               Subham Saha and
               Shalini Parekh and
               Chandan Bandyopadhyay and
               Hafizur Rahaman},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {An Approach for Detection of Node Displacement Fault {(NDF)} in Reversible
               Circuit},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {605--616},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_50},
  doi       = {10.1007/978-981-32-9767-8\_50},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MondalBSPBR19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MongaC19,
  author    = {Kanika Monga and
               Nitin Chaturvedi},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A {CMOS/MTJ} Based Novel Non-volatile {SRAM} Cell with Asynchronous
               Write Termination for Normally {OFF} Applications},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {553--564},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_46},
  doi       = {10.1007/978-981-32-9767-8\_46},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MongaC19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NairP19,
  author    = {Devika R. Nair and
               A. Purushothaman},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Brain Inspired One Shot Learning Method for {HD} Computing},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {286--297},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_25},
  doi       = {10.1007/978-981-32-9767-8\_25},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NairP19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PalK19,
  author    = {Shagun Pal and
               Brijesh Kumar},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Low-Voltage Dual-Gate Organic Thin Film Transistors with Distinctly
               Placed Source and Drain},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {727--738},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_60},
  doi       = {10.1007/978-981-32-9767-8\_60},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PalK19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PanigrahiJK19,
  author    = {Priyanka Panigrahi and
               Rajesh Kumar Jha and
               Chandan Karfa},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {User Guided Register Manipulation in Digital Circuits},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {468--481},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_39},
  doi       = {10.1007/978-981-32-9767-8\_39},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PanigrahiJK19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PariharG19,
  author    = {Shivendra Singh Parihar and
               Ramchandra Gurjar},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Compact Modeling of Drain-Extended {MOS} Transistor Using {BSIM-BULK}
               Model},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {667--678},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_55},
  doi       = {10.1007/978-981-32-9767-8\_55},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PariharG19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PokharaMP19,
  author    = {Ankur Pokhara and
               Biswajit Mishra and
               Purvi Patel},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {All-Digital {CMOS} On-Chip Temperature Sensor with Time-Assisted Analytical
               Model},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {749--763},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_62},
  doi       = {10.1007/978-981-32-9767-8\_62},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PokharaMP19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RaghunathSGKT19,
  author    = {K. P. Raghunath and
               K. V. Manu Sagar and
               T. Gokulan and
               Kundan Kumar and
               Chetan Singh Thakur},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {{ASIC} Based {LVDT} Signal Conditioner for High-Accuracy Measurements},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {385--397},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_33},
  doi       = {10.1007/978-981-32-9767-8\_33},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RaghunathSGKT19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RautBRKBV19,
  author    = {Gopal Raut and
               Vishal Bhartiy and
               Gunjan Rajput and
               Sajid Khan and
               Ankur Beohar and
               Santosh Kumar Vishvakarma},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Efficient Low-Precision {CORDIC} Algorithm for Hardware Implementation
               of Artificial Neural Network},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {321--333},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_28},
  doi       = {10.1007/978-981-32-9767-8\_28},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RautBRKBV19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RaveendranJMVS19,
  author    = {Aneesh Raveendran and
               Sandra Jean and
               J. Mervin and
               D. Vivian and
               A. David Selvakumar},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {{RISC-V} Half Precision Floating Point Instruction Set Extensions
               and Co-processor},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {482--495},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_40},
  doi       = {10.1007/978-981-32-9767-8\_40},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RaveendranJMVS19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RaveendranKVS19,
  author    = {Aneesh Raveendran and
               Vinay Kumar and
               D. Vivian and
               David Selvakumar},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Functional Simulation Verification of {RISC-V} Instruction Set Based
               High Level Language Modeled {FPU}},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {496--509},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_41},
  doi       = {10.1007/978-981-32-9767-8\_41},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RaveendranKVS19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ReddyR19,
  author    = {M. Mahendra Reddy and
               Sounak Roy},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive
               Approximation Register {ADC}},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {141--149},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_12},
  doi       = {10.1007/978-981-32-9767-8\_12},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ReddyR19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RekhaS19,
  author    = {S. Shanthi Rekha and
               P. Saravanan},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Threshold Implementation of a Low-Cost {CLEFIA-128} Cipher for Power
               Analysis Attack Resistance},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {272--285},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_24},
  doi       = {10.1007/978-981-32-9767-8\_24},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RekhaS19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RoyDD19,
  author    = {Sayantani Roy and
               Arighna Deb and
               Debesh K. Das},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Delay Efficient All Optical Carry Lookahead Adder},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {236--244},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_21},
  doi       = {10.1007/978-981-32-9767-8\_21},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RoyDD19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SabirJNN19,
  author    = {Anam Sabir and
               Anushree Jain and
               Yashwini Nathwani and
               Vaibhav Neema},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Intelligent Traffic Light Controller: {A} Solution for Smart City
               Traffic Problem},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {764--772},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_63},
  doi       = {10.1007/978-981-32-9767-8\_63},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SabirJNN19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShahMW19,
  author    = {Ambika Prasad Shah and
               Amirhossein Moshrefi and
               Michael Waltl},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Utilizing {NBTI} for Operation Detection of Integrated Circuits},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {190--201},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_17},
  doi       = {10.1007/978-981-32-9767-8\_17},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ShahMW19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaD19,
  author    = {Priyamvada Sharma and
               Bishnu Prasad Das},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power
               for Near-Threshold Designs},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {371--382},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_32},
  doi       = {10.1007/978-981-32-9767-8\_32},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SharmaD19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SiddamalSHI19,
  author    = {Saroja V. Siddamal and
               Suhas B. Shirol and
               Shraddha Hiremath and
               Nalini C. Iyer},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Design and Physical Implementation of Mixed Signal Elapsed Time Counter
               in 0.18 {\(\mathrm{\mu}\)}m {CMOS} Technology},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {126--140},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_11},
  doi       = {10.1007/978-981-32-9767-8\_11},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SiddamalSHI19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghGB19,
  author    = {Kamini Singh and
               R. S. Gamad and
               P. P. Bansod},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Design and Analysis for Power Reduction with High {SNM} of 10T {SRAM}
               Cell},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {541--549},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_45},
  doi       = {10.1007/978-981-32-9767-8\_45},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghGB19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghSSP19,
  author    = {Anushka Singh and
               Yash Sharma and
               Arvind Sharma and
               Archana Pandey},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A Novel 20nm FinFET Based 10T {SRAM} Cell Design for Improved Performance},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {523--531},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_43},
  doi       = {10.1007/978-981-32-9767-8\_43},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghSSP19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SulthanCGT19,
  author    = {Muneeb Sulthan and
               Shubhajit Roy Chowdury and
               Rajnish Garg and
               Alok Tripathi},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Design of a Power Efficient Pulse Latch Circuit as a Solution for
               Master Slave Flip-Flop},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {532--540},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_44},
  doi       = {10.1007/978-981-32-9767-8\_44},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SulthanCGT19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SunithaM19,
  author    = {Archana Sunitha and
               Bhaskar Manickam},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E
               Differential Power Amplifier},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {14--22},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_2},
  doi       = {10.1007/978-981-32-9767-8\_2},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SunithaM19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SwainKP19,
  author    = {Jyotiranjan Swain and
               Rajesh Kolluri and
               Sumanta Pyne},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {A Space Efficient Greedy Droplet Routing for Digital Microfluidics
               Biochip},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {102--114},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_9},
  doi       = {10.1007/978-981-32-9767-8\_9},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SwainKP19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/TankwalNK19,
  author    = {Piyush Tankwal and
               Vikas Nehra and
               Brajesh Kumar Kaushik},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Comparative Analysis of Logic Gates Based on Spin Transfer Torque
               {(STT)} and Differential Spin Hall Effect {(DSHE)} Switching Mechanisms},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {428--441},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_36},
  doi       = {10.1007/978-981-32-9767-8\_36},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/TankwalNK19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/VermaK19,
  author    = {Avinash Verma and
               Gaurav Kaushal},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Radiation Hardened by Design Sense Amplifier},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {224--235},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_20},
  doi       = {10.1007/978-981-32-9767-8\_20},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/VermaK19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/VineeshKA19,
  author    = {V. S. Vineesh and
               Binod Kumar and
               Jay Adhaduk},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Identification of Effective Guidance Hints for Better Design Debugging
               by Formal Methods},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {413--427},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_35},
  doi       = {10.1007/978-981-32-9767-8\_35},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/VineeshKA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/YadavRSB19,
  author    = {Shivendra Yadav and
               Chithraja Rajan and
               Dheeraj Sharma and
               Sanjay Balotiya},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel {FET}},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {694--701},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_57},
  doi       = {10.1007/978-981-32-9767-8\_57},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/YadavRSB19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/YempadaJ19,
  author    = {Venkata Appa Rao Yempada and
               Srivatsava Jandhyala},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Simulation Study of {III-V} Lateral Tunnel FETs with Gate-Drain Underlap},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {716--726},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_59},
  doi       = {10.1007/978-981-32-9767-8\_59},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/YempadaJ19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/YousufBS19,
  author    = {Shah Zahid Yousuf and
               Anil Kumar Bhardwaj and
               Rohit Sharma},
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {Investigating the Role of Parasitic Resistance in a Class of Nanoscale
               Interconnects},
  booktitle = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  pages     = {357--370},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8\_31},
  doi       = {10.1007/978-981-32-9767-8\_31},
  timestamp = {Wed, 21 Aug 2019 13:24:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/YousufBS19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vdat/2018,
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-13-5950-7},
  doi       = {10.1007/978-981-13-5950-7},
  isbn      = {978-981-13-5949-1},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/2018.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vdat/2019,
  editor    = {Anirban Sengupta and
               Sudeb Dasgupta and
               Virendra Singh and
               Rohit Sharma and
               Santosh Kumar Vishvakarma},
  title     = {{VLSI} Design and Test - 23rd International Symposium, {VDAT} 2019,
               Indore, India, July 4-6, 2019, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {1066},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-981-32-9767-8},
  doi       = {10.1007/978-981-32-9767-8},
  isbn      = {978-981-32-9766-1},
  timestamp = {Wed, 21 Aug 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/2019.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AbbasZO18,
  author    = {Zia Abbas and
               Andleeb Zahra and
               Mauro Olivieri},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {{LEADER:} Leakage Currents Estimation Technique for Aging Degradation
               Aware 16 nm {CMOS} Circuits},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {394--407},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_34},
  doi       = {10.1007/978-981-13-5950-7\_34},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/AbbasZO18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AgarwalHBM18,
  author    = {Shantanu Agarwal and
               G. Harish and
               S. Balamurugan and
               R. Marimuthu},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {49--60},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_5},
  doi       = {10.1007/978-981-13-5950-7\_5},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/AgarwalHBM18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AliJA18,
  author    = {Ashfakh Ali and
               Arpan Jain and
               Zia Abbas},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Voltage Level Adapter Design for High Voltage Swing Applications in
               {CMOS} Differential Amplifier},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {130--139},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_12},
  doi       = {10.1007/978-981-13-5950-7\_12},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/AliJA18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BasiriS18,
  author    = {M. Mohamed Asan Basiri and
               Sandeep K. Shukla},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Efficient Hardware-Software Codesigns of {AES} Encryptor and {RS-BCH}
               Encoder},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {3--15},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_1},
  doi       = {10.1007/978-981-13-5950-7\_1},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BasiriS18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BhattacharjeeBB18,
  author    = {Anirban Bhattacharjee and
               Chandan Bandyopadhyay and
               Laxmidhar Biswal and
               Hafizur Rahaman},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Heuristic Qubit Placement Strategy for Nearest Neighbor Realization
               in 2D Architecture},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {593--605},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_49},
  doi       = {10.1007/978-981-13-5950-7\_49},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BhattacharjeeBB18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BiswalBDTR18,
  author    = {Laxmidhar Biswal and
               Anirban Bhattacharjee and
               Rakesh Das and
               Gopinath Thirunavukarasu and
               Hafizur Rahaman},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Quantum Domain Design of Clifford+T-Based Bidirectional Barrel Shifter},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {606--618},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_50},
  doi       = {10.1007/978-981-13-5950-7\_50},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BiswalBDTR18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/CHRKK18,
  author    = {Naga Raghuram CH and
               D. Manohar Reddy and
               Puli Kishore Kumar and
               Gaurav Kaushal},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Robust {SRAM} Cell Development for Single-Event Multiple Effects},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {335--347},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_29},
  doi       = {10.1007/978-981-13-5950-7\_29},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/CHRKK18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChauhanJJM18,
  author    = {Sandeep Singh Chauhan and
               Niharika J and
               M. M. Joglekar and
               Sanjeev Kumar Manhas},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Fabrication of Molybdenum MEMs Structures Using Dry and Wet Etching},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {254--263},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_22},
  doi       = {10.1007/978-981-13-5950-7\_22},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ChauhanJJM18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChothaniM18,
  author    = {Chintanika Chothani and
               Biswajit Mishra},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Fully Digital, Low Energy Capacitive Sensor Interface with an Auto-calibration
               Unit},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {657--669},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_54},
  doi       = {10.1007/978-981-13-5950-7\_54},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ChothaniM18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChoubeyKM18,
  author    = {Balkrishna Choubey and
               Vijay Rao Kumbhare and
               Manoj Kumar Majumder},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Performance Analysis of Graphene Based Optical Interconnect at Nanoscale
               Technology},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {418--429},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_36},
  doi       = {10.1007/978-981-13-5950-7\_36},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ChoubeyKM18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DharRG18,
  author    = {Tapobrata Dhar and
               Surajit Kumar Roy and
               Chandan Giri},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Detecting Hardware Trojans by Reducing Rarity of Transitions in ICs},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {173--185},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_15},
  doi       = {10.1007/978-981-13-5950-7\_15},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/DharRG18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DhuleP18,
  author    = {Sagar B. Dhule and
               Vasu Pulijala},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Novel {RF} {MEMS} Capacitive Switch for Lower Actuation Voltage},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {285--294},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_25},
  doi       = {10.1007/978-981-13-5950-7\_25},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/DhuleP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GiftaRFA18,
  author    = {G. Gifta and
               D. Gracia Nirmala Rani and
               Nifasath Farhana and
               R. Archana},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Design of {CMOS} Based Biosensor for Implantable Medical Devices},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {695--704},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_57},
  doi       = {10.1007/978-981-13-5950-7\_57},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GiftaRFA18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GoswamiRNS18,
  author    = {Mrinal Goswami and
               Govind Raj and
               Aron Narzary and
               Bibhash Sen},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Methodology to Design Online Testable Reversible Circuits},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {322--334},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_28},
  doi       = {10.1007/978-981-13-5950-7\_28},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GoswamiRNS18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuhaSC18,
  author    = {Krishnendu Guha and
               Debasri Saha and
               Amlan Chakrabarti},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {{SARP:} Self Aware Runtime Protection Against Integrity Attacks of
               Hardware Trojans},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {198--209},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_17},
  doi       = {10.1007/978-981-13-5950-7\_17},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GuhaSC18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuptaKA18,
  author    = {Prateek Gupta and
               Shubham Kumar and
               Zia Abbas},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage
               Power},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {88--99},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_8},
  doi       = {10.1007/978-981-13-5950-7\_8},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GuptaKA18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuptaSP18,
  author    = {Vinay Gupta and
               Pratiksha Shukla and
               Manisha Pattanaik},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Low Leakage Noise Tolerant 10T {SRAM} Cell},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {538--550},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_45},
  doi       = {10.1007/978-981-13-5950-7\_45},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GuptaSP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KaibarttaD18,
  author    = {Tanusree Kaibartta and
               Debesh Kumar Das},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Optimization of Test Wrapper Length for {TSV} Based 3D SOCs Using
               a Heuristic Approach},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {310--321},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_27},
  doi       = {10.1007/978-981-13-5950-7\_27},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KaibarttaD18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KalaJPM18,
  author    = {S. Kala and
               Babita R. Jose and
               Debdeep Paul and
               Jimson Mathew},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Hardware Accelerator for Convolutional Neural Network Using Fast
               Fourier Transform},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {28--36},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_3},
  doi       = {10.1007/978-981-13-5950-7\_3},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KalaJPM18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KashyapVKR18,
  author    = {Ravi Kashyap and
               Twinkle Verma and
               Priyanka Kwatra and
               Sidhartha Sankar Rout},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Efficient Data Compression Scheme for Secured Application Needs},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {221--230},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_19},
  doi       = {10.1007/978-981-13-5950-7\_19},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KashyapVKR18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KetavanyaD18,
  author    = {Dubakula Ketavanya and
               Anand D. Darji},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Automation of Timing Quality Checks and Optimization},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {348--356},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_30},
  doi       = {10.1007/978-981-13-5950-7\_30},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KetavanyaD18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KharePNC18,
  author    = {Ajay Khare and
               Chinmay Patil and
               Manikanta Nallamalli and
               Santanu Chattopadhyay},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time
               Communications in NoC},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {433--445},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_37},
  doi       = {10.1007/978-981-13-5950-7\_37},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KharePNC18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KhuushiJPD18,
  author    = {Khuushi and
               Vanadana Jain and
               Rajendra Patrikar and
               Raghavendra B. Deshmukh},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Real Time Mixing Index Measurement of Microchannels Using OpenCV},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {278--284},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_24},
  doi       = {10.1007/978-981-13-5950-7\_24},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KhuushiJPD18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KokkiligaddaGB18,
  author    = {Keerthi Sagar Kokkiligadda and
               Yogendra Gupta and
               Lava Bhargava},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Efficient and Failure Aware {ECC} for {STT-MRAM} Cache Memory},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {509--520},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_43},
  doi       = {10.1007/978-981-13-5950-7\_43},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KokkiligaddaGB18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KokkulaJD18,
  author    = {Vineysarathi Kokkula and
               Akash Joshi and
               Raghavendra B. Deshmukh},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Supply and Temperature Independent Voltage Reference Circuit in Subthreshold
               Region},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {109--120},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_10},
  doi       = {10.1007/978-981-13-5950-7\_10},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KokkulaJD18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ManivannanS18,
  author    = {T. S. Manivannan and
               Meena Srinivasan},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Novel Design Approach to Implement Multi-port Register Files Using
               Pulsed-Latches},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {521--537},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_44},
  doi       = {10.1007/978-981-13-5950-7\_44},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ManivannanS18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MidhulaBJJ18,
  author    = {K. S. Midhula and
               Sarath Babu and
               John Jose and
               Sangeetha Jose},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Performance Enhancement of NoCs Using Single Cycle Deflection Routers
               and Adaptive Priority Schemes},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {460--472},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_39},
  doi       = {10.1007/978-981-13-5950-7\_39},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/MidhulaBJJ18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MorankarP18,
  author    = {Amol Morankar and
               Rajendra Patrikar},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Effective Method for Temperature Compensation in Dual Band Metal {MEMS}
               Resonator},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {233--241},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_20},
  doi       = {10.1007/978-981-13-5950-7\_20},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/MorankarP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NagulapalliHBZY18,
  author    = {Rajasekhar Nagulapalli and
               Khaled Hayatleh and
               Steve Barker and
               Saddam Zourob and
               Nabil Yassine and
               B. Naresh Kumar Reddy},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A 31 ppm/{\textdegree} {C} Pure {CMOS} Bandgap Reference by Exploiting
               Beta-Multiplier},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {100--108},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_9},
  doi       = {10.1007/978-981-13-5950-7\_9},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/NagulapalliHBZY18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PMRBVRJ18,
  author    = {Akshay B. P. and
               Ganesh K. M. and
               Thippeswamy D. R. and
               Vishnu S. Bhat and
               Anitha Vijayakumar and
               Ananda Y. R. and
               John Jose},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Implementation of a Novel Fault Tolerant Routing Technique for Mesh
               Network on Chip},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {495--506},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_42},
  doi       = {10.1007/978-981-13-5950-7\_42},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PMRBVRJ18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PandeyGNMKVKS18,
  author    = {Jai Gopal Pandey and
               Tarun Goel and
               Mausam Nayak and
               Chhavi Mitharwal and
               Sajid Khan and
               Santosh Kumar Vishvakarma and
               Abhijit Karmakar and
               Raj Singh},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A {VLSI} Architecture for the {PRESENT} Block Cipher with {FPGA} and
               {ASIC} Implementations},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {210--220},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_18},
  doi       = {10.1007/978-981-13-5950-7\_18},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PandeyGNMKVKS18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PopatM18,
  author    = {Jayesh Popat and
               Usha Mehta},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Novel Countermeasure Against Differential Scan Attack in {AES} Algorithm},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {297--309},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_26},
  doi       = {10.1007/978-981-13-5950-7\_26},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PopatM18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PravinrajP18,
  author    = {T. Pravinraj and
               Rajendra Patrikar},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Fabrication and LBM-Modeling of Directional Fluid Transport on Low-Cost
               Electro-Osmotic Flow Device},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {643--656},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_53},
  doi       = {10.1007/978-981-13-5950-7\_53},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PravinrajP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PriyadharshniK18,
  author    = {M. Priyadharshni and
               Sundaram Kumaravel},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Comparative Exploration About Approximate Full Adders for Error
               Tolerant Applications},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {61--74},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_6},
  doi       = {10.1007/978-981-13-5950-7\_6},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PriyadharshniK18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PriyankaNR18,
  author    = {P. Priyanka and
               G. K. Nisarga and
               S. Raghuram},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {{CMOS} Implementations of Rectified Linear Activation Function},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {121--129},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_11},
  doi       = {10.1007/978-981-13-5950-7\_11},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PriyankaNR18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RaiAWTB18,
  author    = {Nishtha Rai and
               Vaibhav Agarwal and
               Nishtha Wadhwa and
               Bhawna Tiwari and
               Pydi Ganga Bahubalindruni},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Temperature Insensitive Low-Power Ring Oscillator Using only n-type
               Transistors},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {359--369},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_31},
  doi       = {10.1007/978-981-13-5950-7\_31},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/RaiAWTB18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RajeshKP18,
  author    = {Ammu Lakshmy Rajesh and
               Sanket V. Kadam and
               Rajendra Patrikar},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Complete Hardware Advent on {IEEE} 802.15.4 Based Mac Layer and
               a Comparison with Open-ZB},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {682--694},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_56},
  doi       = {10.1007/978-981-13-5950-7\_56},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/RajeshKP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RanjaniD18,
  author    = {Sree Ranjani Rajendran and
               M. Nirmala Devi},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Enhanced Logical Locking for a Secured Hardware {IP} Against Key-Guessing
               Attacks},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {186--197},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_16},
  doi       = {10.1007/978-981-13-5950-7\_16},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/RanjaniD18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RathodT18,
  author    = {Amit Rathod and
               Rajesh Thakker},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Parameter Extraction of {PSP} {MOSFET} Model Using Particle Swarm
               Optimization - SoC Approach},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {483--494},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_41},
  doi       = {10.1007/978-981-13-5950-7\_41},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/RathodT18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RaveendranDP18,
  author    = {Abhimanniu Raveendran and
               Sanjay B. Dhok and
               Rajendra Patrikar},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {High Level Synthesis and Implementation of Cryptographic Algorithm
               in {AHIR} Platform},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {16--27},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_2},
  doi       = {10.1007/978-981-13-5950-7\_2},
  timestamp = {Fri, 17 Apr 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RaveendranDP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ReddyS18,
  author    = {B. Naresh Kumar Reddy and
               Sireesha},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC)},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {631--640},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_52},
  doi       = {10.1007/978-981-13-5950-7\_52},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ReddyS18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SGRSKRJ18,
  author    = {Ajay S and
               Satya Sai Krishna Mohan G and
               Shashank S Rao and
               Sujay B Shaunak and
               Krutthika H. K and
               Ananda Y. R. and
               John Jose},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Source Hotspot Management in a Mesh Network on Chip},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {619--630},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_51},
  doi       = {10.1007/978-981-13-5950-7\_51},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SGRSKRJ18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SaravananM18,
  author    = {P. Saravanan and
               Babu M. Mehtre},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Novel Approach to Detect Hardware Malware Using Hamming Weight Model
               and One Class Support Vector Machine},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {159--172},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_14},
  doi       = {10.1007/978-981-13-5950-7\_14},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SaravananM18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShahUBJC18,
  author    = {Monil Shah and
               Mohit Upadhyay and
               P. Veda Bhanu and
               Soumya J. and
               Linga Reddy Cenkeramaddi},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {446--459},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_38},
  doi       = {10.1007/978-981-13-5950-7\_38},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ShahUBJC18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaBDCJV18,
  author    = {Vishal Sharma and
               Pranshu Bisht and
               Abhishek Dalal and
               Shailesh Singh Chouhan and
               H. S. Jattana and
               Santosh Kumar Vishvakarma},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Write-Improved Half-Select-Free Low-Power 11T Subthreshold {SRAM}
               with Double Adjacent Error Correction for {FPGA-LUT} Design},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {551--564},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_46},
  doi       = {10.1007/978-981-13-5950-7\_46},
  timestamp = {Mon, 22 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SharmaBDCJV18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaTBG18,
  author    = {Ashish Sharma and
               Manish Tailor and
               Lava Bhargava and
               Manoj Singh Gaur},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {3D {LBDR:} Logic-Based Distributed Routing for 3D NoC},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {473--482},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_40},
  doi       = {10.1007/978-981-13-5950-7\_40},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SharmaTBG18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShresthaS18,
  author    = {Rahul Shrestha and
               Ashutosh Sharma},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori
               Decoder for New Generation of Wireless Devices},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {37--48},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_4},
  doi       = {10.1007/978-981-13-5950-7\_4},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ShresthaS18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShuklaGP18,
  author    = {Pratiksha Shukla and
               Vinay Gupta and
               Manisha Pattanaik},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Low Leakage Read Write Enhanced 9T {SRAM} Cell},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {565--577},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_47},
  doi       = {10.1007/978-981-13-5950-7\_47},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ShuklaGP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShuklaTWBB18,
  author    = {Suprateek Shukla and
               Bhawna Tiwari and
               Nishtha Wadhwa and
               Pydi Ganga Bahubalindruni and
               Pedro Barquinha},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Low-Power Switched Operational Amplifier Using a-InGaZnO TFTs},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {370--379},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_32},
  doi       = {10.1007/978-981-13-5950-7\_32},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ShuklaTWBB18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghKSG18,
  author    = {Preeti Singh and
               Vandana Kumari and
               Manoj Saxena and
               Mridula Gupta},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Threshold Voltage Investigation of Recessed Dual-Gate {MISHEMT:} Simulation
               Study},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {380--393},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_33},
  doi       = {10.1007/978-981-13-5950-7\_33},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghKSG18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinharayDRR18,
  author    = {Arindam Sinharay and
               Subrata Das and
               Pranab Roy and
               Hafizur Rahaman},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {An Angular Steiner Tree Based Global Routing Algorithm for Graphene
               Nanoribbon Circuit},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {670--681},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_55},
  doi       = {10.1007/978-981-13-5950-7\_55},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SinharayDRR18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Sribhuvaneshwari18,
  author    = {H. Sribhuvaneshwari and
               K. Suthendran},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A Novel March {C2RR} Algorithm for Nanoelectronic Resistive Random
               Access Memory {(RRAM)} Testing},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {578--589},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_48},
  doi       = {10.1007/978-981-13-5950-7\_48},
  timestamp = {Fri, 03 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Sribhuvaneshwari18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SrishtiK18,
  author    = {Srishti and
               Jasmeet Kaur},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Performance Optimization of FinFET Configurations at 14 nm Technology
               Using {ANN-PSO}},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {408--417},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_35},
  doi       = {10.1007/978-981-13-5950-7\_35},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SrishtiK18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SrivastavaP18,
  author    = {Jagriti Srivastava and
               Rajendra Patrikar},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Continuous Flow Microfluidic Channel Design for Blood Plasma Separation},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {264--277},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_23},
  doi       = {10.1007/978-981-13-5950-7\_23},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SrivastavaP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/StefigrafR18,
  author    = {I. Stefigraf and
               S. Rajaram},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Layout Design of X-Band Low Noise Amplifier for Radar Applications},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {140--156},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_13},
  doi       = {10.1007/978-981-13-5950-7\_13},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/StefigrafR18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SwainP18,
  author    = {Jyotiranjan Swain and
               Sumanta Pyne},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Deadlock Detection in Digital Microfluidics Biochip Droplet Routing},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {242--253},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_21},
  doi       = {10.1007/978-981-13-5950-7\_21},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SwainP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ThoolDP18,
  author    = {Saket Thool and
               Raghavendra B. Deshmukh and
               Rajendra M. Patrikar},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {Design and Fabrication of Versatile Low Power Wireless Sensor Nodes
               for IoT Applications},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {705--719},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_58},
  doi       = {10.1007/978-981-13-5950-7\_58},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ThoolDP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/WadhwaBD18,
  author    = {Nishtha Wadhwa and
               Pydi Ganga Bahubalindruni and
               Sujay Deb},
  editor    = {S. Rajaram and
               N. B. Balamurugan and
               D. Gracia Nirmala Rani and
               Virendra Singh},
  title     = {A {PVT} Insensitive Low-Power Differential Ring Oscillator},
  booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
               Madurai, India, June 28-30, 2018, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {892},
  pages     = {77--87},
  publisher = {Springer},
  year      = {2018},
  url       = {https://doi.org/10.1007/978-981-13-5950-7\_7},
  doi       = {10.1007/978-981-13-5950-7\_7},
  timestamp = {Fri, 27 Mar 2020 08:58:30 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/WadhwaBD18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/0001BJPF17,
  author    = {Binod Kumar and
               Kanad Basu and
               Ankit Jindal and
               Brajesh Pandey and
               Masahiro Fujita},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A Formal Perspective on Effective Post-silicon Debug and Trace Signal
               Selection},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {753--766},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_71},
  doi       = {10.1007/978-981-10-7470-7\_71},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/0001BJPF17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AhlawatVTS17,
  author    = {Satyadev Ahlawat and
               Darshit Vaghani and
               Jaynarayan T. Tudu and
               Ashok Suhag},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A Cost Effective Technique for Diagnosis of Scan Chain Faults},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {191--204},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_20},
  doi       = {10.1007/978-981-10-7470-7\_20},
  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/AhlawatVTS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AinSD17,
  author    = {Antara Ain and
               Sayandeep Sanyal and
               Pallab Dasgupta},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A Framework for Automated Feature Based Mixed-Signal Equivalence Checking},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {779--791},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_73},
  doi       = {10.1007/978-981-10-7470-7\_73},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/AinSD17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AliG17,
  author    = {Naushad Ali and
               Bharat Garg},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {New Energy Efficient Reconfigurable {FIR} Filter Architecture and
               Its {VLSI} Implementation},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {519--532},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_51},
  doi       = {10.1007/978-981-10-7470-7\_51},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/AliG17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AswathyR0JJ17,
  author    = {N. S. Aswathy and
               R. S. Reshma Raj and
               Abhijit Das and
               John Jose and
               V. R. Josna},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Adaptive Packet Throttling Technique for Congestion Management in
               Mesh NoCs},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {337--344},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_33},
  doi       = {10.1007/978-981-10-7470-7\_33},
  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/AswathyR0JJ17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BansalJK17,
  author    = {Rajul Bansal and
               Mahendra Kumar Jatav and
               Abhijit Karmakar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A Lifting Instruction for Performing {DWT} in {LEON3} Processor Based
               System-on-Chip},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {731--736},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_68},
  doi       = {10.1007/978-981-10-7470-7\_68},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BansalJK17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BashirPP17,
  author    = {Mudasir Bashir and
               Sreehari Rao Patri and
               K. S. R. Krishna Prasad},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A Low Power, Frequency-to-Digital Converter {CMOS} Based Temperature
               Sensor in 65 nm Process},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {657--666},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_62},
  doi       = {10.1007/978-981-10-7470-7\_62},
  timestamp = {Fri, 12 Jan 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BashirPP17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BasiriS17,
  author    = {M. Mohamed Asan Basiri and
               Sandeep K. Shukla},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Flexible Composite Galois Field GF((2m)2) Multiplier Designs},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {3--14},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_1},
  doi       = {10.1007/978-981-10-7470-7\_1},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BasiriS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BasuKKK17,
  author    = {Kanad Basu and
               Rishi Kumar and
               Santosh Kulkarni and
               Rohit Kapur},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Deterministic Shift Power Reduction in Test Compression},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {155--167},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_17},
  doi       = {10.1007/978-981-10-7470-7\_17},
  timestamp = {Sun, 07 Jan 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BasuKKK17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BhardwajR17,
  author    = {Anshu Bhardwaj and
               Subir Kumar Roy},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Defeating HaTCh: Building Malicious {IP} Cores},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {345--353},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_34},
  doi       = {10.1007/978-981-10-7470-7\_34},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BhardwajR17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BhattacharyaRK17,
  author    = {Rahul Bhattacharya and
               S. H. M. Ragamai and
               Subindu Kumar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {{SFG} Based Fault Simulation of Linear Analog Circuits Using Fault
               Classification and Sensitivity Analysis},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {179--190},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_19},
  doi       = {10.1007/978-981-10-7470-7\_19},
  timestamp = {Fri, 12 Jan 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BhattacharyaRK17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChakrabortyDDP17,
  author    = {Arpan Chakraborty and
               Piyali Datta and
               Debasis Dhal and
               Rajat Kumar Pal},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A Dependability Preserving Fluid-Level Synthesis for Reconfigurable
               Droplet-Based Microfluidic Biochips},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {694--706},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_65},
  doi       = {10.1007/978-981-10-7470-7\_65},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ChakrabortyDDP17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChatterjeeRGR17,
  author    = {Subhajit Chatterjee and
               Surajit Kumar Roy and
               Chandan Giri and
               Hafizur Rahaman},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Modeling and Analysis of Transient Heat for 3D {IC}},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {365--375},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_36},
  doi       = {10.1007/978-981-10-7470-7\_36},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChatterjeeRGR17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChaudhuriBR17,
  author    = {Neha Chaudhuri and
               Chandan Bandyopadhyay and
               Hafizur Rahaman},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Improving the Design of Nearest Neighbor Quantum Circuits in 2D Space},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {421--426},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_42},
  doi       = {10.1007/978-981-10-7470-7\_42},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChaudhuriBR17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChoudhuryR17,
  author    = {Rituparna Choudhury and
               P. Rangababu},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Design and Implementation of Mixed Parallel and Dataflow Architecture
               for Intra-prediction Hardware in {HEVC} Decoder},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {742--750},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_70},
  doi       = {10.1007/978-981-10-7470-7\_70},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChoudhuryR17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChoudhuryS17,
  author    = {Avishek Choudhury and
               Biplab K. Sikdar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Performance Analysis of Disability Based Fault Tolerance Techniques
               for Permanent Faults in Chip Multiprocessors},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {217--224},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_22},
  doi       = {10.1007/978-981-10-7470-7\_22},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChoudhuryS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChoukseyKB17,
  author    = {Ramanuj Chouksey and
               Chandan Karfa and
               Purandar Bhaduri},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Translation Validation of Loop Invariant Code Optimizations Involving
               False Computations},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {767--778},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_72},
  doi       = {10.1007/978-981-10-7470-7\_72},
  timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChoukseyKB17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DarjiP17,
  author    = {Pallavi G. Darji and
               Chetan D. Parikh},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A Calibration Technique for Current Steering DACs - Self Calibration
               with Capacitor Storage},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {103--114},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_12},
  doi       = {10.1007/978-981-10-7470-7\_12},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/DarjiP17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasBS17,
  author    = {Moumita Das and
               Ansuman Banerjee and
               Bhaskar Sardar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A Framework for Branch Predictor Selection with Aggregation on Multiple
               Parameters},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {69--74},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_8},
  doi       = {10.1007/978-981-10-7470-7\_8},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/DasBS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasKB17,
  author    = {Surajit Das and
               Chandan Karfa and
               Santosh Biswas},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {xMAS Based Accurate Modeling and Progress Verification of NoCs},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {792--804},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_74},
  doi       = {10.1007/978-981-10-7470-7\_74},
  timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasKB17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DheepikaJCK17,
  author    = {K. Dheepika and
               K. S. Jevasankari and
               Vippin Chandhar and
               Binsu J. Kailath},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {36--47},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_4},
  doi       = {10.1007/978-981-10-7470-7\_4},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/DheepikaJCK17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GS17,
  author    = {G. Hanumanta Rao and
               S. Rekha},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Low Voltage, Low Power Transconductor for Low Frequency G{\_}m -C
               Filters},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {83--92},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_10},
  doi       = {10.1007/978-981-10-7470-7\_10},
  timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GhoshG17,
  author    = {Prokash Ghosh and
               Jyotirmoy Ghosh},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A Configurable and Area Efficient Technique for Implementing Isolation
               Cells in Low Power SoC},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {619--627},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_59},
  doi       = {10.1007/978-981-10-7470-7\_59},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GhoshG17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GhoshR17,
  author    = {Puja Ghosh and
               P. Rangababu},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Design and Implementation of Ternary Content Addressable Memory {(TCAM)}
               Based Hierarchical Motion Estimation for Video Processing},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {557--569},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_54},
  doi       = {10.1007/978-981-10-7470-7\_54},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GhoshR17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GoelG17,
  author    = {Anshu Goel and
               Rohini Gulve},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Multi-mode Toggle Random Access Scan to Minimize Test Application
               Time},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {205--216},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_21},
  doi       = {10.1007/978-981-10-7470-7\_21},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GoelG17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GovilSC17,
  author    = {Naman Govil and
               Rahul Shrestha and
               Shubhajit Roy Chowdhury},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach
               for High Speed Applications},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {62--68},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_7},
  doi       = {10.1007/978-981-10-7470-7\_7},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GovilSC17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GudaparthiS17,
  author    = {Sumanth Gudaparthi and
               Rahul Shrestha},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Energy-Efficient {VLSI} Architecture {\&} Implementation of Bi-modal
               Multi-banked Register-File Organization},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {299--312},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_30},
  doi       = {10.1007/978-981-10-7470-7\_30},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GudaparthiS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GulatiPD17,
  author    = {Jasmine Kaur Gulati and
               Bhanu Prakash and
               Sumit Jagdish Darak},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {An Efficient Timing and Clock Tree Aware Placement Flow with Multibit
               Flip-Flops for Power Reduction},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {581--593},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_56},
  doi       = {10.1007/978-981-10-7470-7\_56},
  timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GulatiPD17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GulveH17,
  author    = {Rohini Gulve and
               Nihar Hage},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {On Generation of Delay Test with Capture Power Safety},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {607--618},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_58},
  doi       = {10.1007/978-981-10-7470-7\_58},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GulveH17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuptaDSSSD17,
  author    = {Yatharth Gupta and
               Sujay Deb and
               Vikrant Singh and
               V. N. Srinivasan and
               Manish Sharma and
               Sabyasachi Das},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Pseudo-BIST: {A} Novel Technique for {SAR-ADC} Testing},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {168--178},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_18},
  doi       = {10.1007/978-981-10-7470-7\_18},
  timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GuptaDSSSD17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/IlakalG17,
  author    = {Anand Ilakal and
               Anuj Grover},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Comparison of {SRAM} Cell Layout Topologies to Estimate Improvement
               in {SER} Robustness in 28FDSOI and 40 nm Technologies},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {414--420},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_41},
  doi       = {10.1007/978-981-10-7470-7\_41},
  timestamp = {Fri, 12 Jan 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/IlakalG17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JainDP17,
  author    = {Vandana Jain and
               Vasavi Devarasetty and
               Rajendra Patrikar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Droplet Position Estimator for Open {EWOD} System Using Open Source
               Computer Vision},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {737--741},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_69},
  doi       = {10.1007/978-981-10-7470-7\_69},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/JainDP17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JainLTGB17,
  author    = {Anugrah Jain and
               Vijay Laxmi and
               Meenakshi Tripathi and
               Manoj Singh Gaur and
               Rimpy Bishnoi},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Performance-Enhanced d2 -LBDR for 2D Mesh Network-on-Chip},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {313--323},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_31},
  doi       = {10.1007/978-981-10-7470-7\_31},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/JainLTGB17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JapaVV17,
  author    = {Aditya Japa and
               Harshita Vallabhaneni and
               Ramesh Vaddi},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Exploiting Characteristics of Steep Slope Tunnel Transistors Towards
               Energy Efficient and Reliable Buffer Designs for IoT SoCs},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {259--269},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_26},
  doi       = {10.1007/978-981-10-7470-7\_26},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/JapaVV17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JoshiTSD17,
  author    = {Manish Joshi and
               Koduri Teja and
               Ashish Singh and
               Rohit Dhiman},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Delay and Frequency Investigations in Coupled {MLGNR} Interconnects},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {429--440},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_43},
  doi       = {10.1007/978-981-10-7470-7\_43},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/JoshiTSD17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KhanA17,
  author    = {Mohd. Tasleem Khan and
               Shaik Rafi Ahamed},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {{VLSI} Implementation of Throughput Efficient Distributed Arithmetic
               Based {LMS} Adaptive Filter},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {24--35},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_3},
  doi       = {10.1007/978-981-10-7470-7\_3},
  timestamp = {Fri, 25 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KhanA17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarGB17,
  author    = {Naresh Kumar and
               Raja Hari Gudlavalleti and
               Subash Chandra Bose},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {An Improved Highly Efficient Low Input Voltage Charge Pump Circuit},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {93--102},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_11},
  doi       = {10.1007/978-981-10-7470-7\_11},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarGB17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumariSG17,
  author    = {Vandana Kumari and
               Manoj Saxena and
               Mridula Gupta},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Variability Investigation of Double Gate JunctionLess {(DG-JL)} Transistor
               for Circuit Design Perspective},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {496--503},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_49},
  doi       = {10.1007/978-981-10-7470-7\_49},
  timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumariSG17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MaheshwaramPSBM17,
  author    = {Satish Maheshwaram and
               Om. Prakash and
               Mohit Sharma and
               Anand Bulusu and
               Sanjeev Manhas},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Vertical Nanowire {FET} Based Standard Cell Design Employing Verilog-A
               Compact Model for Higher Performance},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {239--248},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_24},
  doi       = {10.1007/978-981-10-7470-7\_24},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/MaheshwaramPSBM17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MahtoN17,
  author    = {Sujit Kr Mahto and
               Newton},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {{ACAM:} Application Aware Adaptive Cache Management for Shared {LLC}},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {324--336},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_32},
  doi       = {10.1007/978-981-10-7470-7\_32},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/MahtoN17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MaityRG17,
  author    = {Dilip Kumar Maity and
               Surajit Kumar Roy and
               Chandan Giri},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Faulty TSVs Identification in 3D {IC} Using Pre-bond Testing},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {805--812},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_75},
  doi       = {10.1007/978-981-10-7470-7\_75},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MaityRG17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MalikKJ17,
  author    = {Munish Malik and
               Ajay Kumar and
               H. S. Jatana},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Design {\&} Development of High Speed {LVDS} Receiver with Cold-Spare
               Feature in SCL's 0.18 {\(\mathrm{\mu}\)}m {CMOS} Process},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {667--678},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_63},
  doi       = {10.1007/978-981-10-7470-7\_63},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/MalikKJ17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MewadaZL17,
  author    = {Manan Mewada and
               Mazad Zaveri and
               Anurag Lakhlani},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder
               Using Reduced Input Transitions},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {15--23},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_2},
  doi       = {10.1007/978-981-10-7470-7\_2},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MewadaZL17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NarangGS17,
  author    = {Rakhi Narang and
               Mridula Gupta and
               Manoj Saxena},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Improved Gate Modulation in Tunnel Field Effect Transistors with Non-rectangular
               Tapered Y-Gate Geometry},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {463--473},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_46},
  doi       = {10.1007/978-981-10-7470-7\_46},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NarangGS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NegiMK17,
  author    = {Shubham Negi and
               Poornima Mittal and
               Brijesh Kumar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Performance Analysis of {OLED} with Hole Block Layer and Impact of
               Multiple Hole Block Layer},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {452--462},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_45},
  doi       = {10.1007/978-981-10-7470-7\_45},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/NegiMK17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PalchaudhuriD17,
  author    = {Ayan Palchaudhuri and
               Anindya Sundar Dhar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Primitive Instantiation Based Fault Localization Circuitry for High
               Performance {FPGA} Designs},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {594--606},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_57},
  doi       = {10.1007/978-981-10-7470-7\_57},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PalchaudhuriD17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PandeyGK17,
  author    = {Jai Gopal Pandey and
               Tarun Goel and
               Abhijit Karmakar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {An Efficient {VLSI} Architecture for {PRESENT} Block Cipher and Its
               {FPGA} Implementation},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {270--278},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_27},
  doi       = {10.1007/978-981-10-7470-7\_27},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PandeyGK17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PanigrahiP17,
  author    = {Antaryami Panigrahi and
               Abhipsa Parhi},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A 1.8 {V} Gain Enhanced Fully Differential Doubly-Recycled Cascode
               {OTA} with 100 dB Gain 200 MHz {UGB} in {CMOS}},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {646--656},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_61},
  doi       = {10.1007/978-981-10-7470-7\_61},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PanigrahiP17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PanigrahyBVCD17,
  author    = {Mamata Panigrahy and
               Nirmal Chandra Behera and
               B. Vandana and
               Indrajit Chakrabarti and
               Anindya Sundar Dhar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {376--387},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_37},
  doi       = {10.1007/978-981-10-7470-7\_37},
  timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PanigrahyBVCD17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PatelMN17,
  author    = {Purvi Patel and
               Biswajit Mishra and
               Dipankar Nagchoudhuri},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A 36 nW Power Management Unit for Solar Energy Harvesters Using 0.18
               {\textbackslash}upmu m {CMOS}},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {474--486},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_47},
  doi       = {10.1007/978-981-10-7470-7\_47},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PatelMN17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PathakD17,
  author    = {Jay Pathak and
               Anand D. Darji},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Investigation of TCADs Models for Characterization of Sub 16 nm In
               {\_}0.53 Ga {\_}0.47 As FinFET},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {279--286},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_28},
  doi       = {10.1007/978-981-10-7470-7\_28},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PathakD17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PaulS17,
  author    = {Rourab Paul and
               Sandeep Kumar Shukla},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A High Speed {KECCAK} Coprocessor for Partitioned {NSP} Architecture
               on {FPGA} Platform},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {507--518},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_50},
  doi       = {10.1007/978-981-10-7470-7\_50},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PaulS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PawanekarT17,
  author    = {Sameer Pawanekar and
               Gaurav Trivedi},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Fast {FPGA} Placement Using Analytical Optimization},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {681--693},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_64},
  doi       = {10.1007/978-981-10-7470-7\_64},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PawanekarT17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PawanekarT17a,
  author    = {Sameer Pawanekar and
               Gaurav Trivedi},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Analytical Partitioning: Improvement over {FM}},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {718--730},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_67},
  doi       = {10.1007/978-981-10-7470-7\_67},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PawanekarT17a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PravinrajP17,
  author    = {T. Pravinraj and
               Rajendra Patrikar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Splitting and Transport of a Droplet with No External Actuation Force
               for Lab on Chip Devices},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {707--717},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_66},
  doi       = {10.1007/978-981-10-7470-7\_66},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PravinrajP17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RSVB17,
  author    = {Thilagavathy R and
               Susmitha Settivari and
               B. Venkataramani and
               M. Bhaskar},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {{FPGA} Implementation of a Novel Area Efficient {FFT} Scheme Using
               Mixed Radix {FFT}},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {75--80},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_9},
  doi       = {10.1007/978-981-10-7470-7\_9},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/RSVB17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RayKBSAT17,
  author    = {Ashok Ray and
               Gaurav Kumar and
               Sushanta Bordoloi and
               Dheeraj Kumar Sinha and
               Pratima Agarwal and
               Gaurav Trivedi},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {{FEM} Based Device Simulator for High Voltage Devices},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {127--135},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_14},
  doi       = {10.1007/978-981-10-7470-7\_14},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/RayKBSAT17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RehaniDS17,
  author    = {Ankit Rehani and
               Sujay Deb and
               Suprateek Shukla},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Enhancing Retention Voltage for {SRAM}},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {406--413},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_40},
  doi       = {10.1007/978-981-10-7470-7\_40},
  timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RehaniDS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RekhaS17,
  author    = {Shanthi Rekha Shanmugham and
               Saravanan Paramasivam},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Low Cost Circuit Level Implementation of {PRESENT-80} {S-BOX}},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {354--362},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_35},
  doi       = {10.1007/978-981-10-7470-7\_35},
  timestamp = {Fri, 12 Apr 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RekhaS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SantoshBMBB17,
  author    = {M. Santosh and
               Anjli Bansal and
               Jitendra Mishra and
               K. C. Behra and
               S. C. Bose},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Characterization and Compensation Circuitry for Piezo-Resistive Pressure
               Sensor to Accommodate Temperature Induced Variation},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {115--126},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_13},
  doi       = {10.1007/978-981-10-7470-7\_13},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SantoshBMBB17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShahYV17,
  author    = {Ambika Prasad Shah and
               Nandakishor Yadav and
               Santosh Kumar Vishvakarma},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {{LISOCHIN:} An {NBTI} Degradation Monitoring Sensor for Reliable {CMOS}
               Circuits},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {441--451},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_44},
  doi       = {10.1007/978-981-10-7470-7\_44},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ShahYV17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharatBVB17,
  author    = {Kavya Sharat and
               Sumeet Bandishte and
               Kuruvilla Varghese and
               Amrutur Bharadwaj},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A Custom Designed {RISC-V} {ISA} Compatible Processor for SoC},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {570--577},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_55},
  doi       = {10.1007/978-981-10-7470-7\_55},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SharatBVB17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Singh17,
  author    = {Divya Singh},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Metal-Oxide Nanostructures Designed by Glancing Angle Deposition Technique
               and Its Applications on Sensors and Optoelectronic Devices: {A} Review},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {388--397},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_38},
  doi       = {10.1007/978-981-10-7470-7\_38},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/Singh17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghMM17,
  author    = {Jatindeep Singh and
               Satyajit Mohapatra and
               Nihar Ranjan Mohapatra},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Performance Optimized 64b/66b Line Encoding Technique for High Speed
               {SERDES} Devices},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {56--61},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_6},
  doi       = {10.1007/978-981-10-7470-7\_6},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghMM17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghNSG17,
  author    = {Ajay Singh and
               Rakhi Narang and
               Manoj Saxena and
               Mridula Gupta},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect
               Transistor as pH Sensor},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {249--258},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_25},
  doi       = {10.1007/978-981-10-7470-7\_25},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghNSG17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghSSMC17,
  author    = {Sanjay Singh and
               Sumeet Saurav and
               Ravi Saini and
               Atanendu S. Mandal and
               Santanu Chaudhury},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {FPGA-Based Smart Camera System for Real-Time Automated Video Surveillance},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {533--544},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_52},
  doi       = {10.1007/978-981-10-7470-7\_52},
  timestamp = {Wed, 20 Nov 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghSSMC17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinharayRR17,
  author    = {Arindam Sinharay and
               Pranab Roy and
               Hafizur Rahaman},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Hausdorff Distance Driven L-Shape Matching Based Layout Decomposition
               for E-Beam Lithography},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {287--295},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_29},
  doi       = {10.1007/978-981-10-7470-7\_29},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinharayRR17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SoniUM17,
  author    = {Ashish Soni and
               Abhijit Umap and
               Nihar R. Mohapatra},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Low-Power Sequential Circuit Design Using Work-Function Engineered
               FinFETs},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {227--238},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_23},
  doi       = {10.1007/978-981-10-7470-7\_23},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SoniUM17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SrivastavaR17,
  author    = {Sushma Srivastava and
               Surendra S. Rathod},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Synapse Circuits Implementation and Analysis in 180 nm {MOSFET} and
               {CNFET} Technology},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {136--143},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_15},
  doi       = {10.1007/978-981-10-7470-7\_15},
  timestamp = {Mon, 07 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SrivastavaR17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SwaatiD17,
  author    = {Swaati and
               Bishnu Prasad Das},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A 10T Subthreshold {SRAM} Cell with Minimal Bitline Switching for
               Ultra-Low Power Applications},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {487--495},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_48},
  doi       = {10.1007/978-981-10-7470-7\_48},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SwaatiD17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/TyagiHRR17,
  author    = {Vivek Tyagi and
               Mohammad S. Hashmi and
               Ganesh Raj and
               Vikas Rana},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A 10 MHz, 73 ppm/{\textdegree}C, 84 {\(\mathrm{\mu}\)}W {PVT} Compensated
               Ring Oscillator},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {144--152},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_16},
  doi       = {10.1007/978-981-10-7470-7\_16},
  timestamp = {Fri, 27 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/TyagiHRR17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/TyagiHRR17a,
  author    = {Vivek Tyagi and
               Mohammad S. Hashmi and
               Ganesh Raj and
               Vikas Rana},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {A 10 MHz, 42 ppm/ {\textdegree}C, 69 {\(\mu\)}W {PVT} Compensated
               Latch Based Oscillator in {BCD9S} Technology for {PCM}},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {631--645},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_60},
  doi       = {10.1007/978-981-10-7470-7\_60},
  timestamp = {Fri, 27 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/TyagiHRR17a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/VandanaDMK17,
  author    = {B. Vandana and
               J. K. Das and
               S. K. Mohapatra and
               Brajesh Kumar Kaushik},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Effectiveness of High Permittivity Spacer for Underlap Regions of
               Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {545--556},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_53},
  doi       = {10.1007/978-981-10-7470-7\_53},
  timestamp = {Sat, 03 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/VandanaDMK17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/VaniRV17,
  author    = {Y. Sudha Vani and
               N. Usha Rani and
               Ramesh Vaddi},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Low Write Energy {STT-MRAM} Cell Using 2T- Hybrid Tunnel FETs Exploiting
               the Steep Slope and Ambipolar Characteristics},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {398--405},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_39},
  doi       = {10.1007/978-981-10-7470-7\_39},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/VaniRV17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ZodeDS17,
  author    = {Pravin Zode and
               Raghavendra B. Deshmukh and
               Abdus Samad},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {48--55},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_5},
  doi       = {10.1007/978-981-10-7470-7\_5},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ZodeDS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vdat/2017,
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7},
  doi       = {10.1007/978-981-10-7470-7},
  isbn      = {978-981-10-7469-1},
  timestamp = {Sat, 06 Jan 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/2017.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/0001NPT16,
  author    = {Binod Kumar and
               Boda Nehru and
               Brajesh Pandey and
               Jaynarayan T. Tudu},
  title     = {Skip-scan: {A} methodology for test time reduction},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064869},
  doi       = {10.1109/ISVDAT.2016.8064869},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/0001NPT16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AcharyaMM16,
  author    = {Rama Prasad Acharya and
               Abir J. Mondal and
               Alak Majumder},
  title     = {A method to design a comparator for sampled data processing applications},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064863},
  doi       = {10.1109/ISVDAT.2016.8064863},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AcharyaMM16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AgarwalK16,
  author    = {Sukarn Agarwal and
               Hemangee K. Kapoor},
  title     = {Towards a dynamic associativity enabled write prediction based hybrid
               cache},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064870},
  doi       = {10.1109/ISVDAT.2016.8064870},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AgarwalK16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AhlawatT16,
  author    = {Satyadev Ahlawat and
               Jaynarayan T. Tudu},
  title     = {On minimization of test power through modified scan flip-flop},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064878},
  doi       = {10.1109/ISVDAT.2016.8064878},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AhlawatT16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AlagarsamyG16,
  author    = {Aravindhan Alagarsamy and
               Lakshminaraynan Gopalakrishnan},
  title     = {{SAT:} {A} new application mapping method for power optimization in
               2D - NoC},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064880},
  doi       = {10.1109/ISVDAT.2016.8064880},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AlagarsamyG16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AroraGH16,
  author    = {Disha Arora and
               Anil Kumar Gundu and
               Mohammad S. Hashmi},
  title     = {A high speed low voltage latch type sense amplifier for non-volatile
               memory},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064841},
  doi       = {10.1109/ISVDAT.2016.8064841},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AroraGH16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BasiriS16,
  author    = {M. Mohamed Asan Basiri and
               Sandeep K. Shukla},
  title     = {Hardware optimizations for crypto implementations (Invited paper)},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064877},
  doi       = {10.1109/ISVDAT.2016.8064877},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BasiriS16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BatraGHVG16,
  author    = {Nidhi Batra and
               Anil Kumar Gundu and
               Mohammad S. Hashmi and
               G. S. Visweswaran and
               Anuj Grover},
  title     = {An effective test methodology enabling detection of weak bits in SRAMs:
               Case study in 28nm {FDSOI}},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064868},
  doi       = {10.1109/ISVDAT.2016.8064868},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BatraGHVG16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BatraSKH16,
  author    = {Shipra Batra and
               Pankhuri Singh and
               Shashwat Kaushik and
               Mohammad S. Hashmi},
  title     = {Frequency domain analysis of on-chip power distribution network},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064853},
  doi       = {10.1109/ISVDAT.2016.8064853},
  timestamp = {Tue, 11 Feb 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BatraSKH16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BhattacharjeeMM16,
  author    = {Paromita Bhattacharjee and
               Abir J. Mondal and
               Alak Majumder},
  title     = {A constraint driven technique for {MOS} amplifier design},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064882},
  doi       = {10.1109/ISVDAT.2016.8064882},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BhattacharjeeMM16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BhattacharyaDR16,
  author    = {Sandip Bhattacharya and
               Debaprasad Das and
               Hafizur Rahaman},
  title     = {Temperature dependent IR-drop and delay analysis in side-contact multilayer
               graphene nanoribbon based power interconnects},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064891},
  doi       = {10.1109/ISVDAT.2016.8064891},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BhattacharyaDR16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/CeliaC16,
  author    = {D. Celia and
               Nitin Chandrachoodan},
  title     = {Guided multilevel approximation of less significant bits for power
               reduction},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064879},
  doi       = {10.1109/ISVDAT.2016.8064879},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/CeliaC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChakrabortyCMSG16,
  author    = {Moumita Chakraborty and
               Amlan Chakrabarti and
               Partha Mitra and
               Debasri Saha and
               Krishnendu Guha},
  title     = {Pre-layout module wise decap allocation for noise suppression and
               accurate delay estimation of SoC},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064873},
  doi       = {10.1109/ISVDAT.2016.8064873},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ChakrabortyCMSG16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChakrabortyDBR16,
  author    = {Anindita Chakraborty and
               Rakesh Das and
               Chandan Bandyopadhyay and
               Hafizur Rahaman},
  title     = {{BDD} based synthesis technique for design of high-speed memristor
               based circuits},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064842},
  doi       = {10.1109/ISVDAT.2016.8064842},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChakrabortyDBR16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChakrabortyDS16,
  author    = {Bidesh Chakraborty and
               Mamata Dalui and
               Biplab K. Sikdar},
  title     = {Design of coherence verification unit for CMPs realizing dragon protocol},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064850},
  doi       = {10.1109/ISVDAT.2016.8064850},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChakrabortyDS16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChanuPD16,
  author    = {Waikhom Mona Chanu and
               Vikash Prasad and
               Debaprasad Das},
  title     = {Performance analysis of temperature dependent {GNR} interconnect},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064864},
  doi       = {10.1109/ISVDAT.2016.8064864},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChanuPD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChatterjeeK016,
  author    = {Procheta Chatterjee and
               Sougata Kar and
               Siddhartha Sen},
  title     = {Design methodology of closed loop {MEMS} capacitive accelerometers
               based on {\(\Sigma\)}{\(\Delta\)} modulation technique},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064884},
  doi       = {10.1109/ISVDAT.2016.8064884},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChatterjeeK016.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChatterjeeK016a,
  author    = {Procheta Chatterjee and
               Sougata Kar and
               Siddhartha Sen},
  title     = {Design, integration and performance analysis of {\(\Sigma\)}{\(\Delta\)}
               {ADC} for capacitive sensor interfacing},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064892},
  doi       = {10.1109/ISVDAT.2016.8064892},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChatterjeeK016a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChatterjeeMC16,
  author    = {Navonil Chatterjee and
               Priyajit Mukherjee and
               Santanu Chattopadhyay},
  title     = {A strategy for fault tolerant reconfigurable Network-on-Chip design},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064893},
  doi       = {10.1109/ISVDAT.2016.8064893},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChatterjeeMC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChattopadhyayTG16,
  author    = {Subrata Chattopadhyay and
               Shiv Bhushan Tripathi and
               Mrinal Goswami and
               Bibhash Sen},
  title     = {Design of fault tolerant majority voter for {TMR} circuit in {QCA}},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064905},
  doi       = {10.1109/ISVDAT.2016.8064905},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChattopadhyayTG16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasDK16,
  author    = {Surajit Das and
               Shirshendu Das and
               Hemangee K. Kapoor},
  title     = {Tag only storage for capacity optimised last level cache in chip multiprocessors},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064886},
  doi       = {10.1109/ISVDAT.2016.8064886},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasDK16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GadeKD16,
  author    = {Sri Harsha Gade and
               Praveen Kumar and
               Sujay Deb},
  title     = {A Pre-RTL floorplanner tool for automated {CMP} design space exploration
               with thermal awareness},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064876},
  doi       = {10.1109/ISVDAT.2016.8064876},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GadeKD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GangulyGBG16,
  author    = {Antara Ganguly and
               Sangeeta Goyal and
               Sneha Bhatia and
               Anuj Grover},
  title     = {New stable loadless 6T dual-port {SRAM} cell design},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064859},
  doi       = {10.1109/ISVDAT.2016.8064859},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GangulyGBG16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GargD16,
  author    = {Sasha Garg and
               Sumit Jagdish Darak},
  title     = {{FPGA} implementation of high speed reconfigurable filter bank for
               multi-standard wireless communication receivers},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064855},
  doi       = {10.1109/ISVDAT.2016.8064855},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GargD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GargGS16,
  author    = {Bharat Garg and
               V. N. S. K. Chaitanya Goteti and
               G. K. Sharma},
  title     = {A low-cost energy efficient image scaling processor for multimedia
               applications},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064888},
  doi       = {10.1109/ISVDAT.2016.8064888},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GargGS16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GargYS16,
  author    = {Bharat Garg and
               Sameer Yadav and
               G. K. Sharma},
  title     = {An area and performance aware {ECG} encoder design for wireless healthcare
               services},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064861},
  doi       = {10.1109/ISVDAT.2016.8064861},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GargYS16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GarjeKTMK16,
  author    = {Kiran Garje and
               Shravan Kumar and
               Amitesh Tripathi and
               Gillela Maruthi and
               Madhava Kumar},
  title     = {A high CMRR, high resolution bio-ASIC for {ECG} signals},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064890},
  doi       = {10.1109/ISVDAT.2016.8064890},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GarjeKTMK16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GauravGKR16,
  author    = {Ankit Gaurav and
               Sandeep Singh Gill and
               Navneet Kaur and
               Munish Rattan},
  title     = {Density gradient quantum corrections based performance optimization
               of triangular {TG} bulk FinFETs using {ANN} and {GA}},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064854},
  doi       = {10.1109/ISVDAT.2016.8064854},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GauravGKR16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GhoshMDHD16,
  author    = {Saurav Kumar Ghosh and
               Akash Mondal and
               Souradeep Dutta and
               Aritra Hazra and
               Soumyajit Dey},
  title     = {Synthesis of scheduler automata guaranteeing stability and reliability
               of embedded control systems},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064856},
  doi       = {10.1109/ISVDAT.2016.8064856},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GhoshMDHD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GulveHT16,
  author    = {Rohini Gulve and
               Nihar Hage and
               Jaynarayan T. Tudu},
  title     = {On determination of instantaneous peak and cycle peak switching using
               {ILP}},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064881},
  doi       = {10.1109/ISVDAT.2016.8064881},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GulveHT16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/HebbarKBB16,
  author    = {Suraj Hebbar and
               Vinay Kumar and
               M. S. Bhat and
               Navakanta Bhat},
  title     = {Smart handheld platform for electrochemical bio sensors},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064906},
  doi       = {10.1109/ISVDAT.2016.8064906},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/HebbarKBB16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/HeitmannKC16,
  author    = {Nils Heitmann and
               Philipp Kindt and
               Samarjit Chakraborty},
  title     = {{EG0N:} Portable in-situ energy measurement for low-power sensor devices},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064889},
  doi       = {10.1109/ISVDAT.2016.8064889},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/HeitmannKC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JanaKDDK16,
  author    = {Rajib Lochan Jana and
               Shashank Kuchibhotla and
               Soumyajit Dey and
               Pallab Dasgupta and
               Rakesh Kumar},
  title     = {Planning based guided reconstruction of corner cases in architectural
               validation},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064887},
  doi       = {10.1109/ISVDAT.2016.8064887},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JanaKDDK16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KhanAC16,
  author    = {Mohd. Tasleem Khan and
               Shaik Rafi Ahamed and
               Amitabh Chatterjee},
  title     = {Efficient implementation of concurrent lookahead decision feedback
               equalizer using offset binary coding},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064862},
  doi       = {10.1109/ISVDAT.2016.8064862},
  timestamp = {Fri, 25 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KhanAC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KhandagaleS16,
  author    = {Sachin Khandagale and
               Santanu Sarkar},
  title     = {An 8-bit 500 {MSPS} segmented current steering {DAC} using Chinese
               abacus technique},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064903},
  doi       = {10.1109/ISVDAT.2016.8064903},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KhandagaleS16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KhandelwalMGB16,
  author    = {Sapna Khandelwal and
               Jyoti Meena and
               Lokesh Garg and
               Dharmendar Boolchandani},
  title     = {Variability and reliability aware surrogate model for sensing delay
               analysis of {SRAM} sense amplifier},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064839},
  doi       = {10.1109/ISVDAT.2016.8064839},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KhandelwalMGB16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KimteeDB16,
  author    = {Priyanka Kimtee and
               Devarshi Mrinal Das and
               Maryam Shojaei Baghini},
  title     = {A mismatch insensitive reconfigurable discrete time biosignal conditioning
               circuit in 180 nm {MM} {CMOS} technology},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064907},
  doi       = {10.1109/ISVDAT.2016.8064907},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KimteeDB16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KishoreMD16,
  author    = {Raghav Kishore and
               Hemanta Kumar Mondal and
               Sujay Deb},
  title     = {Energy-efficient reconfigurable framework for evaluating hybrid NoCs},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064902},
  doi       = {10.1109/ISVDAT.2016.8064902},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KishoreMD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KushwahDSR16,
  author    = {C. B. Kushwah and
               Devesh Dwivedi and
               N. Sathisha and
               Krishnan S. Rengarajan},
  title     = {A robust 8T FinFET {SRAM} cell with improved stability for low voltage
               applications},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064858},
  doi       = {10.1109/ISVDAT.2016.8064858},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KushwahDSR16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MewadaZ16,
  author    = {Manan Mewada and
               Mazad Zaveri},
  title     = {A low-power high-speed hybrid full adder},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064900},
  doi       = {10.1109/ISVDAT.2016.8064900},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MewadaZ16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MishraR16,
  author    = {Ambuj Mishra and
               Subir K. Roy},
  title     = {Formal verification of switched capacitor {DC} to {DC} power converter
               using circuit simulation traces},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064894},
  doi       = {10.1109/ISVDAT.2016.8064894},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MishraR16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MondalDC16,
  author    = {Bikromadittya Mondal and
               Kushal Dey and
               Susanta Chakraborty},
  title     = {An efficient reversible cryptographic circuit design},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064874},
  doi       = {10.1109/ISVDAT.2016.8064874},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MondalDC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MovvaA16,
  author    = {Krishna Kumar Movva and
               Syed Azeemuddin},
  title     = {A novel low power 6-bit {FLASH} {ADC} using charge steering amplifier
               for {RF} applications},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064904},
  doi       = {10.1109/ISVDAT.2016.8064904},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MovvaA16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MukherjeeRPM16,
  author    = {Chiradeep Mukherjee and
               Soudip Sinha Roy and
               Saradindu Panda and
               Bansibadan Maji},
  title     = {T-Gate: Concept of partial polarization in Quantum Dot Cellular Automata},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064844},
  doi       = {10.1109/ISVDAT.2016.8064844},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MukherjeeRPM16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MuralidharGK16,
  author    = {G. Muralidhar and
               Dinesh G. and
               Binsu J. Kailath},
  title     = {Switched-capacitor circuit simulator in {Q-V} domain including nonidealities},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064865},
  doi       = {10.1109/ISVDAT.2016.8064865},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MuralidharGK16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NadimpalliR16,
  author    = {Pavan Kumar Nadimpalli and
               Subir K. Roy},
  title     = {An efficient FPGA-based function profiler for embedded system applications},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064857},
  doi       = {10.1109/ISVDAT.2016.8064857},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NadimpalliR16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NavlaniJD16,
  author    = {Bharti Navlani and
               Pankaj U. Joshi and
               Raghavendra B. Deshmukh},
  title     = {Data dependent spurious power reduction for fixed width multiplier},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064898},
  doi       = {10.1109/ISVDAT.2016.8064898},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NavlaniJD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PalPDD16,
  author    = {Debasis Pal and
               Abir Pramanik and
               Parthasarathi Dasgupta and
               Debesh Kumar Das},
  title     = {Double Patterning Lithography (DPL)-compliant layout construction
               {(DCLC)} with area-stitch usage tradeoff},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064875},
  doi       = {10.1109/ISVDAT.2016.8064875},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PalPDD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PalchaudhuriD16,
  author    = {Ayan Palchaudhuri and
               Anindya Sundar Dhar},
  title     = {High performance bit-sliced pipelined comparator tree for FPGAs},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064843},
  doi       = {10.1109/ISVDAT.2016.8064843},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PalchaudhuriD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ParikhA16,
  author    = {Chetan D. Parikh and
               Gopal Agarwal},
  title     = {New technique to improve transient response of {LDO} regulators without
               an off-chip capacitor},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064847},
  doi       = {10.1109/ISVDAT.2016.8064847},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ParikhA16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PendyalaP16,
  author    = {Prateek Pendyala and
               Vijaya Sankara Rao Pasupureddi},
  title     = {Backward compatible {MIL-STD-1553B} analog transceiver upgrade for
               100-Mb/s data rate},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064845},
  doi       = {10.1109/ISVDAT.2016.8064845},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PendyalaP16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PrakashMSBSM16,
  author    = {Om. Prakash and
               Satish Maheshwaram and
               Mohit Sharma and
               Anand Bulusu and
               A. K. Saxena and
               S. K. Manhas},
  title     = {A unified Verilog-A compact model for lateral Si nanowire {(NW)} {FET}
               incorporating parasitics for circuit simulation},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064852},
  doi       = {10.1109/ISVDAT.2016.8064852},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PrakashMSBSM16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Purushothaman16,
  author    = {A. Purushothaman},
  title     = {Analysis of regeneration time constant of dynamic latch using Adomian
               Decomposition method},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064860},
  doi       = {10.1109/ISVDAT.2016.8064860},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Purushothaman16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RatnakumarN16,
  author    = {Rahul Ratnakumar and
               Satyasai Jagannath Nanda},
  title     = {A {FSM} based approach for efficient implementation of K-means algorithm},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064848},
  doi       = {10.1109/ISVDAT.2016.8064848},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RatnakumarN16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RoyCR16,
  author    = {Pranab Roy and
               Sudeshna Chakraborty and
               Hafizur Rahaman},
  title     = {Synthesis aware sample preparation techniques using random sample
               sets in {DMFB}},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064872},
  doi       = {10.1109/ISVDAT.2016.8064872},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RoyCR16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RoyPD16,
  author    = {Avishek Sinha Roy and
               N. Prasad and
               Anindya Sundar Dhar},
  title     = {Approximate conditional carry adder for error tolerant applications},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064867},
  doi       = {10.1109/ISVDAT.2016.8064867},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RoyPD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SalaskarC16,
  author    = {Amit Salaskar and
               Nitin Chandrachoodan},
  title     = {{FFT/IFFT} implementation using Vivado{\texttrademark} {HLS}},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064896},
  doi       = {10.1109/ISVDAT.2016.8064896},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SalaskarC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SankarSCRB16,
  author    = {K. Nithin Sankar and
               Abhishek Srivastava and
               Baibhab Chatterjee and
               K. K. Rakesh and
               Maryam Shojaei Baghini},
  title     = {{FSK} demodulator and {FPGA} based {BER} measurement system for low
               {IF} receivers},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064901},
  doi       = {10.1109/ISVDAT.2016.8064901},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SankarSCRB16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SarkarSAB16,
  author    = {Soumik Sarkar and
               Gaurav Saini and
               Mahima Arrawatia and
               Maryam Shojaei Baghini},
  title     = {Optimal design flow of {CMOS} doubler-based rectifiers},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064885},
  doi       = {10.1109/ISVDAT.2016.8064885},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SarkarSAB16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SehgalSMRD16,
  author    = {Pawan Sehgal and
               Aditi Sharma and
               Akhilesh C. Mishra and
               Rangarajan Ramanujam and
               Sujay Deb},
  title     = {An effective and efficient algorithm to analyse and debug clock propagation
               issues},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064849},
  doi       = {10.1109/ISVDAT.2016.8064849},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SehgalSMRD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaABGWD16,
  author    = {Pulkit Sharma and
               R. Anusha and
               K. Bharath and
               Jasmine Kaur Gulati and
               Preet K. Walia and
               Sumit Jagdish Darak},
  title     = {Quantification of figures of merit of 7T and 8T {SRAM} cells in subthreshold
               region and their comparison with the conventional 6T {SRAM} cell},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064899},
  doi       = {10.1109/ISVDAT.2016.8064899},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SharmaABGWD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaAGBL16,
  author    = {Ashish Sharma and
               Ruby Ansar and
               Manoj Singh Gaur and
               Lava Bhargava and
               Vijay Laxmi},
  title     = {Reducing {FIFO} buffer power using architectural alternatives at {RTL}},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064897},
  doi       = {10.1109/ISVDAT.2016.8064897},
  timestamp = {Wed, 23 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SharmaAGBL16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaGH16,
  author    = {Pulkit Sharma and
               Anil Kumar Gundu and
               Mohammad S. Hashmi},
  title     = {Modeling and yield estimation of {SRAM} sub-system for different capacities
               subjected to parametric variations},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064840},
  doi       = {10.1109/ISVDAT.2016.8064840},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SharmaGH16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShresthaSM16,
  author    = {Rahul Shrestha and
               Vinay Swargam and
               Mahesh S. Murty},
  title     = {Cognitive-radio wireless-sensor based on energy detection with improved
               accuracy: Performance and hardware perspectives},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064871},
  doi       = {10.1109/ISVDAT.2016.8064871},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ShresthaSM16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SrivastavaSRCDB16,
  author    = {Abhishek Srivastava and
               Nithin Sankar and
               K. K. Rakesh and
               Baibhab Chatterjee and
               Devarshi Mrinal Das and
               Maryam Shojaei Baghini},
  title     = {Design and measurement techniques for a low noise amplifier in a receiver
               chain for MedRadio spectrum of 401-406 MHz frequency band},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064846},
  doi       = {10.1109/ISVDAT.2016.8064846},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SrivastavaSRCDB16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Tudu16,
  author    = {Jaynarayan T. Tudu},
  title     = {{JSCAN:} {A} joint-scan {DFT} architecture to minimize test time,
               pattern volume, and power},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064866},
  doi       = {10.1109/ISVDAT.2016.8064866},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Tudu16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/TuduA16,
  author    = {Jaynarayan T. Tudu and
               Satyadev Ahlawat},
  title     = {Guided shifting of test pattern to minimize test time in serial scan},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064851},
  doi       = {10.1109/ISVDAT.2016.8064851},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/TuduA16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/VaikuntapuBS16,
  author    = {Ramakrishna Vaikuntapu and
               Lava Bhargava and
               Vineet Sahula},
  title     = {Golden {IC} free methodology for hardware Trojan detection using symmetric
               path delays},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064895},
  doi       = {10.1109/ISVDAT.2016.8064895},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/VaikuntapuBS16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ZanwarS16,
  author    = {Mahesh Zanwar and
               Subhajit Sen},
  title     = {Programmable output switched capacitor step-down {DC-DC} converter
               with high accuracy using Sigma-Delta Feedback Control Loop},
  booktitle = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ISVDAT.2016.8064883},
  doi       = {10.1109/ISVDAT.2016.8064883},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ZanwarS16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vdat/2016,
  title     = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
               Guwahati, India, May 24-27, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8059694/proceeding},
  isbn      = {978-1-5090-1422-4},
  timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/2016.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AbhinavCSS15,
  author    = {Vishnuram Abhinav and
               Amitabh Chatterjee and
               Dheeraj Kumar Sinha and
               Rajan Singh},
  title     = {Methodology for optimizing {ESD} protection for high speed {LVDS}
               based I/Os},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208096},
  doi       = {10.1109/ISVDAT.2015.7208096},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AbhinavCSS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AgrawalC15,
  author    = {Kshitij Agrawal and
               Shubhajit Roy Chowdhury},
  title     = {Real time multisensor Laplacian fusion on {FPGA}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--4},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208087},
  doi       = {10.1109/ISVDAT.2015.7208087},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AgrawalC15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BanerjeeD15,
  author    = {Arindam Banerjee and
               Debesh Kumar Das},
  title     = {Squarer design with reduced area and delay},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208092},
  doi       = {10.1109/ISVDAT.2015.7208092},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BanerjeeD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BanerjeeMD15,
  author    = {Sabyasachee Banerjee and
               Subhashis Majumder and
               Debesh K. Das},
  title     = {Partitioning-based test time reduction for core-based 3DICs},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208088},
  doi       = {10.1109/ISVDAT.2015.7208088},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BanerjeeMD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BanerjeeMSB15,
  author    = {Ansuman Banerjee and
               Arijit Mondal and
               Arnab Sarkar and
               Santosh Biswas},
  title     = {Real-time embedded systems analysis - From theory to practice},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208162},
  doi       = {10.1109/ISVDAT.2015.7208162},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BanerjeeMSB15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BaraiyaMS15,
  author    = {Binal B. Baraiya and
               Hiren K. Mewada and
               Amish B. Shah},
  title     = {{FPGA} based disk controller and photon counter of optical polarimeter},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208115},
  doi       = {10.1109/ISVDAT.2015.7208115},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BaraiyaMS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BashirPP15,
  author    = {Mudasir Bashir and
               Sreehari Rao Patri and
               K. S. R. Krishna Prasad},
  title     = {On-chip {CMOS} temperature sensor with current calibrated accuracy
               of -1.1{\textdegree}C to +1.4{\textdegree}C (3{\(\sigma\)}) from -20{\textdegree}C
               to 150{\textdegree}C},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208056},
  doi       = {10.1109/ISVDAT.2015.7208056},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BashirPP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BashirPP15a,
  author    = {Mudasir Bashir and
               Sreehari Rao Patri and
               K. S. R. Krishna Prasad},
  title     = {High speed self biased current sense amplifier for low power {CMOS}
               SRAM's},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208057},
  doi       = {10.1109/ISVDAT.2015.7208057},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BashirPP15a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BharCSK15,
  author    = {Anupam Bhar and
               Santanu Chattopadhyay and
               Indranil Sengupta and
               Rohit Kapur},
  title     = {{GA} based diagnostic test pattern generation for transition faults},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208122},
  doi       = {10.1109/ISVDAT.2015.7208122},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BharCSK15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BhatiaRV15,
  author    = {Praneet Bhatia and
               Bhupendra Singh Reniwal and
               Santosh Kumar Vishvakarma},
  title     = {An offset-tolerant self-correcting sense amplifier for robust high
               speed {SRAM}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208082},
  doi       = {10.1109/ISVDAT.2015.7208082},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BhatiaRV15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChakrabortyDCD15,
  author    = {Sarit Chakraborty and
               Chandan Das and
               Susanta Chakraborty and
               Parthasarathi Dasgupta},
  title     = {A novel two phase heuristic routing technique in digital microfluidic
               biochip},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208144},
  doi       = {10.1109/ISVDAT.2015.7208144},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChakrabortyDCD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChakrabortyDK15,
  author    = {Shounak Chakraborty and
               Shirshendu Das and
               Hemangee K. Kapoor},
  title     = {Power aware cache miss reduction by energy efficient victim retention},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208078},
  doi       = {10.1109/ISVDAT.2015.7208078},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChakrabortyDK15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChakrabortySCDS15,
  author    = {Bidesh Chakraborty and
               Bhanu Pratap Singh and
               M. Chinnapureddy and
               Mamata Dalui and
               Biplab K. Sikdar},
  title     = {Design of coherence verification unit for heterogeneous CMPs},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208098},
  doi       = {10.1109/ISVDAT.2015.7208098},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChakrabortySCDS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChandraKCK15,
  author    = {Anshuman Chandra and
               Santosh Kulkarni and
               Subramanian Chebiyam and
               Rohit Kapur},
  title     = {Designing efficient combinational compression architecture for testing
               industrial circuits},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208149},
  doi       = {10.1109/ISVDAT.2015.7208149},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChandraKCK15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Chattopadhyay15,
  author    = {Santanu Chattopadhyay},
  title     = {Power- and thermal-aware testing of {VLSI} circuits and systems},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208161},
  doi       = {10.1109/ISVDAT.2015.7208161},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Chattopadhyay15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChaudharySSYSMK15,
  author    = {Rekha Chaudhary and
               Amit Sharma and
               Soumendu Sinha and
               Jitendra Yadav and
               Rishi Sharma and
               Ravindra Mukhiya and
               Vinod K. Khanna},
  title     = {Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated
               with Si3N4 {ISFET}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--4},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208083},
  doi       = {10.1109/ISVDAT.2015.7208083},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChaudharySSYSMK15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChaurasiyaBSKA15,
  author    = {Yogesh Chaurasiya and
               Surabhi Bhargava and
               Arvind Kumar Sharma and
               Baljit Kaur and
               Bulusu Anand},
  title     = {Timing model for two stage buffer and its application in {ECSM} characterization},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208075},
  doi       = {10.1109/ISVDAT.2015.7208075},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChaurasiyaBSKA15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChoudhuryNRP15,
  author    = {Priyanka Choudhury and
               Debanjali Nath and
               Vivek Rai and
               Sambhu Nath Pradhan},
  title     = {Thermal aware {AND-OR-XOR} network synthesis},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208047},
  doi       = {10.1109/ISVDAT.2015.7208047},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChoudhuryNRP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DSouzaJC15,
  author    = {Sandeep D'Souza and
               Soumya J. and
               Santanu Chattopadhyay},
  title     = {A constructive heuristic for application mapping onto an express channel
               based Network-on-Chip},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208147},
  doi       = {10.1109/ISVDAT.2015.7208147},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DSouzaJC15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DarjiM15,
  author    = {Anand D. Darji and
               Raviraj P. Makwana},
  title     = {High-performance multiplierless {DCT} architecture for {HEVC}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208051},
  doi       = {10.1109/ISVDAT.2015.7208051},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DarjiM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DashBKTP15,
  author    = {Satyabrata Dash and
               Vivek Bangera and
               Vinay B. Y. Kumar and
               Gaurav Trivedi and
               Sachin B. Patkar},
  title     = {Parallel two step random walk algorithm to analyze {VLSI} power grid
               networks},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208101},
  doi       = {10.1109/ISVDAT.2015.7208101},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DashBKTP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DeyRD15,
  author    = {Debarati Dey and
               Pradipta Roy and
               Debashis De},
  title     = {Molecular modeling of Nano bio p-i-n {FET}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208111},
  doi       = {10.1109/ISVDAT.2015.7208111},
  timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/DeyRD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DhalDCRP15,
  author    = {Debasis Dhal and
               Piyali Datta and
               Arpan Chakrabarty and
               Sudipta Roy and
               Rajat Kumar Pal},
  title     = {An impressive approach for incorporating parallelism in designing
               {DMFB} with cross contamination avoidance},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208137},
  doi       = {10.1109/ISVDAT.2015.7208137},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DhalDCRP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DhareM15,
  author    = {Vaishali Dhare and
               Usha Mehta},
  title     = {Defect characterization and testing of {QCA} devices and circuits:
               {A} survey},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208060},
  doi       = {10.1109/ISVDAT.2015.7208060},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DhareM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DuttaC15,
  author    = {Arpita Dutta and
               Santanu Chattopadhyay},
  title     = {Particle swarm optimization approach for low temperature {BIST}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208148},
  doi       = {10.1109/ISVDAT.2015.7208148},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DuttaC15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GalgaliR15,
  author    = {Pradyumna Galgali and
               Surandra Rathod},
  title     = {Analysis of {CMOS} inhibitory synapse with varying neurotransmitter
               concentration, reuptake time and spread delay},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208112},
  doi       = {10.1109/ISVDAT.2015.7208112},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GalgaliR15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GaurLZKGS15,
  author    = {Manoj Singh Gaur and
               Vijay Laxmi and
               Mark Zwolinski and
               Manoj Kumar and
               Niyati Gupta and
               Ashish Sharma},
  title     = {Network-on-chip: Current issues and challenges},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--3},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208160},
  doi       = {10.1109/ISVDAT.2015.7208160},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GaurLZKGS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GhoshGSM15,
  author    = {Prokash Ghosh and
               Sandip Ghosh and
               Pritpal Singh and
               Saurabh Mishra},
  title     = {Case study: Re-visiting SoC verification challenges and best practices},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--9},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208052},
  doi       = {10.1109/ISVDAT.2015.7208052},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GhoshGSM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GowthamiHRY15,
  author    = {M. R. Gowthami and
               G. Harish and
               B. V. Bhargav Ram and
               Siva Sankar Yellampalli},
  title     = {Modified low power scan based technique},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208126},
  doi       = {10.1109/ISVDAT.2015.7208126},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GowthamiHRY15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuhaSC15,
  author    = {Krishnendu Guha and
               Debasri Saha and
               Amlan Chakrabarti},
  title     = {{RTNA:} Securing {SOC} architectures from confidentiality attacks
               at runtime using {ART1} neural networks},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208048},
  doi       = {10.1109/ISVDAT.2015.7208048},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GuhaSC15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuptaKBCMCPV15,
  author    = {Hari Shanker Gupta and
               Shweta Kirkire and
               Sunil Bhati and
               Ravi Shankar Chaurasia and
               Sanjeev Mehta and
               Arup Roy Choudhary and
               Dipen Patel and
               Jaymin Vaghela},
  title     = {Bipolar voltage level shifter},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208055},
  doi       = {10.1109/ISVDAT.2015.7208055},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GuptaKBCMCPV15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuptaKLGZ15,
  author    = {Niyati Gupta and
               Manoj Kumar and
               Vijay Laxmi and
               Manoj Singh Gaur and
               Mark Zwolinski},
  title     = {{\(\sigma\)}LBDR: Congestion-aware logic based distributed routing
               for 2D NoC},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208058},
  doi       = {10.1109/ISVDAT.2015.7208058},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GuptaKLGZ15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuptaMR15,
  author    = {Suraj Gupta and
               Sabir Ali Mondal and
               Hafizur Rahaman},
  title     = {Improved supply regulation and temperature compensated current reference
               circuit with low process variations},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208049},
  doi       = {10.1109/ISVDAT.2015.7208049},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GuptaMR15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Islam15,
  author    = {Aminul Islam},
  title     = {Technology scaling and its side effects},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208164},
  doi       = {10.1109/ISVDAT.2015.7208164},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Islam15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JainJDHVB15,
  author    = {Yogesh M. Jain and
               Aviraj R. Jadhav and
               Harish V. Dixit and
               Akshay S. Hindole and
               Jithin R. Vadakoott and
               Devendra Bilaye},
  title     = {A novel {VLSI} design of {DCTQ} processor for {FPGA} implementation},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208102},
  doi       = {10.1109/ISVDAT.2015.7208102},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JainJDHVB15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JainM15,
  author    = {Nupur Jain and
               Biswajit Mishra},
  title     = {{CORDIC} on a configurable serial architecture for biomedical signal
               processing applications},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208050},
  doi       = {10.1109/ISVDAT.2015.7208050},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JainM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JatanaD15,
  author    = {Shri H. S. Jatana and
               Nilesh M. Desai},
  title     = {{SCL} 180nm {CMOS} foundry: High reliability {ASIC} design for aerospace
               applications},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208163},
  doi       = {10.1109/ISVDAT.2015.7208163},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JatanaD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JungharePP15,
  author    = {Rajesh C. Junghare and
               Vinayak Pachkawade and
               Rajendra M. Patrikar},
  title     = {A 2.47 GHz ultra NanoCrystaline diamond disk resonator with temperature
               compensation for {RF} application},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208119},
  doi       = {10.1109/ISVDAT.2015.7208119},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JungharePP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Kale15,
  author    = {Nitin S. Kale},
  title     = {Introduction to MEMS; their applications as sensors for chemical {\&}
               bio sensing},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208158},
  doi       = {10.1109/ISVDAT.2015.7208158},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Kale15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KaurMD15,
  author    = {Ramandeep Kaur and
               Rahul Malhotra and
               Sujay Deb},
  title     = {{MAC} based {FIR} filter: {A} novel approach for low-power real-time
               de-noising of {ECG} signals},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208065},
  doi       = {10.1109/ISVDAT.2015.7208065},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KaurMD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KaushalDPP15,
  author    = {Shaurya Kaushal and
               Pulkit Kumar Dubey and
               Gaurav Prabhudesai and
               B. D. Pant},
  title     = {Novel design for wideband piezoelectric vibrational energy harvester
               {(P-VEH)}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208140},
  doi       = {10.1109/ISVDAT.2015.7208140},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KaushalDPP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KhotS15,
  author    = {Prashant Khot and
               Rajashekhar B. Shettar},
  title     = {Design of area efficient and low power bandgap voltage reference using
               sub-threshold {MOS} transistors},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208121},
  doi       = {10.1109/ISVDAT.2015.7208121},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KhotS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KiranHKY15,
  author    = {N. Ravi Kiran and
               G. Harish and
               A. Karthik and
               Siva Sankar Yellampalli},
  title     = {Low power and hardware cost {STUMPS} {BIST}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--4},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208125},
  doi       = {10.1109/ISVDAT.2015.7208125},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KiranHKY15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KoringaJS15,
  author    = {Hasmukh P. Koringa and
               Bhushan D. Joshi and
               Vipul Shah},
  title     = {High power gain low noise amplifier design for next generation 1-7GHz
               wideband {RF} frontend {RFIC} using 0.18{\(\mu\)}m {CMOS}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208105},
  doi       = {10.1109/ISVDAT.2015.7208105},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KoringaJS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarCSM15,
  author    = {K. Sudeendra Kumar and
               Rakesh Chanamala and
               Sauvagya Ranjan Sahoo and
               Kamala Kanta Mahapatra},
  title     = {An improved {AES} Hardware Trojan benchmark to validate Trojan detection
               schemes in an {ASIC} design flow},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208064},
  doi       = {10.1109/ISVDAT.2015.7208064},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarCSM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarM15,
  author    = {S. Dinesh Kumar and
               S. K. Noor Mahammad},
  title     = {A novel adiabatic {SRAM} cell implementation using split level charge
               recovery logic},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208071},
  doi       = {10.1109/ISVDAT.2015.7208071},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarP15,
  author    = {Rohit Kumar and
               Manisha Pattanaik},
  title     = {A novel dual multiplier floating point multiply accumulate architecture},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208061},
  doi       = {10.1109/ISVDAT.2015.7208061},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarP15a,
  author    = {S. Santosh Kumar and
               B. D. Pant},
  title     = {Fabrication and characterization of pressure sensor, and enhancement
               of output characteristics by modification of operating pressure range},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--4},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208132},
  doi       = {10.1109/ISVDAT.2015.7208132},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarP15a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarS15,
  author    = {G. Ganesh Kumar and
               Subhendu Kumar Sahoo},
  title     = {Implementation of a high speed multiplier for high-performance and
               low power applications},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--4},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208143},
  doi       = {10.1109/ISVDAT.2015.7208143},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumawatSG15,
  author    = {Renu Kumawat and
               Vineet Sahula and
               Manoj Singh Gaur},
  title     = {Modeling and synthesis of molecular memory},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208081},
  doi       = {10.1109/ISVDAT.2015.7208081},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumawatSG15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/LathaK15,
  author    = {Yericharla Mary Asha Latha and
               Gargi Khanna},
  title     = {Design and simulative analysis of a batteryless Teflon coated capacitive
               pressure sensor for glaucoma diagnosis},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208118},
  doi       = {10.1109/ISVDAT.2015.7208118},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/LathaK15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/LocharlaKMA15,
  author    = {Govinda Rao Locharla and
               K. Sudeendra Kumar and
               Kamala Kanta Mahapatra and
               Samit Ari},
  title     = {Implementation of input data buffering and scheduling methodology
               for 8 parallel {MDC} {FFT}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208107},
  doi       = {10.1109/ISVDAT.2015.7208107},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/LocharlaKMA15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MPM15,
  author    = {Vinay M. M. and
               Roy P. Paily and
               Anil Mahanta},
  title     = {A low-power subthreshold {LNA} for mobile applications},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208134},
  doi       = {10.1109/ISVDAT.2015.7208134},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MPM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MalathiGSV15,
  author    = {D. Malathi and
               R. Greeshma and
               R. Sanjay and
               B. Venkataramani},
  title     = {A 4 bit medium speed flash {ADC} using inverter based comparator in
               0.18{\(\mu\)}m {CMOS}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208069},
  doi       = {10.1109/ISVDAT.2015.7208069},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MalathiGSV15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MalhotraDC15,
  author    = {Rahul Malhotra and
               Sujay Deb and
               Fabio Carlucci},
  title     = {A novel approach to reusable time-economized {STIL} based pattern
               development},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208066},
  doi       = {10.1109/ISVDAT.2015.7208066},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MalhotraDC15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MasraniC15,
  author    = {Mansi S. Masrani and
               Raghavendra Chilukuri},
  title     = {Low-leakage architecture for embedded {ROM}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208151},
  doi       = {10.1109/ISVDAT.2015.7208151},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MasraniC15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MayankM15,
  author    = {Jaishree Mayank and
               Arijit Mondal},
  title     = {Performance optimization of real time control systems using variable
               time period},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208076},
  doi       = {10.1109/ISVDAT.2015.7208076},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MayankM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MeheraCDP15,
  author    = {Ranjan Mehera and
               Arpan Chakraborty and
               Piyali Datta and
               Rajat Kumar Pal},
  title     = {A cost-optimal algorithm for guard zone computation including detection
               and exclusion of overlapping},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208086},
  doi       = {10.1109/ISVDAT.2015.7208086},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MeheraCDP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MehtaDRA15,
  author    = {Jagrat Mehta and
               Anand D. Darji and
               T. V. S. Ram and
               Rajat Arora},
  title     = {Super-scale architecture enhancement of {LEON3} core for {DSP} application},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208067},
  doi       = {10.1109/ISVDAT.2015.7208067},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MehtaDRA15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MishraHM15,
  author    = {Yagya D. Mishra and
               Mohammad S. Hashmi and
               Akhilesh C. Mishra},
  title     = {An efficient approach for estimating the impact of {SSO} noise on
               {LPDDR2} timing budget},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208085},
  doi       = {10.1109/ISVDAT.2015.7208085},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MishraHM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MondalP15,
  author    = {Saroj Mondal and
               Roy P. Paily},
  title     = {An efficient on-chip energy processing circuit for micro-scale energy
               harvesting systems},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208108},
  doi       = {10.1109/ISVDAT.2015.7208108},
  timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MondalP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MousumiGS15,
  author    = {Saha Mousumi and
               Navneet Kumar Gautam and
               Biplab K. Sikdar},
  title     = {A fault tolerant test hardware for {L1} cache module in tile CMPs
               architecture},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208100},
  doi       = {10.1109/ISVDAT.2015.7208100},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MousumiGS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MukherjeeR15,
  author    = {Shyamapada Mukherjee and
               Suchismita Roy},
  title     = {Multi terminal net routing for island style FPGAs using nearly-2-SAT
               computation},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208142},
  doi       = {10.1109/ISVDAT.2015.7208142},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MukherjeeR15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NambisanKP15,
  author    = {Ramprasad Nambisan and
               S. Santosh Kumar and
               B. D. Pant},
  title     = {Sensitivity and non-linearity study and performance enhancement in
               bossed diaphragm piezoresistive pressure sensor},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208104},
  doi       = {10.1109/ISVDAT.2015.7208104},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NambisanKP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NathSDCTS15,
  author    = {Rajdeep Kumar Nath and
               Bibhash Sen and
               Rachit Daga and
               Nilesh Chakraborty and
               Harsh Tibrewal and
               Biplab K. Sikdar},
  title     = {Fault masking in Quantum-dot cellular automata using prohibitive logic
               circuit},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208103},
  doi       = {10.1109/ISVDAT.2015.7208103},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NathSDCTS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NegiM15,
  author    = {Sonam Negi and
               Pitchaiah Madduri},
  title     = {Implementation of high speed radix-10 parallel multiplier using Verilog},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208073},
  doi       = {10.1109/ISVDAT.2015.7208073},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NegiM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NegiM15a,
  author    = {Sonam Negi and
               Pitchaiah Madduri},
  title     = {Implementation of high speed radix-10 parallel multiplier using Verilog},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208074},
  doi       = {10.1109/ISVDAT.2015.7208074},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NegiM15a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PachkawadeJP15,
  author    = {Vinayak Pachkawade and
               Rajesh C. Junghare and
               Rajendra M. Patrikar},
  title     = {A small bandwidth microelectromechanical ring resonator-based bandpass
               filter},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208120},
  doi       = {10.1109/ISVDAT.2015.7208120},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PachkawadeJP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PandeyKSG15,
  author    = {Jai Gopal Pandey and
               Arindam Karmakar and
               Chandra Shekhar and
               S. Gurunarayanan},
  title     = {An embedded framework for accurate object localization using center
               of gravity measure with mean shift procedure},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208135},
  doi       = {10.1109/ISVDAT.2015.7208135},
  timestamp = {Wed, 09 Sep 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PandeyKSG15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PareekG15,
  author    = {Vibhor Pareek and
               Gaurvi Goyal},
  title     = {Area optimized {CMOS} layouts of a 50 Gb/s low power 4: 1 multiplexer},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208054},
  doi       = {10.1109/ISVDAT.2015.7208054},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PareekG15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PariharVP15,
  author    = {Kunal Parihar and
               M. Venkatesh and
               Ravikumar Patel},
  title     = {Realistic dynamic timing verification for complex mixed signal hard
               macro's using {UVM}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208072},
  doi       = {10.1109/ISVDAT.2015.7208072},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PariharVP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ParmarM15,
  author    = {Harikrishna Parmar and
               Usha Sandeep Mehta},
  title     = {A Hamming code based technique to resolve the bit flip impact on compressed
               {VLSI} test data in {IP} core based SoC},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208099},
  doi       = {10.1109/ISVDAT.2015.7208099},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ParmarM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PatelNSAB15,
  author    = {Ronak Patel and
               Amisha Naik and
               Amit Singh and
               Archana Arya and
               Pulkit Bhatnagar},
  title     = {Advanced {UPF} based voltage-aware verification for IOs},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208091},
  doi       = {10.1109/ISVDAT.2015.7208091},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PatelNSAB15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PatelR15,
  author    = {Rajendra Patel and
               Arvind Rajawat},
  title     = {Instruction cache design space exploration for embedded software applications},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208127},
  doi       = {10.1109/ISVDAT.2015.7208127},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PatelR15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PatilRSSV15,
  author    = {Vinayak Patil and
               Aneesh Raveendran and
               P. M. Sobha and
               A. David Selvakumar and
               D. Vivian},
  title     = {Out of order floating point coprocessor for {RISC} {V} {ISA}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--7},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208116},
  doi       = {10.1109/ISVDAT.2015.7208116},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PatilRSSV15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PawanekarT15,
  author    = {Sameer Pawanekar and
               Gaurav Trivedi},
  title     = {{TSV} aware standard cell placement for 3D ICs},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208113},
  doi       = {10.1109/ISVDAT.2015.7208113},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PawanekarT15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PawanekarT15a,
  author    = {Sameer Pawanekar and
               Gaurav Trivedi},
  title     = {Net weighing based timing driven standard cell placer},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208114},
  doi       = {10.1109/ISVDAT.2015.7208114},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PawanekarT15a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PunethaS15,
  author    = {Mayank Punetha and
               Yashvir Singh},
  title     = {An integrable trench {LDMOS} transistor on {SOI} for {RF} power amplifiers
               in PICs},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--4},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208084},
  doi       = {10.1109/ISVDAT.2015.7208084},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PunethaS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RaoOR15,
  author    = {Madhav Rao and
               Neha Oraon and
               S. Ranganatha},
  title     = {Design and simulation of magnetic logic device for next generation
               data processing},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208089},
  doi       = {10.1109/ISVDAT.2015.7208089},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RaoOR15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RashmiSB15,
  author    = {V. S. Rashmi and
               Giridhar Somayaji and
               Sirisha Bhamidipathi},
  title     = {A methodology to reuse random {IP} stimuli in an SoC functional verification
               environment},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208152},
  doi       = {10.1109/ISVDAT.2015.7208152},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RashmiSB15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RaveendranPDSS15,
  author    = {Aneesh Raveendran and
               Vinayak Patil and
               Vivian Desalphine and
               P. M. Sobha and
               A. David Selvakumar},
  title     = {{RISC-V} out-of-order data conversion co-processor},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208117},
  doi       = {10.1109/ISVDAT.2015.7208117},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RaveendranPDSS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ReddyNSV15,
  author    = {Karri Manikantta Reddy and
               Kumar Y. B. Nithin and
               Dheeraj Sharma and
               M. H. Vasantha},
  title     = {Low power, high speed error tolerant multiplier using approximate
               adders},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208150},
  doi       = {10.1109/ISVDAT.2015.7208150},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ReddyNSV15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RitheshHRY15,
  author    = {Munishamanna Rithesh and
               G. Harish and
               B. V. Bhargav Ram and
               Siva Sankar Yellampalli},
  title     = {Detection and analysis of hardware trojan using scan chain method},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208124},
  doi       = {10.1109/ISVDAT.2015.7208124},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RitheshHRY15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RuchiD15,
  author    = {Ruchi and
               S. Dasgupta},
  title     = {Sensitivity analysis of {DRV} for various configurations of {SRAM}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208059},
  doi       = {10.1109/ISVDAT.2015.7208059},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RuchiD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SahooKM15,
  author    = {Sauvagya Ranjan Sahoo and
               K. Sudeendra Kumar and
               Kamalakanta Mahapatra},
  title     = {A novel {ROPUF} for hardware security},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208093},
  doi       = {10.1109/ISVDAT.2015.7208093},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SahooKM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Santhanalakshmi15,
  author    = {M. Santhanalakshmi and
               K. Yasoda},
  title     = {Verilog-A implementation of energy-efficient {SAR} ADCs for biomedical
               application},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208139},
  doi       = {10.1109/ISVDAT.2015.7208139},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Santhanalakshmi15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SarkarK15,
  author    = {Hari Sarkar and
               Sudakshina Kundu},
  title     = {Standby leakage current estimation model for multi threshold {CMOS}
               inverter circuit in deep submicron technology},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208141},
  doi       = {10.1109/ISVDAT.2015.7208141},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SarkarK15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SavaniD15,
  author    = {Vijay Savani and
               N. M. Devashrayee},
  title     = {Analysis {\&} characterization of dual tail current based dynamic
               latch comparator with modified {SR} latch using 90nm technology},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208136},
  doi       = {10.1109/ISVDAT.2015.7208136},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SavaniD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SaxenaSP15,
  author    = {Shanky Saxena and
               Ritu Sharma and
               B. D. Pant},
  title     = {Design and development of cantilever-type {MEMS} based piezoelectric
               energy harvester},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--4},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208045},
  doi       = {10.1109/ISVDAT.2015.7208045},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SaxenaSP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShahMS15,
  author    = {Toral Shah and
               Anzhela Yu. Matrosova and
               Virendra Singh},
  title     = {{PDF} testability of a combinational circuit derived by covering {ROBDD}
               nodes using Invert-And-Or circuits},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208130},
  doi       = {10.1109/ISVDAT.2015.7208130},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ShahMS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Sharma15,
  author    = {Anil Sharma},
  title     = {Design and analysis of a touch mode {MEMS} capacitive pressure sensor
               for {IUPC}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208106},
  doi       = {10.1109/ISVDAT.2015.7208106},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Sharma15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaMADB15,
  author    = {Arvind Kumar Sharma and
               Neeraj Mishra and
               Naushad Alam and
               Sudeb Dasgupta and
               Anand Bulusu},
  title     = {Pre-layout estimation of performance and design of basic analog circuits
               in stress enabled technologies},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208062},
  doi       = {10.1109/ISVDAT.2015.7208062},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SharmaMADB15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaPD15,
  author    = {Priyanka Sharma and
               Sunil Pandey and
               Pravin A. Dwaramwar},
  title     = {An inductorless receiver front-end for multiband wireless applications},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208070},
  doi       = {10.1109/ISVDAT.2015.7208070},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SharmaPD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaUALBGZ15,
  author    = {Ashish Sharma and
               Prachi Upadhyay and
               Ruby Ansar and
               Vijay Laxmi and
               Lava Bhargava and
               Manoj Singh Gaur and
               Mark Zwolinski},
  title     = {A framework for thermal aware reliability estimation in 2D NoC},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208063},
  doi       = {10.1109/ISVDAT.2015.7208063},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SharmaUALBGZ15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghD15,
  author    = {Namrata Singh and
               Sujay Deb},
  title     = {Analysis and design guidelines for customized logic families in {CMOS}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208133},
  doi       = {10.1109/ISVDAT.2015.7208133},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinhaNH15,
  author    = {Rohan Sinha and
               Bhawana Singh Nirwan and
               Mohammad S. Hashmi},
  title     = {A new row decoding architecture for fast wordline charging in {NOR}
               type Flash memories},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208131},
  doi       = {10.1109/ISVDAT.2015.7208131},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinhaNH15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinhaS15,
  author    = {Rohan Sinha and
               Pranay Samanta},
  title     = {Analysis of stability and different speed boosting assist techniques
               towards the design and optimization of high speed {SRAM} cell},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208097},
  doi       = {10.1109/ISVDAT.2015.7208097},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinhaS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SkaggsRRBP15,
  author    = {Michael Skaggs and
               Sushmita Kadiyala Rao and
               Ryan W. Robucci and
               Nilanjan Banerjee and
               Chintan Patel},
  title     = {Transient current estimation using {S3C} (Standard cell current transient
               characterization)},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208110},
  doi       = {10.1109/ISVDAT.2015.7208110},
  timestamp = {Tue, 07 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SkaggsRRBP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Sudha15,
  author    = {N. Sudha},
  title     = {Multicore processor - Architecture and programming},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208159},
  doi       = {10.1109/ISVDAT.2015.7208159},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Sudha15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SudhaC15,
  author    = {N. Sudha and
               D. Bharat Chandrahas},
  title     = {A pipelined memory-efficient architecture for face detection and tracking
               on a multicore environment},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208145},
  doi       = {10.1109/ISVDAT.2015.7208145},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SudhaC15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/TalatuleZZ15,
  author    = {Samta D. Talatule and
               Pravin Zode and
               Pradnya Zode},
  title     = {A secure architecture for the design for testability structures},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208090},
  doi       = {10.1109/ISVDAT.2015.7208090},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/TalatuleZZ15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Talukdar15,
  author    = {Priyankar Talukdar},
  title     = {On logic depth per pipelining stage with power aware flop, wave and
               hybrid pipelining with gate size and area constraints},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208053},
  doi       = {10.1109/ISVDAT.2015.7208053},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Talukdar15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Talukdar15a,
  author    = {Priyankar Talukdar},
  title     = {{BONY:} An algorithm to generate large synthetic combinational benchmark
               circuits},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208094},
  doi       = {10.1109/ISVDAT.2015.7208094},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Talukdar15a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/TewariS15,
  author    = {Shikhar Tewari and
               Kirmender Singh},
  title     = {Intuitive design of {PTAT} and {CTAT} circuits for {MOSFET} based
               temperature sensor using Inversion Coefficient based approach},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208077},
  doi       = {10.1109/ISVDAT.2015.7208077},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/TewariS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/TrivediDMDP15,
  author    = {Rakesh Trivedi and
               N. M. Devashrayee and
               Usha Sandeep Mehta and
               N. M. Desai and
               Himanshu Patel},
  title     = {Development of Radiation Hardened by Design(RHBD) primitive gates
               using 0.18{\(\mu\)}m {CMOS} technology},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208046},
  doi       = {10.1109/ISVDAT.2015.7208046},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/TrivediDMDP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/UpadhyaySS15,
  author    = {Darshana Upadhyay and
               Trishla Shah and
               Priyanka Sharma},
  title     = {Cryptanalysis of hardware based stream ciphers and implementation
               of {GSM} stream cipher to propose a novel approach for designing n-bit
               {LFSR} stream cipher},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208129},
  doi       = {10.1109/ISVDAT.2015.7208129},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/UpadhyaySS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/VanapalliKD15,
  author    = {Kartheek Vanapalli and
               Hemangee K. Kapoor and
               Shirshendu Das},
  title     = {An efficient searching mechanism for dynamic {NUCA} in chip multiprocessors},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208079},
  doi       = {10.1109/ISVDAT.2015.7208079},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/VanapalliKD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/VarshaARP15,
  author    = {Rangwani Varsha and
               Rajat Arora and
               T. V. S. Ram and
               Amit Patel},
  title     = {Design and implementation of {DVB-S2} transport stream for onboard
               processing satellite},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208128},
  doi       = {10.1109/ISVDAT.2015.7208128},
  timestamp = {Fri, 17 Apr 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/VarshaARP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/VermaP15,
  author    = {Gagan Deep Verma and
               Manisha Pattanaik},
  title     = {Performance study of side block oxide band gap engineered {SONOS:}
               {A} device simulation approach},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--4},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208146},
  doi       = {10.1109/ISVDAT.2015.7208146},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/VermaP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/WadhwaT15,
  author    = {Sanjay Kumar Wadhwa and
               Avinash Chandra Tripathi},
  title     = {Measurement of de-assertion threshold of power-on-reset circuits},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--4},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208109},
  doi       = {10.1109/ISVDAT.2015.7208109},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/WadhwaT15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/WarisMKMC15,
  author    = {Mohammad Waris and
               Urvi Mehta and
               Rajiv Kumaran and
               Sanjeev Mehta and
               Arup Roy Chowdhury},
  title     = {An all digital delay lock loop architecture for high precision timing
               generator},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--6},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208138},
  doi       = {10.1109/ISVDAT.2015.7208138},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/WarisMKMC15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/YadavDJG15,
  author    = {Jitendra Yadav and
               Pallavi Das and
               Abhinav Jain and
               Anuj Grover},
  title     = {Area compact 5T portless {SRAM} cell for high density cache in 65nm
               {CMOS}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--4},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208095},
  doi       = {10.1109/ISVDAT.2015.7208095},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/YadavDJG15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/YadavLGB15,
  author    = {Sonal Yadav and
               Vijay Laxmi and
               Manoj Singh Gaur and
               Megha Bhargava},
  title     = {C\({}^{\mbox{2}}\)-DLM: Cache coherence aware dual link mesh for on-chip
               interconnect},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208068},
  doi       = {10.1109/ISVDAT.2015.7208068},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/YadavLGB15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/YadavSSCMSK15,
  author    = {Jitendra Yadav and
               Soumendu Sinha and
               Amit Sharma and
               Rekha Chaudhary and
               Ravindra Mukhiya and
               Rishi Sharma and
               Vinod K. Khanna},
  title     = {Simulation and characterization of dual-gate {SOI} MOSFET, on-chip
               fabricated with {ISFET}},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--5},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208080},
  doi       = {10.1109/ISVDAT.2015.7208080},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/YadavSSCMSK15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ZodeD15,
  author    = {Pravin Zode and
               Raghavendra B. Deshmukh},
  title     = {Side channel attack resistant architecture for elliptic curve cryptography},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208123},
  doi       = {10.1109/ISVDAT.2015.7208123},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ZodeD15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vdat/2015,
  title     = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7166536/proceeding},
  isbn      = {978-1-4799-1743-3},
  timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/2015.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BairagiP14,
  author    = {Debayan Bairagi and
               Soumya Pandit},
  title     = {Study of reverse substrate bias effect of 22nm node epitaxial delta
               doped channel {MOS} transistor for low power SoC applications},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881050},
  doi       = {10.1109/ISVDAT.2014.6881050},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BairagiP14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BanerjeeM14,
  author    = {Sabyasachee Banerjee and
               Subhashis Majumder},
  title     = {A thermal aware 3D {IC} partitioning technique},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881069},
  doi       = {10.1109/ISVDAT.2014.6881069},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BanerjeeM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BanerjeeMS14,
  author    = {Kunal Banerjee and
               Chittaranjan A. Mandal and
               Dipankar Sarkar},
  title     = {Extending the scope of translation validation by augmenting path based
               equivalence checkers with {SMT} solvers},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881061},
  doi       = {10.1109/ISVDAT.2014.6881061},
  timestamp = {Sat, 04 Apr 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BanerjeeMS14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BassiP14,
  author    = {Shipra Bassi and
               Manisha Pattanaik},
  title     = {{TID} effects on retention of 0.13 {\(\mu\)}m {SONOS} memory cell:
               {A} device simulation approach},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881090},
  doi       = {10.1109/ISVDAT.2014.6881090},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BassiP14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BhakthavatchaluKVD14,
  author    = {Ramesh Bhakthavatchalu and
               Sreeja Krishnan and
               V. Vineeth and
               M. Nirmala Devi},
  title     = {Deterministic seed selection and pattern reduction in Logic {BIST}},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881039},
  doi       = {10.1109/ISVDAT.2014.6881039},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BhakthavatchaluKVD14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BishnoiSLGS14,
  author    = {Rimpy Bishnoi and
               Pankaj Kumar Srivastava and
               Vijay Laxmi and
               Manoj Singh Gaur and
               Apoorva Sikka},
  title     = {Distributed adaptive routing for spidergon NoC},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881058},
  doi       = {10.1109/ISVDAT.2014.6881058},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BishnoiSLGS14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChandaCNM14,
  author    = {Manash Chanda and
               Ananda Sankar Chakraborty and
               S. Nag and
               R. Modak},
  title     = {Design of sequential circuits using single-clocked Energy efficient
               adiabatic Logic for ultra low power application},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881076},
  doi       = {10.1109/ISVDAT.2014.6881076},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChandaCNM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChatterjeePC14,
  author    = {Navonil Chatterjee and
               N. Prasad and
               Santanu Chattopadhyay},
  title     = {A spare link based reliable Network-on-Chip design},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881036},
  doi       = {10.1109/ISVDAT.2014.6881036},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChatterjeePC14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DalaiKSA14,
  author    = {Bijay Kumar Dalai and
               N. Karnnan and
               Arvind Kumar Sharma and
               Bulusu Anand},
  title     = {An empirical delta delay model for highly scaled {CMOS} inverter considering
               Well Proximity Effect},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881062},
  doi       = {10.1109/ISVDAT.2014.6881062},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DalaiKSA14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasD14,
  author    = {Somak Das and
               Sowvik Dey},
  title     = {Design of a fault tolerant low-order interleaved memory based on the
               concept of bubble-stack an image storage perspective},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881087},
  doi       = {10.1109/ISVDAT.2014.6881087},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasD14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasM14,
  author    = {Palash Das and
               Bikromadittya Mondal},
  title     = {Signature analysis for synthesis of reversible circuit},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881043},
  doi       = {10.1109/ISVDAT.2014.6881043},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasSRR14,
  author    = {Indrajit Das and
               Manodipan Sahoo and
               Pranab Roy and
               Hafizur Rahaman},
  title     = {A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s {SAR} {ADC} for digital microfluidic
               biochip applications},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881068},
  doi       = {10.1109/ISVDAT.2014.6881068},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasSRR14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DeBM14,
  author    = {Partha De and
               Kunal Banerjee and
               Chittaranjan A. Mandal},
  title     = {A {BDD} based secure hardware design method to guard against power
               analysis attacks},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881088},
  doi       = {10.1109/ISVDAT.2014.6881088},
  timestamp = {Sat, 04 Apr 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DeBM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DebD14,
  author    = {Arighna Deb and
               Debesh Kumar Das},
  title     = {A regular network of symmetric functions in quantum-dot cellular automata},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881080},
  doi       = {10.1109/ISVDAT.2014.6881080},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DebD14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DuttaBR14,
  author    = {Pratik Dutta and
               Chandan Bandyopadhyay and
               Hafizur Rahaman},
  title     = {All optical implementation of Mach-Zehnder interferometer based reversible
               sequential circuit},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881079},
  doi       = {10.1109/ISVDAT.2014.6881079},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DuttaBR14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GhoshDH14,
  author    = {Amitava Ghosh and
               Anindya Sundar Dhar and
               Achintya Halder},
  title     = {An ultra low power {MICS/ISM} band transmitter in 0.18 {\(\mu\)}m
               {CMOS}},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881077},
  doi       = {10.1109/ISVDAT.2014.6881077},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GhoshDH14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GhoshR14,
  author    = {Kasturi Ghosh and
               Baidya Nath Ray},
  title     = {Design of a new high order {OTA-C} filter structure and its specification
               based testing},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881074},
  doi       = {10.1109/ISVDAT.2014.6881074},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GhoshR14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GlittasL14,
  author    = {Antony Xavier Glittas and
               Gopalakrishnan Lakshminarayanan},
  title     = {Pipelined {FFT} architectures for real-time signal processing and
               wireless communication applications},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881052},
  doi       = {10.1109/ISVDAT.2014.6881052},
  timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GlittasL14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GourNSS14,
  author    = {Pranav Narayan Gour and
               Sujay Narumanchi and
               Sumeet Saurav and
               Sanjay Singh},
  title     = {Hardware accelerator for real-time image resizing},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881070},
  doi       = {10.1109/ISVDAT.2014.6881070},
  timestamp = {Wed, 20 Nov 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/GourNSS14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JSC14,
  author    = {Soumya J. and
               Ashish Sharma and
               Santanu Chattopadhyay},
  title     = {A locally reconfigurable Network-on-Chip architecture and application
               mapping onto it},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881041},
  doi       = {10.1109/ISVDAT.2014.6881041},
  timestamp = {Wed, 23 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JSC14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JosephFHRJP14,
  author    = {Fradaric Joseph and
               Kiran Francis and
               Archita Hore and
               Siddhanta Roy and
               S. Josephine and
               Roy P. Paily},
  title     = {An efficient hardware architecture for stereo disparity estimation},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881049},
  doi       = {10.1109/ISVDAT.2014.6881049},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JosephFHRJP14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KamalB14,
  author    = {Akhila Kamal and
               Bindu Boby},
  title     = {Design of tunnel {FET} based low power digital circuits},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881075},
  doi       = {10.1109/ISVDAT.2014.6881075},
  timestamp = {Wed, 01 Jan 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KamalB14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KarmakarAC14,
  author    = {Rajit Karmakar and
               Aditya Agarwal and
               Santanu Chattopadhyay},
  title     = {Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip
               test scheduling using window-based peak power model},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881089},
  doi       = {10.1109/ISVDAT.2014.6881089},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KarmakarAC14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KaushikSSSM14,
  author    = {Bhavit Kaushik and
               Ravi Saini and
               Anil K. Saini and
               Sanjay Singh and
               A. S. Mandal},
  title     = {An {FPGA} implementation of image signature based visual-saliency
               detection},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881060},
  doi       = {10.1109/ISVDAT.2014.6881060},
  timestamp = {Wed, 20 Nov 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/KaushikSSSM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KothaBJK14,
  author    = {Srinivasa Reddy Kotha and
               Devendra Bilaye and
               Utkarsh Jain and
               Sahoo Subhendu Kumar},
  title     = {An approach for efficient {FIR} filter design for hearing aid application},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881051},
  doi       = {10.1109/ISVDAT.2014.6881051},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KothaBJK14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KothaBK14,
  author    = {Srinivasa Reddy Kotha and
               Sumit Bajaj and
               Sahoo Subhendu Kumar},
  title     = {An {LUT} based {RNS} {FIR} filter implementation for reconfigurable
               applications},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881047},
  doi       = {10.1109/ISVDAT.2014.6881047},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KothaBK14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarK14,
  author    = {Apoorv Kumar and
               Hemangee K. Kapoor},
  title     = {Modelling and analysis of wireless communication over Networks-on-Chip},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881044},
  doi       = {10.1109/ISVDAT.2014.6881044},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarK14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarKP14,
  author    = {Vivek Kumar and
               Vinay B. Y. Kumar and
               Sachin B. Patkar},
  title     = {FPGA-based implementation of {M4RM} for matrix multiplication over
               {GF(2)}},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881072},
  doi       = {10.1109/ISVDAT.2014.6881072},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarKP14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarS14,
  author    = {P. Saidesh Kumar and
               M. A. Seenivasan},
  title     = {A 32{\texttimes}32 {CMOS} image sensor: Tested using process and temperature
               compensated voltage controlled current source},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881073},
  doi       = {10.1109/ISVDAT.2014.6881073},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarS14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MajumdarZB14,
  author    = {Shubhankar Majumdar and
               Mohd. Zuhair and
               Dhrubes Biswas},
  title     = {Artificial neural network modelling of {ADS} designed Double Pole
               Double Throw switch},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881066},
  doi       = {10.1109/ISVDAT.2014.6881066},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MajumdarZB14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ManikandanVCA14,
  author    = {R. R. Manikandan and
               Venkata Narayana Rao Vanukuru and
               Anjan Chakravorty and
               Bharadwaj S. Amrutur},
  title     = {Design and modeling of high-Q variable width and spacing, planar and
               3-D stacked spiral inductors},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881053},
  doi       = {10.1109/ISVDAT.2014.6881053},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ManikandanVCA14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MeenaKC14,
  author    = {Narendra Kumar Meena and
               Hemangee K. Kapoor and
               Shounak Chakraborty},
  title     = {A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881040},
  doi       = {10.1109/ISVDAT.2014.6881040},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MeenaKC14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NehraPKD14,
  author    = {Dilsukh Nehra and
               Pankaj Kumar Pal and
               Brajesh Kumar Kaushik and
               S. Dasgupta},
  title     = {High permittivity spacer effects on junctionless FinFET based circuit/SRAM
               applications},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881054},
  doi       = {10.1109/ISVDAT.2014.6881054},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NehraPKD14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NguyenSMC14,
  author    = {Phuong Ha Nguyen and
               Durga Prasad Sahoo and
               Debdeep Mukhopadhyay and
               Rajat Subhra Chakraborty},
  title     = {Cryptanalysis of Composite PUFs (Extended abstract-invited talk)},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881035},
  doi       = {10.1109/ISVDAT.2014.6881035},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NguyenSMC14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PandeyKG14,
  author    = {Jai Gopal Pandey and
               Arindam Karmakar and
               S. Gurunarayanan},
  title     = {Architectures and algorithms for image and video processing using
               FPGA-based platform},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881081},
  doi       = {10.1109/ISVDAT.2014.6881081},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PandeyKG14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PanigrahyCD14,
  author    = {Mamata Panigrahy and
               Indrajit Chakrabarti and
               Anindya Sundar Dhar},
  title     = {{VLSI} design of fast fractal image encoder},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881071},
  doi       = {10.1109/ISVDAT.2014.6881071},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PanigrahyCD14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ParsediyaSK14,
  author    = {Deep Kishore Parsediya and
               Jawar Singh and
               Pavan Kumar Kankar},
  title     = {Modeling and simulation of variable thickness based stepped {MEMS}
               cantilever designs for biosensing and pull-in voltage optimization},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881055},
  doi       = {10.1109/ISVDAT.2014.6881055},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/ParsediyaSK14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PatriACP14,
  author    = {Sreehari Rao Patri and
               Suresh Alapati and
               Surendra Chowdary and
               K. S. R. Krishna Prasad},
  title     = {250mA ultra low drop out regulator with high slew rate double recycling
               folded cascode error amplifier},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881067},
  doi       = {10.1109/ISVDAT.2014.6881067},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PatriACP14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PrajapatiYPS14,
  author    = {Ekta Prajapati and
               Nandakishor Yadav and
               Manisha Pattanaik and
               G. K. Sharma},
  title     = {Operation-aware assist circuit design for improved write performance
               of FinFET based {SRAM}},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881063},
  doi       = {10.1109/ISVDAT.2014.6881063},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PrajapatiYPS14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/Puppala14,
  author    = {Venkata Ganapathi Puppala},
  title     = {A VLIW-Vector co-processor design for accelerating Basic Linear Algebraic
               Operations in OpenCV},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881085},
  doi       = {10.1109/ISVDAT.2014.6881085},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/Puppala14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PyneP14,
  author    = {Sumanta Pyne and
               Ajit Pal},
  title     = {Loop unrolling with fine grained power gating for runtime leakage
               power reduction},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881084},
  doi       = {10.1109/ISVDAT.2014.6881084},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PyneP14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RanjithM14,
  author    = {M. E. Jayasanthi Ranjith and
               N. J. R. Muniraj},
  title     = {{VLSI} implementation of novel fast confluence {ICA} algorithm for
               signal processing applications},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881086},
  doi       = {10.1109/ISVDAT.2014.6881086},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RanjithM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RayS14,
  author    = {Swarnendu Ray and
               Arnab Sarkar},
  title     = {A Pseudo-Deadline Based {O(1)} proportional share scheduler for embedded
               systems},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881083},
  doi       = {10.1109/ISVDAT.2014.6881083},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RayS14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RomiAY14,
  author    = {Mohammad Shueb Romi and
               Naushad Alam and
               Mohd Yusuf Yasin},
  title     = {An analytical delay model for {CMOS} Inverter-Transmission Gate structure},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881038},
  doi       = {10.1109/ISVDAT.2014.6881038},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RomiAY14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SahaKS14,
  author    = {Sumit Saha and
               Bapi Kar and
               Susmita Sur{-}Kolay},
  title     = {A novel architecture for {QPSK} modulation based on time-mode signal
               processing},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881056},
  doi       = {10.1109/ISVDAT.2014.6881056},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SahaKS14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SamantaCDG14,
  author    = {Pranay Samanta and
               Deepak Chauhan and
               Sujay Deb and
               Piyush Kumar Gupta},
  title     = {{UVM} based {STBUS} verification {IP} for verifying SoC architectures},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881037},
  doi       = {10.1109/ISVDAT.2014.6881037},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SamantaCDG14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SamantaER14,
  author    = {Radhamanjari Samanta and
               Adil I. Erzin and
               Soumyendu Raha},
  title     = {Timing-driven Steiner tree construction on uniform {\(\lambda\)}-geometry},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--4},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881082},
  doi       = {10.1109/ISVDAT.2014.6881082},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SamantaER14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SaravananKPS14,
  author    = {P. Saravanan and
               P. Kalpana and
               V. Prcethisri and
               V. Sneha},
  title     = {Power analysis attack using neural networks with wavelet transform
               as pre-processor},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881059},
  doi       = {10.1109/ISVDAT.2014.6881059},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SaravananKPS14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SauP14,
  author    = {Swagata Saha Sau and
               Rajat Kumar Pal},
  title     = {A re-router for optimizing wire length in two-and four-layer no-dogleg
               channel routing},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881057},
  doi       = {10.1109/ISVDAT.2014.6881057},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SauP14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghSSSSV14,
  author    = {Sanjay Singh and
               Sumeet Saurav and
               Ravi Saini and
               Anil K. Saini and
               Chandra Shekhar and
               Anil Vohra},
  title     = {Automatic real-time extraction of focused regions in a live video
               stream using edge width information},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881046},
  doi       = {10.1109/ISVDAT.2014.6881046},
  timestamp = {Wed, 09 Sep 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghSSSSV14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghSSSSV14a,
  author    = {Sanjay Singh and
               Ravi Saini and
               Sumeet Saurav and
               Anil K. Saini and
               Chandra Shekhar and
               Anil Vohra},
  title     = {FPGA-based real-time object tracker using modified particle filtering
               and {SAD} computation},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881045},
  doi       = {10.1109/ISVDAT.2014.6881045},
  timestamp = {Wed, 09 Sep 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghSSSSV14a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinhaHK14,
  author    = {Rohan Sinha and
               Mohammad S. Hashmi and
               G. Anil Kumar},
  title     = {A positive level shifter for high speed symmetric switching in flash
               memories},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881064},
  doi       = {10.1109/ISVDAT.2014.6881064},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinhaHK14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SreehariDKAP14,
  author    = {Patri Sreehari and
               Pavankumarsharma Devulapalli and
               Dhananjay Kewale and
               Omkar Asbe and
               K. S. R. Krishna Prasad},
  title     = {Power optimized {PLL} implementation in 180nm {CMOS} technology},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881065},
  doi       = {10.1109/ISVDAT.2014.6881065},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SreehariDKAP14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SubramanyamSV14,
  author    = {Kasturi Subramanyam and
               Sadulla Shaik and
               Ramesh Vaddi},
  title     = {Tunnel {FET} based low voltage static vs dynamic logic families for
               energy efficiency},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881042},
  doi       = {10.1109/ISVDAT.2014.6881042},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SubramanyamSV14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ThakyalM14,
  author    = {Prateek Thakyal and
               Prabhat Mishra},
  title     = {Layout-aware signal selection in reconfigurable architectures},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--6},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881078},
  doi       = {10.1109/ISVDAT.2014.6881078},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ThakyalM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/YadavB14,
  author    = {Vimal Kumar Singh Yadav and
               Ratul Kr. Baruah},
  title     = {An analytic potential and threshold voltage model for short-channel
               symmetric double-gate {MOSFET}},
  booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISVDAT.2014.6881048},
  doi       = {10.1109/ISVDAT.2014.6881048},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/YadavB14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vdat/2014,
  title     = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
               Coimbatore, India, July 16-18, 2014},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/6873898/proceeding},
  isbn      = {978-1-4799-5088-1},
  timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/2014.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AgrawalA13,
  author    = {Madhusoodan Agrawal and
               Alpana Agarwal},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {A Combined {CMOS} Reference Circuit with Supply and Temperature Compensation},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {177--184},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_22},
  doi       = {10.1007/978-3-642-42024-5\_22},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AgrawalA13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AgrawalPSK13,
  author    = {Sachin Agrawal and
               Sunil Kumar Pandey and
               Jawar Singh and
               Pravin Neminath Kondekar},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {An Efficient {RF} Energy Harvester with Tuned Matching Circuit},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {138--145},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_17},
  doi       = {10.1007/978-3-642-42024-5\_17},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/AgrawalPSK13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AlagappanA13,
  author    = {Chidambaram Alagappan and
               Vishwani D. Agrawal},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Defect Diagnosis of Digital Circuits Using Surrogate Faults},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {376--386},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_44},
  doi       = {10.1007/978-3-642-42024-5\_44},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AlagappanA13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AlamDMP13,
  author    = {Akhtar W. Alam and
               Esakkimuthu Dhakshinamoorthy and
               Prince Mathew and
               Narender Ponna},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {A Novel Input Capacitance Modeling Methodology for Nano-Scale {VLSI}
               Standard Cell Library Characterization},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {44--48},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_6},
  doi       = {10.1007/978-3-642-42024-5\_6},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AlamDMP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AnwarAK13,
  author    = {Mohd Anwar and
               Syed Azeemuddin and
               Mohammed Zafar Ali Khan},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Design and Analysis of a Novel Noise Cancelling Topology for Common
               Gate {UWB} LNAs},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {169--176},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_21},
  doi       = {10.1007/978-3-642-42024-5\_21},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AnwarAK13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BaruahP13,
  author    = {Ratul Kumar Baruah and
               Roy P. Paily},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {A Dual Material Double-Layer Gate Stack Junctionless Transistor for
               Enhanced Analog Performance},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {118--127},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_15},
  doi       = {10.1007/978-3-642-42024-5\_15},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BaruahP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BhattacharyaBSBK13,
  author    = {Arani Bhattacharya and
               Ansuman Banerjee and
               Susmita Sur{-}Kolay and
               Prasenjit Basu and
               Bhaskar J. Karmakar},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {A Cache-Aware Strategy for {H.264} Decoding on Multi-processor Architectures},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {194--203},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_24},
  doi       = {10.1007/978-3-642-42024-5\_24},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BhattacharyaBSBK13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BishnoiLGB13,
  author    = {Rimpy Bishnoi and
               Vijay Laxmi and
               Manoj Singh Gaur and
               Mohit Baskota},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Fault Aware Dynamic Adaptive Routing Using {LBDR}},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {304--311},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_36},
  doi       = {10.1007/978-3-642-42024-5\_36},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BishnoiLGB13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/CherukatS13,
  author    = {Saima Cherukat and
               Vineet Sahula},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Variation Robust Subthreshold {SRAM} Design with Ultra Low Power Consumption},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {242--248},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_29},
  doi       = {10.1007/978-3-642-42024-5\_29},
  timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/CherukatS13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasPHK13,
  author    = {Shirshendu Das and
               Nagaraju Polavarapu and
               Prateek D. Halwe and
               Hemangee K. Kapoor},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Random-LRU: {A} Replacement Policy for Chip Multiprocessors},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {204--213},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_25},
  doi       = {10.1007/978-3-642-42024-5\_25},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasPHK13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GhoshS13,
  author    = {Sandip Ghosh and
               Rohit Srivastava},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {{CPK} Based {IO} {AC} Timing Closure to Reduce Yield Loss and Test
               Time},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {257--266},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_31},
  doi       = {10.1007/978-3-642-42024-5\_31},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GhoshS13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuhaC13,
  author    = {Anirban Guha and
               Shubhajit Roy Chowdhury},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {{CMOS} {ASIC} Design of a High Performance Digital Fuzzy Processor
               That Can Compute on Arbitrary Membership Functions},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {233--241},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_28},
  doi       = {10.1007/978-3-642-42024-5\_28},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GuhaC13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JainK13,
  author    = {Anita Jain and
               Kavita Khare},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {3D {CORDIC} Algorithm Based Cartesian to Spherical Coordinate Converter},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {337--344},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_40},
  doi       = {10.1007/978-3-642-42024-5\_40},
  timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JainK13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JosephP13,
  author    = {Jose Joseph and
               Rajendra M. Patrikar},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Impact of Fin Width and Graded Channel Doping on the Performance of
               22nm {SOI} FinFET},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {153--159},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_19},
  doi       = {10.1007/978-3-642-42024-5\_19},
  timestamp = {Thu, 13 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JosephP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KordeKDP13,
  author    = {Shrirang Korde and
               Amol Khandare and
               Raghavendra B. Deshmukh and
               Rajendra M. Patrikar},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Computational Functions' {VLSI} Implementation for Compressed Sensing},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {35--43},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_5},
  doi       = {10.1007/978-3-642-42024-5\_5},
  timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KordeKDP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KrishnamurthyS13,
  author    = {Rahul Krishnamurthy and
               G. K. Sharma},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {An Area Efficient Wide Range On-Chip Delay Measurement Architecture},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {49--58},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_7},
  doi       = {10.1007/978-3-642-42024-5\_7},
  timestamp = {Wed, 17 Jul 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KrishnamurthyS13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarMKD13,
  author    = {Jainender Kumar and
               Manoj Kumar Majumder and
               Brajesh Kumar Kaushik and
               Sudeb Dasgupta},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Analysis of Crosstalk Deviation for Bundled {MWCNT} with Process Induced
               Height and Width Variations},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {214--222},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_26},
  doi       = {10.1007/978-3-642-42024-5\_26},
  timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarMKD13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/LamZ13,
  author    = {Kai Chi Alex Lam and
               Mark Zwolinski},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Circuit Transient Analysis Using State Space Equations},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {330--336},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_39},
  doi       = {10.1007/978-3-642-42024-5\_39},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/LamZ13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MaheshGKP13,
  author    = {R. K. Naga Mahesh and
               Akash Ganesan and
               Manchi Pavan Kumar and
               Roy Paily},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area
               Network},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {26--34},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_4},
  doi       = {10.1007/978-3-642-42024-5\_4},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MaheshGKP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MaheshwariRG13,
  author    = {Sachin Maheshwari and
               Himadri Singh Raghav and
               Anu Gupta},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Characterization of Logical Effort for Improved Delay},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {108--117},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_14},
  doi       = {10.1007/978-3-642-42024-5\_14},
  timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MaheshwariRG13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MaheshwariRKG13,
  author    = {Sachin Maheshwari and
               Rameez Raza and
               Pramod Kumar and
               Anu Gupta},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Convex Optimization of Energy and Delay Using Logical Effort Method
               in Deep Sub-micron Technology},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {185--193},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_23},
  doi       = {10.1007/978-3-642-42024-5\_23},
  timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MaheshwariRKG13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MannaSCS13,
  author    = {Kanchan Manna and
               Shailesh Singh and
               Santanu Chattopadhyay and
               Indranil Sengupta},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm
               Optimization},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {74--82},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_10},
  doi       = {10.1007/978-3-642-42024-5\_10},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MannaSCS13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MondalDKRB13,
  author    = {Joyati Mondal and
               Debesh Kumar Das and
               Dipak Kumar Kole and
               Hafizur Rahaman and
               Bhargab B. Bhattacharya},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {On Designing Testable Reversible Circuits Using Gate Duplication},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {322--329},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_38},
  doi       = {10.1007/978-3-642-42024-5\_38},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MondalDKRB13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MukherjeePR13,
  author    = {Shyamapada Mukherjee and
               Jibesh Patra and
               Suchismita Roy},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Congestion Balancing Global Router},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {223--232},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_27},
  doi       = {10.1007/978-3-642-42024-5\_27},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MukherjeePR13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NathCP13,
  author    = {Debanjali Nath and
               Priyanka Choudhury and
               Sambhu Nath Pradhan},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Power Reduction by Integrated Within{\_}Clock{\_}Power Gating and
               Power Gating (WCPG{\_}in{\_}PG)},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {160--168},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_20},
  doi       = {10.1007/978-3-642-42024-5\_20},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NathCP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NavlakhaGBS13,
  author    = {Nupur Navlakha and
               Lokesh Garg and
               Dharmendar Boolchandani and
               Vineet Sahula},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Architectural Level Sub-threshold Leakage Power Estimation of {SRAM}
               Arrays with its Peripherals},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {312--321},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_37},
  doi       = {10.1007/978-3-642-42024-5\_37},
  timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NavlakhaGBS13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NinanSR13,
  author    = {Cerin Ninan and
               Chandra Shekhar and
               M. Radhakrishna},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Design and Optimization of a 2x2 Directional Microstrip Patch Antenna},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {353--360},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_42},
  doi       = {10.1007/978-3-642-42024-5\_42},
  timestamp = {Thu, 13 Feb 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/NinanSR13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PalKD13,
  author    = {Pankaj Kr. Pal and
               Brajesh Kumar Kaushik and
               Sudeb Dasgupta},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Optimization of Underlap FinFETs and Its {SRAM} Performance Projections
               Using High-\emph{k} Spacers},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {267--273},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_32},
  doi       = {10.1007/978-3-642-42024-5\_32},
  timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PalKD13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PaulDP13,
  author    = {Somnath Paul and
               Abhijit Dana and
               Soumya Pandit},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {An Improved \emph{g} \({}_{\mbox{ \emph{m} }}\)/\emph{I} \({}_{\mbox{
               \emph{D} }}\) Methodology for Ultra-Low-Power Nano-Scale {CMOS} {OTA}
               Design},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {128--137},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_16},
  doi       = {10.1007/978-3-642-42024-5\_16},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PaulDP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PawanekarKT13,
  author    = {Sameer Pawanekar and
               Kalpesh Kapoor and
               Gaurav Trivedi},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Kapees: {A} New Tool for Standard Cell Placement},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {66--73},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_9},
  doi       = {10.1007/978-3-642-42024-5\_9},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PawanekarKT13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PyneP13,
  author    = {Sumanta Pyne and
               Ajit Pal},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Energy Efficient Array Initialization Using Loop Unrolling with Partial
               Gray Code Sequence},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {83--93},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_11},
  doi       = {10.1007/978-3-642-42024-5\_11},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/PyneP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RaghavMS13,
  author    = {Himadri Singh Raghav and
               Sachin Maheshwari and
               B. Prasad Singh},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for
               Worst-Case-Delay and Power in Sub-micron Technology},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {100--107},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_13},
  doi       = {10.1007/978-3-642-42024-5\_13},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RaghavMS13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RajahariVB13,
  author    = {Gudlavalleti Rajahari and
               Yashu Anand Varshney and
               Subash Chandra Bose},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {A Novel Design Methodology for High Tuning Linearity and Wide Tuning
               Range Ring Voltage Controlled Oscillator},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {10--18},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_2},
  doi       = {10.1007/978-3-642-42024-5\_2},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RajahariVB13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RathoreP13,
  author    = {Akhil Rathore and
               Chetan D. Parikh},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {10 Gbps Current Mode Logic {I/O} Buffer},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {59--65},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_8},
  doi       = {10.1007/978-3-642-42024-5\_8},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RathoreP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ReniwalV13,
  author    = {Bhupendra Singh Reniwal and
               Santosh Kumar Vishvakarma},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power
               Near-Threshold {SRAM}},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {1--9},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_1},
  doi       = {10.1007/978-3-642-42024-5\_1},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ReniwalV13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RoyBGC13,
  author    = {Sudip Roy and
               Bhargab B. Bhattacharya and
               Sarmishtha Ghoshal and
               Krishnendu Chakrabarty},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using
               Digital Microfluidics},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {274--283},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_33},
  doi       = {10.1007/978-3-642-42024-5\_33},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RoyBGC13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RoyBRD13,
  author    = {Pranab Roy and
               Samadrita Bhattacharya and
               Hafizur Rahaman and
               Parthasarathi Dasgupta},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {A New Method for Route Based Synthesis and Placement in Digital Microfluidic
               Biochips},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {361--375},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_43},
  doi       = {10.1007/978-3-642-42024-5\_43},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RoyBRD13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaMKP13,
  author    = {Amit Sharma and
               Ravindra Mukhiya and
               S. Santosh Kumar and
               B. D. Pant},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Design and Simulation of Bulk Micromachined Accelerometer for Avionics
               Application},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {94--99},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_12},
  doi       = {10.1007/978-3-642-42024-5\_12},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SharmaMKP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghKD13,
  author    = {Surabhi Singh and
               Brajesh Kumar Kaushik and
               Sudeb Dasgupta},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {A Modified Gate Replacement Algorithm for Leakage Reduction Using
               Dual-T\({}_{\mbox{ox }}\)in {CMOS} {VLSI} Circuits},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {146--152},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_18},
  doi       = {10.1007/978-3-642-42024-5\_18},
  timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghKD13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghSVJ13,
  author    = {Prashant Singh and
               Pooja Srivastava and
               Ram Mohan Verma and
               Saurabh Jaiswal},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Modeling of High Frequency Out-of-Plane Single Axis {MEMS} Capacitive
               Accelerometer},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {249--256},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_30},
  doi       = {10.1007/978-3-642-42024-5\_30},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghSVJ13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SinghalDMP13,
  author    = {Vipul Singhal and
               Ayon Dey and
               Suresh Mallala and
               Somshubhra Paul},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {A Methodology for Early and Accurate Analysis of Inrush and Latency
               Tradeoffs during Power-Domain Wakeup},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {294--303},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_35},
  doi       = {10.1007/978-3-642-42024-5\_35},
  timestamp = {Tue, 03 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SinghalDMP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SrivastavaGPM13,
  author    = {Rohit Srivastava and
               Gaurav Gupta and
               Sarvesh Patankar and
               Nandini Mudgil},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Automatic Test Bench Generation and Connection in Modern Verification
               Environments: Methodology and Tool},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {284--293},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_34},
  doi       = {10.1007/978-3-642-42024-5\_34},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SrivastavaGPM13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/TuduMS13,
  author    = {Jaynarayan T. Tudu and
               Deepak Malani and
               Virendra Singh},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {Level-Accurate Peak Activity Estimation in Combinational Circuit Using
               {BILP}},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {345--352},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_41},
  doi       = {10.1007/978-3-642-42024-5\_41},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/TuduMS13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/VermaP13,
  author    = {Vivek Verma and
               Chetan D. Parikh},
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain
               Amplifier},
  booktitle = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  pages     = {19--25},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5\_3},
  doi       = {10.1007/978-3-642-42024-5\_3},
  timestamp = {Wed, 17 May 2017 10:54:37 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/VermaP13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vdat/2013,
  editor    = {Manoj Singh Gaur and
               Mark Zwolinski and
               Vijay Laxmi and
               Dharmendra Boolchandani and
               Virendra Singh and
               Adit D. Singh},
  title     = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
               Jaipur, India, July 27-30, 2013, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {382},
  publisher = {Springer},
  year      = {2013},
  url       = {https://doi.org/10.1007/978-3-642-42024-5},
  doi       = {10.1007/978-3-642-42024-5},
  isbn      = {978-3-642-42023-8},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/2013.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AbburiETA12,
  author    = {Kiran Kumar Abburi and
               Siva Subrahmanya Evani and
               Sajeev Thomas and
               Anup Aprem},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Reusable and Scalable Verification Environment for Memory Controllers},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {209--216},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_24},
  doi       = {10.1007/978-3-642-31494-0\_24},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AbburiETA12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/AlamAD12,
  author    = {Naushad Alam and
               Bulusu Anand and
               Sudeb Dasgupta},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced
               Circuit Performance},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {357--359},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_43},
  doi       = {10.1007/978-3-642-31494-0\_43},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/AlamAD12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BabuKBM12,
  author    = {Gunti Nagendra Babu and
               Brajesh Kumar Kaushik and
               Anand Bulusu and
               Manoj Kumar Majumder},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Low Complexity Encoder for Crosstalk Reduction in {RLC} Modeled Interconnects},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {40--45},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_5},
  doi       = {10.1007/978-3-642-31494-0\_5},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BabuKBM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BandyopadhyayBSM12,
  author    = {Soumyadip Bandyopadhyay and
               Kunal Banerjee and
               Dipankar Sarkar and
               Chittaranjan A. Mandal},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Translation Validation for {PRES+} Models of Parallel Behaviours via
               an {FSMD} Equivalence Checker},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {69--78},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_9},
  doi       = {10.1007/978-3-642-31494-0\_9},
  timestamp = {Sat, 04 Apr 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BandyopadhyayBSM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BurmanPCMS12,
  author    = {Sanjay Burman and
               Ayan Palchaudhuri and
               Rajat Subhra Chakraborty and
               Debdeep Mukhopadhyay and
               Pranav Singh},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Effect of Malicious Hardware Logic on Circuit Reliability},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {190--197},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_22},
  doi       = {10.1007/978-3-642-31494-0\_22},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/BurmanPCMS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChakiG12,
  author    = {Sanga Chaki and
               Chandan Giri},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Test Data Compression for NoC Based SoCs Using Binary Arithmetic Operations},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {337--342},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_38},
  doi       = {10.1007/978-3-642-31494-0\_38},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChakiG12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChatterjeeS12,
  author    = {Ayantika Chatterjee and
               Indranil Sengupta},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary
               Huff Curves},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {243--251},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_28},
  doi       = {10.1007/978-3-642-31494-0\_28},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChatterjeeS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChoudhuryP12,
  author    = {Priyanka Choudhury and
               Sambhu Nath Pradhan},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Power Modeling of Power Gated {FSM} and Its Low Power Realization
               by Simultaneous Partitioning and State Encoding Using Genetic Algorithm},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {19--29},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_3},
  doi       = {10.1007/978-3-642-31494-0\_3},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ChoudhuryP12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DaluiS12,
  author    = {Mamata Dalui and
               Biplab K. Sikdar},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {An Efficient Test Design for CMPs Cache Coherence Realizing {MESI}
               Protocol},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {89--98},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_11},
  doi       = {10.1007/978-3-642-31494-0\_11},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DaluiS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasDS12,
  author    = {Subrata Das and
               Parthasarathi Dasgupta and
               Samar Sen{-}Sarma},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Arithmetic Algorithms for Ternary Number System},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {111--120},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_13},
  doi       = {10.1007/978-3-642-31494-0\_13},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasDS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasR12,
  author    = {Debaprasad Das and
               Hafizur Rahaman},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube Interconnects},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {289--299},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_33},
  doi       = {10.1007/978-3-642-31494-0\_33},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasR12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasRR12,
  author    = {Debaprasad Das and
               Avishek Sinha Roy and
               Hafizur Rahaman},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Design of Content Addressable Memory Architecture Using Carbon Nanotube
               Field Effect Transistors},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {233--242},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_27},
  doi       = {10.1007/978-3-642-31494-0\_27},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasRR12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DasguptaSSCS12,
  author    = {Rituparna Dasgupta and
               Dipankar Saha and
               Jagannath Samanta and
               Sayan Chatterjee and
               Chandan Kumar Sarkar},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Implementation of a New Offset Generator Block for the Low-Voltage,
               Low-Power Self Biased Threshold Voltage Extractor Circuit},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {156--165},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_18},
  doi       = {10.1007/978-3-642-31494-0\_18},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DasguptaSSCS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DobriyalGDM12,
  author    = {Arun Dobriyal and
               Rahul Gonnabattula and
               Pallab Dasgupta and
               Chittaranjan A. Mandal},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Workload Driven Power Domain Partitioning},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {147--155},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_17},
  doi       = {10.1007/978-3-642-31494-0\_17},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DobriyalGDM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DrechslerW12,
  author    = {Rolf Drechsler and
               Robert Wille},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Reversible Circuits: Recent Accomplishments and Future Challenges
               for an Emerging Technology - (Invited Paper)},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {383--392},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_53},
  doi       = {10.1007/978-3-642-31494-0\_53},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/DrechslerW12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GhosalD12,
  author    = {Prasun Ghosal and
               Tuhin Subhra Das},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Routing in NoC on Diametrical 2D Mesh Architecture},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {381--382},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_52},
  doi       = {10.1007/978-3-642-31494-0\_52},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GhosalD12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GhoshTMCRM12,
  author    = {Sudip Ghosh and
               Somsubhra Talapatra and
               Debasish Mondal and
               Navonil Chatterjee and
               Hafizur Rahaman and
               Santi P. Maity},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {{VLSI} Architecture for Spatial Domain Spread Spectrum Image Watermarking
               Using Gray-Scale Watermark},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {375--376},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_49},
  doi       = {10.1007/978-3-642-31494-0\_49},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GhoshTMCRM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GhoshalKSC12,
  author    = {Bibhas Ghoshal and
               Subhadip Kundu and
               Indranil Sengupta and
               Santanu Chattopadhyay},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Particle Swarm Optimization Based {BIST} Design for Memory Cores in
               Mesh Based Network-on-Chip},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {343--349},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_39},
  doi       = {10.1007/978-3-642-31494-0\_39},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GhoshalKSC12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GovindarajSC12,
  author    = {Rekha Govindaraj and
               Indranil Sengupta and
               Santanu Chattopadhyay},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {An Efficient Technique for Longest Prefix Matching in Network Routers},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {317--326},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_36},
  doi       = {10.1007/978-3-642-31494-0\_36},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GovindarajSC12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuptaKRD12,
  author    = {Partha Sarathi Gupta and
               Sayan Kanungo and
               Hafizur Rahaman and
               Parthasarathi Dasgupta},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel
               Field Effect Transistor},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {379--380},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_51},
  doi       = {10.1007/978-3-642-31494-0\_51},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GuptaKRD12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/GuptaS12,
  author    = {Anu Gupta and
               Subhrojyoti Sarkar},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {An Efficient High Frequency and Low Power Analog Multiplier in Current
               Domain},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {1--9},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_1},
  doi       = {10.1007/978-3-642-31494-0\_1},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/GuptaS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/HalderBNB12,
  author    = {Santanu Halder and
               Debotosh Bhattacharjee and
               Mita Nasipuri and
               Dipak Kumar Basu},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {A Fast {FPGA} Based Architecture for Sobel Edge Detection},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {300--306},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_34},
  doi       = {10.1007/978-3-642-31494-0\_34},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/HalderBNB12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/HatiB12,
  author    = {Manas Kumar Hati and
               Tarun Kanti Bhattacharyya},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {A High Speed, Low Jitter and Fast Acquisition {CMOS} Phase Frequency
               Detector for Charge Pump {PLL}},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {166--171},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_19},
  doi       = {10.1007/978-3-642-31494-0\_19},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/HatiB12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JamalPMB12,
  author    = {Lafifa Jamal and
               Md. Masbaul Alam Polash and
               M. A. Mottalib and
               Hafiz Md. Hasan Babu},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {On the Compact Designs of Low Power Reversible Decoders and Sequential
               Circuits},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {281--288},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_32},
  doi       = {10.1007/978-3-642-31494-0\_32},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JamalPMB12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JayagowriG12,
  author    = {R. Jayagowri and
               K. S. Gurumurthy},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Implementation of Gating Technique with Modified Scan Flip-Flop for
               Low Power Testing of {VLSI} Chips},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {52--58},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_7},
  doi       = {10.1007/978-3-642-31494-0\_7},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JayagowriG12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/JunejaKCS12,
  author    = {Dushyant Juneja and
               Sougata Kumar Kar and
               Procheta Chatterjee and
               Siddhartha Sen},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {{SOI} {MEMS} Based Over-Sampling Accelerometer Design with {\(\Delta\)}{\(\Sigma\)}
               Output},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {121--128},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_14},
  doi       = {10.1007/978-3-642-31494-0\_14},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/JunejaKCS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KalyaniR12,
  author    = {K. Kalyani and
               S. Rajaram},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {A Novel Symbol Estimation Algorithm for {LTE} Standard},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {354--356},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_42},
  doi       = {10.1007/978-3-642-31494-0\_42},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KalyaniR12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KarSRM12,
  author    = {Bapi Kar and
               Susmita Sur{-}Kolay and
               Sridhar H. Rangarajan and
               Chittaranjan A. Mandal},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {A Faster Hierarchical Balanced Bipartitioner for {VLSI} Floorplans
               Using Monotone Staircase Cuts},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {327--336},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_37},
  doi       = {10.1007/978-3-642-31494-0\_37},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KarSRM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KaushikKKM12,
  author    = {Naveen Kaushik and
               Brajesh Kumar Kaushik and
               Davinder Kaur and
               Manoj Kumar Majumder},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Independent Gate {SRAM} Based on Asymmetric Gate to Source/Drain Overlap-Underlap
               Device FinFET},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {373--374},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_48},
  doi       = {10.1007/978-3-642-31494-0\_48},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KaushikKKM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KumarappanR12,
  author    = {Arun Kumarappan and
               P. V. Ramakrishna},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Speech Processor Design for Cochlear Implants},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {307--316},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_35},
  doi       = {10.1007/978-3-642-31494-0\_35},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KumarappanR12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KushwahV12,
  author    = {Chandrabhan Kushwah and
               Santosh Kumar Vishvakarma},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Ultra-Low Power Sub-threshold {SRAM} Cell Design to Improve Read Static
               Noise Margin},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {139--146},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_16},
  doi       = {10.1007/978-3-642-31494-0\_16},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/KushwahV12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MaityM12,
  author    = {Biswajit Maity and
               Pradip Mandal},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded
               Voltage Regulator},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {10--18},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_2},
  doi       = {10.1007/978-3-642-31494-0\_2},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MaityM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MandalCS12,
  author    = {Sudhindu Bikash Mandal and
               Amlan Chakrabarti and
               Susmita Sur{-}Kolay},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {A Synthesis Method for Quaternary Quantum Logic Circuits},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {270--280},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_31},
  doi       = {10.1007/978-3-642-31494-0\_31},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/MandalCS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MondalGDC12,
  author    = {Arpan Mondal and
               Santosh Ghosh and
               Abhijit Das and
               Dipanwita Roy Chowdhury},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Efficient {FPGA} Implementation of Montgomery Multiplier Using {DSP}
               Blocks},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {370--372},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_47},
  doi       = {10.1007/978-3-642-31494-0\_47},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MondalGDC12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MukherjeeD12,
  author    = {Atin Mukherjee and
               Anindya Sundar Dhar},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Design of a Fault-Tolerant Conditional Sum Adder},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {217--222},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_25},
  doi       = {10.1007/978-3-642-31494-0\_25},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/MukherjeeD12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/NandiSD12,
  author    = {Ashutosh Nandi and
               Ashok K. Saxena and
               Sudeb Dasgupta},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {46--51},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_6},
  doi       = {10.1007/978-3-642-31494-0\_6},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/NandiSD12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PatraCC12,
  author    = {Biswajit Patra and
               Sanatan Chattopadhyay and
               Amlan Chakrabarti},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in
               Advanced Technology Nodes},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {360--363},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_44},
  doi       = {10.1007/978-3-642-31494-0\_44},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PatraCC12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/PoddarGMSR12,
  author    = {Soumyajit Poddar and
               Prasun Ghosal and
               Priyajit Mukherjee and
               Suman Samui and
               Hafizur Rahaman},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {A Photonic Network on Chip with {CDMA} Links},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {377--378},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_50},
  doi       = {10.1007/978-3-642-31494-0\_50},
  timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/PoddarGMSR12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RahamanMJP12,
  author    = {Hafizur Rahaman and
               Jimson Mathew and
               Abusaleh M. Jabir and
               Dhiraj K. Pradhan},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {{VLSI} Architecture for Bit Parallel Systolic Multipliers for Special
               Class of {GF(2} m )Using Dual Bases},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {258--269},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_30},
  doi       = {10.1007/978-3-642-31494-0\_30},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RahamanMJP12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RanaLC12,
  author    = {Goutam Rana and
               Samir Kumar Lahiri and
               Chirasree Roy Chaudhuri},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Design Optimization of a Wide Band {MEMS} Resonator for Efficient
               Energy Harvesting},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {129--138},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_15},
  doi       = {10.1007/978-3-642-31494-0\_15},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RanaLC12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RashidA12,
  author    = {Farhana Rashid and
               Vishwani D. Agrawal},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Power Problems in {VLSI} Circuit Testing},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {393--405},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_54},
  doi       = {10.1007/978-3-642-31494-0\_54},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RashidA12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RoyM12,
  author    = {Debapriya Basu Roy and
               Debdeep Mukhopadhyay},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {An Efficient High Speed Implementation of Flexible Characteristic-2
               Multipliers on FPGAs},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {99--110},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_12},
  doi       = {10.1007/978-3-642-31494-0\_12},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RoyM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/RoyRGR12,
  author    = {Surajit Kumar Roy and
               Dona Roy and
               Chandan Giri and
               Hafizur Rahaman},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Post-bond Stack Testing for 3D Stacked {IC}},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {59--68},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_8},
  doi       = {10.1007/978-3-642-31494-0\_8},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/RoyRGR12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SahaBDB12,
  author    = {Prabir Saha and
               Arindam Banerjee and
               Anup Dandapat and
               Partha Bhattacharyya},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Design of High Speed Vedic Multiplier for Decimal Number System},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {79--88},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_10},
  doi       = {10.1007/978-3-642-31494-0\_10},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SahaBDB12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SahooA12,
  author    = {Manodipan Sahoo and
               Bharadwaj Amrutur},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Comparison of OpAmp Based and Comparator Based Switched Capacitor
               Filter},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {180--189},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_21},
  doi       = {10.1007/978-3-642-31494-0\_21},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SahooA12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SahooM12,
  author    = {Sauvagya Ranjan Sahoo and
               Kamala Kanta Mahapatra},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Design of Combinational and Sequential Circuits Using Novel Feedthrough
               Logic},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {367--369},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_46},
  doi       = {10.1007/978-3-642-31494-0\_46},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SahooM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SakareSG12,
  author    = {Mahendra Sakare and
               Mohit Singh and
               Shalabh Gupta},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {A 4 {\texttimes} 20 Gb/s 29-1 {PRBS} Generator for Testing a High-Speed
               {DAC} in 90nm {CMOS} Technology},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {252--257},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_29},
  doi       = {10.1007/978-3-642-31494-0\_29},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SakareSG12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SaravananCCSK12,
  author    = {P. Saravanan and
               P. Chandrasekar and
               Livya Chandran and
               Nikilla Sriram and
               P. Kalpana},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Design and Implementation of Efficient Vedic Multiplier Using Reversible
               Logic},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {364--366},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_45},
  doi       = {10.1007/978-3-642-31494-0\_45},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/SaravananCCSK12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SaunCA12,
  author    = {Vikram Singh Saun and
               Suman Chatterjee and
               Anand Arunachalam},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Integrated Placement and Optimization Flow for Structured and Regular
               Logic},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {352--353},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_41},
  doi       = {10.1007/978-3-642-31494-0\_41},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SaunCA12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SenDSS12,
  author    = {Bibhash Sen and
               Manojit Dutta and
               Divyam Saran and
               Biplab K. Sikdar},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {An Efficient Multiplexer in Quantum-dot Cellular Automata},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {350--351},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_40},
  doi       = {10.1007/978-3-642-31494-0\_40},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SenDSS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShayanSSF12,
  author    = {Mohammed Shayan and
               Virendra Singh and
               Adit D. Singh and
               Masahiro Fujita},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {{SEU} Tolerant Robust Latch Design},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {223--232},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_26},
  doi       = {10.1007/978-3-642-31494-0\_26},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ShayanSSF12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShresthaP12,
  author    = {Rahul Shrestha and
               Roy P. Paily},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Design and Implementation of a Linear Feedback Shift Register Interleaver
               for Turbo Decoding},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {30--39},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_4},
  doi       = {10.1007/978-3-642-31494-0\_4},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/ShresthaP12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SruthiD12,
  author    = {P. R. Sruthi and
               M. Nirmala Devi},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {A Modified Scheme for Simultaneous Reduction of Test Data Volume and
               Testing Power},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {198--208},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_23},
  doi       = {10.1007/978-3-642-31494-0\_23},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/SruthiD12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/TuduMS12,
  author    = {Jaynarayan T. Tudu and
               Deepak Malani and
               Virendra Singh},
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {{ILP} Based Approach for Input Vector Controlled {(IVC)} Toggle Maximization
               in Combinational Circuits},
  booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  pages     = {172--179},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0\_20},
  doi       = {10.1007/978-3-642-31494-0\_20},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/TuduMS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vdat/2012,
  editor    = {Hafizur Rahaman and
               Sanatan Chattopadhyay and
               Santanu Chattopadhyay},
  title     = {Progress in {VLSI} Design and Test - 16th International Symposium,
               {VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {7373},
  publisher = {Springer},
  year      = {2012},
  url       = {https://doi.org/10.1007/978-3-642-31494-0},
  doi       = {10.1007/978-3-642-31494-0},
  isbn      = {978-3-642-31493-3},
  timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/2012.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of Schloss Dagstuhl - Leibniz Center for Informatics