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@inproceedings{DBLP:conf/vlsi/AhmedAMS23,
author = {Sagheer Ahmed and
Jayesh Ambulkar and
Debabrata Mondal and
Ambika Prasad Shah},
title = {Soft Error Immune with Enhanced Critical Charge {SIC14T} {SRAM} Cell
for Avionics Applications},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321888},
doi = {10.1109/VLSI-SOC57769.2023.10321888},
timestamp = {Wed, 06 Dec 2023 13:14:06 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AhmedAMS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmerRKSSKK23,
author = {Walaa Amer and
Mariam Rakka and
Rachid Karami and
Minjun Seo and
Mazen A. R. Saghir and
Rouwaida Kanj and
Fadi J. Kurdahi},
title = {Hardware Implementation and Evaluation of an Information Processing
Factory},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321939},
doi = {10.1109/VLSI-SOC57769.2023.10321939},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AmerRKSSKK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AydumanKKMS23,
author = {Can Ayduman and
Emre Ko{\c{c}}er and
Selim Kirbiyik and
Ahmet Can Mert and
Erkay Savas},
title = {Efficient Design-Time Flexible Hardware Architecture for Accelerating
Homomorphic Encryption},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--7},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321943},
doi = {10.1109/VLSI-SOC57769.2023.10321943},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AydumanKKMS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AzizaZHDBG23,
author = {Hassen Aziza and
Cristian Zambelli and
Said Hamdioui and
Sumit Diware and
Rajendra Bishnoi and
Anteneh Gebregiorgis},
title = {On the Reliability of RRAM-Based Neural Networks},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321859},
doi = {10.1109/VLSI-SOC57769.2023.10321859},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AzizaZHDBG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BairamkulovCM23,
author = {Rassul Bairamkulov and
Alessandro Tempia Calvino and
Giovanni De Micheli},
title = {Synthesis of {SFQ} Circuits with Compound Gates},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321853},
doi = {10.1109/VLSI-SOC57769.2023.10321853},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BairamkulovCM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BelwafiAAS23,
author = {Kais Belwafi and
Hamdan Alshamsi and
Ashfaq Ahmed and
Abdulhadi Shoufan},
title = {Zero-Trust Communication between Chips},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321927},
doi = {10.1109/VLSI-SOC57769.2023.10321927},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BelwafiAAS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernardiIK23,
author = {Paolo Bernardi and
Giorgio Insinga and
Nima Kolahimahmoudi},
title = {A Novel Approach to Extract Embedded Memory Design Parameter Through
Irradiation Test},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321848},
doi = {10.1109/VLSI-SOC57769.2023.10321848},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BernardiIK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BrittonMLDBCG23,
author = {Giovani Britton and
Salvador Mir and
Estelle Lauga{-}Larroze and
Benjamin Dormieu and
Quentin Berlingard and
Mika{\"{e}}l Cass{\'{e}} and
Philippe Galy},
title = {Noise modeling using look-up tables and {DC} measurements for cryogenic
applications},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321896},
doi = {10.1109/VLSI-SOC57769.2023.10321896},
timestamp = {Thu, 07 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BrittonMLDBCG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChenKSGLI23,
author = {Hanning Chen and
Yeseong Kim and
Elaheh Sadredini and
Saransh Gupta and
Hugo Latapie and
Mohsen Imani},
title = {Sparsity Controllable Hyperdimensional Computing for Genome Sequence
Matching Acceleration},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321874},
doi = {10.1109/VLSI-SOC57769.2023.10321874},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChenKSGLI23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChenLLFLG23,
author = {Yi Chen and
Jie Lou and
Christian Lanius and
Florian Freye and
Johnson Loh and
Tobias Gemmeke},
title = {An Energy-Efficient and Area-Efficient Depthwise Separable Convolution
Accelerator with Minimal On-Chip Memory Access},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321918},
doi = {10.1109/VLSI-SOC57769.2023.10321918},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChenLLFLG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChouHJH23,
author = {Shan{-}Hui Chou and
Ting{-}Yun Hsiao and
Jing{-}Yang Jou and
Juinn{-}Dar Huang},
title = {An Evaluation and Architecture Exploration Engine for {CNN} Accelerators
through Extensive Dataflow Analysis},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321934},
doi = {10.1109/VLSI-SOC57769.2023.10321934},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChouHJH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DatsukOVW23,
author = {A. Datsuk and
P. Ostrovskyy and
F. Vater and
C. Wieden},
title = {Towards Robust Process Design Kits with a Scalable DevOps Quality
Assurance Platform},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321846},
doi = {10.1109/VLSI-SOC57769.2023.10321846},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/DatsukOVW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DebCM23,
author = {Suman Deb and
Anupam Chattopadhyay and
Avi Mendelson},
title = {A {RISC-V} SoC with Hardware Trojans: Case Study on Trojan-ing the
On-Chip Protocol Conversion},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321883},
doi = {10.1109/VLSI-SOC57769.2023.10321883},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/DebCM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EggermannRANA23,
author = {Gr{\'{e}}goire Eggermann and
Marco Rios and
Giovanni Ansaloni and
Sani R. Nassif and
David Atienza},
title = {A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse
Matrix-Vector Multiplication},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321838},
doi = {10.1109/VLSI-SOC57769.2023.10321838},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/EggermannRANA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GuptaAK23,
author = {Aishwarya Gupta and
N. S. Aswathy and
Hemangee K. Kapoor},
title = {Look before you leap: An Access-based Prudent Page Migration for Hybrid
Memories},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321920},
doi = {10.1109/VLSI-SOC57769.2023.10321920},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GuptaAK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/IbrahimAES23,
author = {Hala Ibrahim and
Haytham Azmi and
M. Watheq El{-}Kharashi and
Mona Safar},
title = {Hardware Security Analysis of Arbiters: Trojan Modeling and Formal
Verification},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321908},
doi = {10.1109/VLSI-SOC57769.2023.10321908},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/IbrahimAES23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JamilUSHR23,
author = {Shahid Jamil and
Muhammad Usman and
Muhammad Jawad Shakil and
Jafar Hussain and
Rashad Ramzan},
title = {Bi-Directional Time Domain Duplexing {(TDD)} Amplifier for 5G Applications},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321915},
doi = {10.1109/VLSI-SOC57769.2023.10321915},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JamilUSHR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JiangCT23,
author = {Jingbo Jiang and
Xizi Chen and
Chi{-}Ying Tsui},
title = {Accelerating Large Kernel Convolutions with Nested Winograd Transformation},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321932},
doi = {10.1109/VLSI-SOC57769.2023.10321932},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JiangCT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JoshiGCBTG23,
author = {Dheemanth Joshi and
Aniket Arun Gangotri and
Sai Pranay Chennamsetti and
Gautham Bolar and
Ganesan Thiagarajan and
Sanjeev Gurugopinath},
title = {A Two-Layer Connected Component Algorithm for Target Extraction Using
K-means and Morphology},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321872},
doi = {10.1109/VLSI-SOC57769.2023.10321872},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JoshiGCBTG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KarimzadehIACLF23,
author = {Foroozan Karimzadeh and
Mohsen Imani and
Bahar Asgari and
Ningyuan Cao and
Yingyan Lin and
Yan Fang},
title = {Memory-Based Computing for Energy-Efficient {AI:} Grand Challenges},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321880},
doi = {10.1109/VLSI-SOC57769.2023.10321880},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KarimzadehIACLF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KarnNE23,
author = {Rupesh Raj Karn and
Kashif Nawaz and
Ibrahim Abe M. Elfadel},
title = {Post-Quantum, Order-Preserving Encryption for the Confidential Inference
in Decision Trees: {FPGA} Design and Implementation},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321917},
doi = {10.1109/VLSI-SOC57769.2023.10321917},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KarnNE23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KhanKRSOLH23,
author = {Safiullah Khan and
Ayesha Khalid and
Ciara Rafferty and
Yasir Ali Shah and
M{\'{a}}ire O'Neill and
Wai{-}Kong Lee and
Seong Oun Hwang},
title = {Efficient, Error-Resistant {NTT} Architectures for CRYSTALS-Kyber
{FPGA} Accelerators},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321885},
doi = {10.1109/VLSI-SOC57769.2023.10321885},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KhanKRSOLH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KumarGMCA23,
author = {Shubham Kumar and
Paul R. Genssler and
Somaya Mansour and
Yogesh Singh Chauhan and
Hussam Amrouch},
title = {Frontiers in {AI} Acceleration: From Approximate Computing to FeFET
Monolithic 3D Integration},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321854},
doi = {10.1109/VLSI-SOC57769.2023.10321854},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KumarGMCA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiZCTH23,
author = {Junjie Li and
Youming Zhang and
Yunqi Cao and
Xusheng Tang and
Fengyi Huang},
title = {A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N
Frequency Synthesizer},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321911},
doi = {10.1109/VLSI-SOC57769.2023.10321911},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LiZCTH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LimKJWBCS23,
author = {Sejin Lim and
Hyunjun Kim and
Kyungbae Jang and
Siyi Wang and
Anubhab Baksi and
Anupam Chattopadhyay and
Hwajeong Seo},
title = {Optimized Quantum Circuit Implementation of Payoff Function},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321843},
doi = {10.1109/VLSI-SOC57769.2023.10321843},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LimKJWBCS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LongcharK23,
author = {Imlijungla Longchar and
Hemangee K. Kapoor},
title = {ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in
Neural Network Inference},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321889},
doi = {10.1109/VLSI-SOC57769.2023.10321889},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LongcharK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MarchandNMNBO23,
author = {C{\'{e}}dric Marchand and
Alban Nicolas and
Paul{-}Antoine Matrangolo and
David Navarro and
Alberto Bosio and
Ian O'Connor},
title = {FeFET based Logic-in-Memory design methodologies, tools and open challenges},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321901},
doi = {10.1109/VLSI-SOC57769.2023.10321901},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MarchandNMNBO23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MasoumianMWYSHT23,
author = {Shayesteh Masoumian and
Roel Maes and
Rui Wang and
Karthik Keni Yerriswamy and
Geert Jan Schrijen and
Said Hamdioui and
Mottaqiallah Taouil},
title = {Modeling and Analysis of {SRAM} {PUF} Bias Patterns in 14nm and 7nm
FinFET Technology Nodes},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321895},
doi = {10.1109/VLSI-SOC57769.2023.10321895},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MasoumianMWYSHT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MedinaHAZA23,
author = {Rafael Medina and
Darong Huang and
Giovanni Ansaloni and
Marina Zapater and
David Atienza},
title = {{REMOTE:} Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package
for Hotspot Removal},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321912},
doi = {10.1109/VLSI-SOC57769.2023.10321912},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MedinaHAZA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MerioLNEMF23,
author = {Cristiano Merio and
Xavier Lesage and
Ali Naimi and
Sylvain Engels and
Katell Morin{-}Allory and
Laurent Fesquet},
title = {Method for Data-Driven Pruning in Micropipeline Circuits},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321868},
doi = {10.1109/VLSI-SOC57769.2023.10321868},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MerioLNEMF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NoelVGCFRG23,
author = {Jean{-}Philippe No{\"{e}}l and
E. Valea and
Laurent Grenouillet and
B. Chapuis and
C. Fisher and
A. Recoquillay and
Bastien Giraud},
title = {Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and
Adaptability in Critical Embedded Systems},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321864},
doi = {10.1109/VLSI-SOC57769.2023.10321864},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NoelVGCFRG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NumanAH23,
author = {Omar Numan and
Martin Andraud and
Kari Halonen},
title = {A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based
In-Memory Computing},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321903},
doi = {10.1109/VLSI-SOC57769.2023.10321903},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NumanAH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PelkeBCSLJ23,
author = {Rebecca Pelke and
Nils Bosbach and
Jos{\'{e}} Cubero{-}Cascante and
Felix Staudigl and
Rainer Leupers and
Jan Moritz Joseph},
title = {Mapping of CNNs on multi-core RRAM-based {CIM} architectures},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321873},
doi = {10.1109/VLSI-SOC57769.2023.10321873},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PelkeBCSLJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PittalaKS23,
author = {Mouli Venkata Prakash Pittala and
Aditya Kalyani and
Nagaveni S},
title = {Reconfigurable Rectifier for {RF} Energy Harvesting System at WiFi-6
Frequency Band for 2.5 {V}},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321941},
doi = {10.1109/VLSI-SOC57769.2023.10321941},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PittalaKS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RajendranZSMRC23,
author = {Gokulnath Rajendran and
Furqan Zahoor and
Simranjeet Singh and
Farhad Merchant and
Vikas Rana and
Anupam Chattopadhyay},
title = {{PR-PUF:} {A} Reconfigurable Strong {RRAM} {PUF}},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321884},
doi = {10.1109/VLSI-SOC57769.2023.10321884},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RajendranZSMRC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ReimannWSML23,
author = {Lennart M. Reimann and
Jonathan Wiesner and
Dominik Sisejkovic and
Farhad Merchant and
Rainer Leupers},
title = {SoftFlow: Automated {HW-SW} Confidentiality Verification for Embedded
Processors},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321922},
doi = {10.1109/VLSI-SOC57769.2023.10321922},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ReimannWSML23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RiazKKPA23,
author = {Anjum Riaz and
Gaurav Kumar and
Pardeep Kumar and
Yamuna Prasad and
Satyadev Ahlawat},
title = {On Protecting {IJTAG} using an Inherently Secure {SIB}},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321938},
doi = {10.1109/VLSI-SOC57769.2023.10321938},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RiazKKPA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RutschME23,
author = {Gabriel Rutsch and
Konrad Maier and
Wolfgang Ecker},
title = {FPGA-implementation techniques to efficiently test application readiness
of mixed-signal products},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321876},
doi = {10.1109/VLSI-SOC57769.2023.10321876},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RutschME23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SarkarDM23,
author = {Esha Sarkar and
Constantine Doumanidis and
Michail Maniatakos},
title = {{TRAPDOOR:} Repurposing neural network backdoors to detect dataset
bias in machine learning-based genomic analysis},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321928},
doi = {10.1109/VLSI-SOC57769.2023.10321928},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SarkarDM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SerunjogiS23,
author = {Solomon Michael Serunjogi and
Mihai Sanduleanu},
title = {3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain {ADC} for Backplane
Interconnect},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321875},
doi = {10.1109/VLSI-SOC57769.2023.10321875},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SerunjogiS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ShakilAHSR23,
author = {Muhammad Jawad Shakil and
Uzair Ahmed and
Jafar Hussain and
Hassan Saif and
Rashad Ramzan},
title = {A Bondwire Inductor Based Flash {ADC} Assisted {DC-DC} Buck Converter},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321869},
doi = {10.1109/VLSI-SOC57769.2023.10321869},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ShakilAHSR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SiddiqiGA23,
author = {Umair F. Siddiqi and
Gary William Grewal and
Shawki Areibi},
title = {A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based
Algorithms},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321904},
doi = {10.1109/VLSI-SOC57769.2023.10321904},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SiddiqiGA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SierraGCR23,
author = {Robert Limas Sierra and
Juan{-}David Guerrero{-}Balaguera and
Josie E. Rodriguez Condia and
Matteo Sonza Reorda},
title = {Analyzing the Impact of Different Real Number Formats on the Structural
Reliability of TCUs in GPUs},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321881},
doi = {10.1109/VLSI-SOC57769.2023.10321881},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SierraGCR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SirohiS23,
author = {Ankit Sirohi and
Jawar Singh},
title = {A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon {FET} with
Intrinsic Cold Contact},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321921},
doi = {10.1109/VLSI-SOC57769.2023.10321921},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SirohiS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SoniNKM23,
author = {Deepraj Soni and
Mohammed Nabeel and
Ramesh Karri and
Michail Maniatakos},
title = {Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321936},
doi = {10.1109/VLSI-SOC57769.2023.10321936},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SoniNKM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TajiMQBA23,
author = {Hossein Taji and
Jose Miranda and
Miguel Pe{\'{o}}n Quir{\'{o}}s and
Szabolcs Bal{\'{a}}si and
David Atienza},
title = {Dynamic Scheduling for Event-Driven Embedded Industrial Applications},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321845},
doi = {10.1109/VLSI-SOC57769.2023.10321845},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/TajiMQBA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsaiCH23,
author = {Chun{-}Jen Tsai and
Chun Wei Chao and
Sheng{-}Di Hong},
title = {Integrated Dynamic Memory Manager for a {RISC-V} Processor},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321894},
doi = {10.1109/VLSI-SOC57769.2023.10321894},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/TsaiCH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WangC23,
author = {Siyi Wang and
Anupam Chattopadhyay},
title = {Reducing Depth of Quantum Adder using Ling Structure},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321948},
doi = {10.1109/VLSI-SOC57769.2023.10321948},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/WangC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YeI23,
author = {Ziyang Ye and
Makoto Ikeda},
title = {Dynamic Digital Circuit Locking {(DDCL):} {A} Shield against Static
Analysis Attacks},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321882},
doi = {10.1109/VLSI-SOC57769.2023.10321882},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/YeI23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YuS23,
author = {Yiyang Yu and
Atif Shamim},
title = {Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial
Magnetic Conductor for 6G System-on-Chip},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321899},
doi = {10.1109/VLSI-SOC57769.2023.10321899},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/YuS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZylaLWH23,
author = {Klajd Zyla and
Marco Liess and
Thomas Wild and
Andreas Herkersdorf},
title = {FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance
SmartNICs},
booktitle = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023.10321933},
doi = {10.1109/VLSI-SOC57769.2023.10321933},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZylaLWH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2023,
title = {31st {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSI-SoC57769.2023},
doi = {10.1109/VLSI-SOC57769.2023},
isbn = {979-8-3503-2599-7},
timestamp = {Wed, 06 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/2023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AccettiL22,
author = {Cecil Accetti and
Peilin Liu},
title = {Architectural Support for Functional Programming},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939644},
doi = {10.1109/VLSI-SOC54400.2022.9939644},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AccettiL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AknesilD22,
author = {Can Aknesil and
Elena Dubrova},
title = {Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose
Computers},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939649},
doi = {10.1109/VLSI-SOC54400.2022.9939649},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AknesilD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AlmeidaGBM22,
author = {Sheiny Fabre Almeida and
Jos{\'{e}} Lu{\'{\i}}s G{\"{u}}ntzel and
Laleh Behjat and
Cristina Meinhardt},
title = {Routability-Driven Detailed Placement Using Reinforcement Learning},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939602},
doi = {10.1109/VLSI-SOC54400.2022.9939602},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AlmeidaGBM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ArrassiGHH22,
author = {Asmae El Arrassi and
Anteneh Gebregiorgis and
Anass El Haddadi and
Said Hamdioui},
title = {Energy-Efficient {SNN} Implementation Using RRAM-Based Computation
In-Memory {(CIM)}},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939654},
doi = {10.1109/VLSI-SOC54400.2022.9939654},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ArrassiGHH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Asokan22,
author = {Anu Asokan},
title = {A Signal-Integrity Aware {ATPG} Flow to Generate High-Quality Patterns
for Testing System-on-Chip Designs},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939635},
doi = {10.1109/VLSI-SOC54400.2022.9939635},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Asokan22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AwaisP22,
author = {Muhammad Awais and
Marco Platzner},
title = {Automated Framework for Fast Synthesis of Approximate Hardware Accelerators},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939606},
doi = {10.1109/VLSI-SOC54400.2022.9939606},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AwaisP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BhatAR22,
author = {Ashwin Bhat and
Adou Sangbone Assoa and
Arijit Raychowdhury},
title = {Gradient Backpropagation based Feature Attribution to Enable Explainable-AI
on the Edge},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939601},
doi = {10.1109/VLSI-SOC54400.2022.9939601},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BhatAR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BliasLSBS22,
author = {Nikolaos Blias and
Iordanis Lilitsis and
Stavros Simoglou and
Evangelos Bakas and
Christos P. Sotiriou},
title = {Investigation on Performance, Power, Area Trade-Offs using Deterministic
and Monte-Carlo Process Variation Aware Synthesis Flows},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939595},
doi = {10.1109/VLSI-SOC54400.2022.9939595},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BliasLSBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BohnenstiehlSAB22,
author = {Brent Bohnenstiehl and
Aaron Stillmaker and
Timothy Andreas and
Bevan M. Baas},
title = {A Low-Overhead Method for the Accurate Estimation of the Maximum Operating
Clock Frequency},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--5},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939598},
doi = {10.1109/VLSI-SOC54400.2022.9939598},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BohnenstiehlSAB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BosbachJLJ22,
author = {Nils Bosbach and
Jan Moritz Joseph and
Rainer Leupers and
Lukas J{\"{u}}nger},
title = {{NISTT:} {A} Non-Intrusive SystemC-TLM 2.0 Tracing Tool},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939578},
doi = {10.1109/VLSI-SOC54400.2022.9939578},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BosbachJLJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BuenoESC22,
author = {C. del R{\'{\i}}o Bueno and
U. Esteban Eraso and
Carlos S{\'{a}}nchez{-}Azqueta and
Santiago Celma},
title = {A 18-27 GHz Programmable Gain Amplifier in 65-nm {CMOS} technology},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939645},
doi = {10.1109/VLSI-SOC54400.2022.9939645},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BuenoESC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CayoVR22,
author = {Jose Cayo and
Ioannis Vourkas and
Antonio Rubio},
title = {A Circuit-Level {SPICE} Modeling Strategy for the Simulation of Behavioral
Variability in ReRAM},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939587},
doi = {10.1109/VLSI-SOC54400.2022.9939587},
timestamp = {Thu, 06 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CayoVR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChatzivangelisV22,
author = {Nikolaos Chatzivangelis and
Dimitris Valiantzas and
Christos P. Sotiriou and
Iordanis Lilitsis},
title = {Simulation-Based Maximum Coverage Hazard Detection and Elimination
Analysis, Supporting Combinational Logic Loops},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939579},
doi = {10.1109/VLSI-SOC54400.2022.9939579},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChatzivangelisV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChenSB22,
author = {Renjie Chen and
Aaron Stillmaker and
Bevan M. Baas},
title = {Architecture and 28 nm {CMOS} Design of a 1886 MBin/sec Context-Adaptive
Binary Arithmetic Coder {(CABAC)} Encoder},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939655},
doi = {10.1109/VLSI-SOC54400.2022.9939655},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChenSB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChuvalasV22,
author = {Christopher Chuvalas and
Ranga Vemuri},
title = {FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting
High Bandwidth Memory},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939631},
doi = {10.1109/VLSI-SOC54400.2022.9939631},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChuvalasV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DattaFSYSD22,
author = {Kamalika Datta and
Saman Fr{\"{o}}hlich and
Saeideh Shirinzadeh and
Dev Narayan Yadav and
Indranil Sengupta and
Rolf Drechsler},
title = {Unlocking High Resolution Arithmetic Operations within Memristive
Crossbars for Error Tolerant Applications},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939573},
doi = {10.1109/VLSI-SOC54400.2022.9939573},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DattaFSYSD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DattaKYMLWTLLSA22,
author = {Gourav Datta and
Souvik Kundu and
Zihan Yin and
Joe Mathai and
Zeyu Liu and
Zixu Wang and
Mulin Tian and
Shunlin Lu and
Ravi Teja Lakkireddy and
Andrew G. Schmidt and
Wael Abd{-}Almageed and
Ajey P. Jacob and
Akhilesh R. Jaiswal and
Peter A. Beerel},
title = {P\({}^{\mbox{2}}\)M-DeTrack: Processing-in-Pixel-in-Memory for Energy-efficient
and Real-Time Multi-Object Detection and Tracking},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939582},
doi = {10.1109/VLSI-SOC54400.2022.9939582},
timestamp = {Tue, 05 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DattaKYMLWTLLSA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DrechslerM22,
author = {Rolf Drechsler and
Alireza Mahzoon},
title = {Preserving Design Hierarchy Information for Polynomial Formal Verification},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--7},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939650},
doi = {10.1109/VLSI-SOC54400.2022.9939650},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DrechslerM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EfstathiouAT22,
author = {Constantinos Efstathiou and
Laura Agalioti and
Yiorgos Tsiatouhas},
title = {Efficient Dynamic Logic Magnitude Comparators},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--5},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939570},
doi = {10.1109/VLSI-SOC54400.2022.9939570},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/EfstathiouAT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/El-ArabyFFJ22,
author = {Nahla A. El{-}Araby and
David Frismuth and
Nilson Neves Filho and
Axel Jantsch},
title = {Run Time Power and Accuracy Management with Approximate Circuits},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939639},
doi = {10.1109/VLSI-SOC54400.2022.9939639},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/El-ArabyFFJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/El-KadyFHP22,
author = {Alexander El{-}Kady and
Apostolos P. Fournaris and
Evangelos Haleplidis and
Vassilis Paliouras},
title = {High-Level Synthesis design approach for Number-Theoretic Multiplier},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939657},
doi = {10.1109/VLSI-SOC54400.2022.9939657},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/El-KadyFHP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EmeretlisTAV22,
author = {Andreas Emeretlis and
George Theodoridis and
Panayiotis Alefragis and
Nikos S. Voros},
title = {A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous
Multi-core Platforms},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939643},
doi = {10.1109/VLSI-SOC54400.2022.9939643},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/EmeretlisTAV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ErasoSAC22,
author = {U. Esteban Eraso and
Carlos S{\'{a}}nchez{-}Azqueta and
Concepci{\'{o}}n Aldea and
Santiago Celma},
title = {A {CMOS} 4-bit Digitally Programmable Phase Shifter for the K-band},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939594},
doi = {10.1109/VLSI-SOC54400.2022.9939594},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ErasoSAC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EslaminiaB22,
author = {Milad Eslaminia and
S{\'{e}}bastien Le Beux},
title = {Toward Large Scale All-Optical Spiking Neural Networks},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939647},
doi = {10.1109/VLSI-SOC54400.2022.9939647},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/EslaminiaB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EsmaeiliMAG22,
author = {P. Esmaeili and
Timothy Martin and
Shawki Areibi and
Gary Gr{\'{e}}wal},
title = {Guiding {FPGA} Detailed Placement via Reinforcement Learning},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939580},
doi = {10.1109/VLSI-SOC54400.2022.9939580},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/EsmaeiliMAG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FalisTP22,
author = {Konstantinos Falis and
Andreas Tsiougkos and
Vasilis F. Pavlidis},
title = {Practical Day-Ahead Power Prediction of Solar Energy-Harvesting for
IoT Systems},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939607},
doi = {10.1109/VLSI-SOC54400.2022.9939607},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FalisTP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FariasNBS22,
author = {Johannes W. Farias and
Diego V. Cirilo do Nascimento and
Tiago Barros and
Samuel Xavier de Souza},
title = {Speculative guardband: exploiting critical-delay variations across
cached instructions},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939597},
doi = {10.1109/VLSI-SOC54400.2022.9939597},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FariasNBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Fernandez-Aragon22,
author = {J. Fern{\'{a}}ndez{-}Arag{\'{o}}n and
Guillermo D{\'{\i}}ez{-}Se{\~{n}}orans and
Miguel Garcia{-}Bosque and
Santiago Celma},
title = {Design and characterisation of a Physically Unclonable Function on
{FPGA} using second-order compensated measurement},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939593},
doi = {10.1109/VLSI-SOC54400.2022.9939593},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Fernandez-Aragon22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FernandezV22,
author = {Carlos Fernandez and
Ioannis Vourkas},
title = {On the Design and Development of a ReRAM-based Computational Memory
Prototype},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939612},
doi = {10.1109/VLSI-SOC54400.2022.9939612},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FernandezV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FernandezV22a,
author = {Carlos Fernandez and
Ioannis Vourkas},
title = {Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational
ReRAM},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939627},
doi = {10.1109/VLSI-SOC54400.2022.9939627},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FernandezV22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FlamisKK22,
author = {Georgios Flamis and
Stavros Kalapothas and
Paris Kitsos},
title = {FPGA-SoC Deployment of Complex Deep Neural Network for Magnitude and
Phase Computations in Denoising of Speech Signal},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--5},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939632},
doi = {10.1109/VLSI-SOC54400.2022.9939632},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FlamisKK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FuscoHMA22,
author = {Alexander Fusco and
Md Sahil Hassan and
Joshua Mack and
Ali Akoglu},
title = {A Hardware-based {HEFT} Scheduler Implementation for Dynamic Workloads
on Heterogeneous SoCs},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939623},
doi = {10.1109/VLSI-SOC54400.2022.9939623},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FuscoHMA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GavaRO22,
author = {Jonas Gava and
Ricardo Reis and
Luciano Ost},
title = {Investigation of Hybrid Soft Error Mitigation Techniques for Applications
running on Resource-constrained devices},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939658},
doi = {10.1109/VLSI-SOC54400.2022.9939658},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GavaRO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GebregiorgisSDB22,
author = {Anteneh Gebregiorgis and
Abhairaj Singh and
Sumit Diware and
Rajendra Bishnoi and
Said Hamdioui},
title = {Dealing with Non-Idealities in Memristor Based Computation-In-Memory
Designs},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939618},
doi = {10.1109/VLSI-SOC54400.2022.9939618},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GebregiorgisSDB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GeorgiouK22,
author = {Nikolaos Georgiou and
Panayiotis Kolios},
title = {Accurate real-time {UAV} flight-mode classification},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939568},
doi = {10.1109/VLSI-SOC54400.2022.9939568},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GeorgiouK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GerlinKBDSKE22,
author = {Nicolas Gerlin and
Endri Kaja and
Monideep Bora and
Keerthikumara Devarajegowda and
Dominik Stoffel and
Wolfgang Kunz and
Wolfgang Ecker},
title = {Design of a Tightly-Coupled {RISC-V} Physical Memory Protection Unit
for Online Error Detection},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939622},
doi = {10.1109/VLSI-SOC54400.2022.9939622},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GerlinKBDSKE22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GerminianiP22,
author = {Samuele Germiniani and
Graziano Pravadelli},
title = {Exploiting clustering and decision-tree algorithms to mine {LTL} assertions
containing non-boolean expressions},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939640},
doi = {10.1109/VLSI-SOC54400.2022.9939640},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GerminianiP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GkoutisKK22,
author = {Panagiotis Gkoutis and
Georgios Konidas and
Grigorios Kalivas},
title = {30 GHz Front-End with Adaptively Biased {PA} and Current Steering
{LNA} for Phased Array Systems},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939604},
doi = {10.1109/VLSI-SOC54400.2022.9939604},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GkoutisKK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GlukhovLMBZOPWI22,
author = {Artem Glukhov and
Nicola Lepri and
Valerio Milo and
Andrea Baroni and
Cristian Zambelli and
Piero Olivo and
Eduardo P{\'{e}}rez and
Christian Wenger and
Daniele Ielmini},
title = {End-to-end modeling of variability-aware neural networks based on
resistive-switching memory arrays},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--5},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939653},
doi = {10.1109/VLSI-SOC54400.2022.9939653},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GlukhovLMBZOPWI22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HongekarGGA22,
author = {Rupali Hongekar and
Ankita Gupta and
Jayakrishna Guddeti and
Meghashyam Ashwathnarayan},
title = {Enabling Automotive Electrification on Heterogeneous Automotive Microcontroller
using Virtual System Modelling},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--5},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939633},
doi = {10.1109/VLSI-SOC54400.2022.9939633},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HongekarGGA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JiangLBLHLW22,
author = {Lieqiu Jiang and
Zepeng Li and
Chenpeng Bao and
Genggeng Liu and
Xing Huang and
Wen{-}Hao Liu and
Ting{-}Chi Wang},
title = {{LA-SVR:} {A} High-Performance Layer Assignment Algorithm with Slew
Violations Reduction},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939586},
doi = {10.1109/VLSI-SOC54400.2022.9939586},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JiangLBLHLW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JingYZLHLW22,
author = {Yidan Jing and
Liliang Yang and
Zhen Zhuang and
Genggeng Liu and
Xing Huang and
Wen{-}Hao Liu and
Ting{-}Chi Wang},
title = {{SPTA:} {A} Scalable Parallel ILP-Based Track Assignment Algorithm
with Two-Stage Partition},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939624},
doi = {10.1109/VLSI-SOC54400.2022.9939624},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JingYZLHLW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KajaGBRDSKE22,
author = {Endri Kaja and
Nicolas Gerlin and
Monideep Bora and
Gabriel Rutsch and
Keerthikumara Devarajegowda and
Dominik Stoffel and
Wolfgang Kunz and
Wolfgang Ecker},
title = {Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939615},
doi = {10.1109/VLSI-SOC54400.2022.9939615},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KajaGBRDSKE22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KarimzadehR22,
author = {Foroozan Karimzadeh and
Arijit Raychowdhury},
title = {Towards Energy Efficient {DNN} accelerator via Sparsified Gradual
Knowledge Distillation},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939619},
doi = {10.1109/VLSI-SOC54400.2022.9939619},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KarimzadehR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KarimzadehR22a,
author = {Foroozan Karimzadeh and
Arijit Raychowdhury},
title = {Towards CIM-friendly and Energy-Efficient {DNN} Accelerator via Bit-level
Sparsity},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939651},
doi = {10.1109/VLSI-SOC54400.2022.9939651},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KarimzadehR22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KarnE22,
author = {Rupesh Raj Karn and
Ibrahim Abe M. Elfadel},
title = {Confidential Inference in Decision Trees: {FPGA} Design and Implementation},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939567},
doi = {10.1109/VLSI-SOC54400.2022.9939567},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KarnE22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KatsanosA22,
author = {Konstantinos D. Katsanos and
George C. Alexandropoulos},
title = {Secrecy Spectral Efficiency Optimization in RIS-Enabled {MIMO} Communication
Systems},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939609},
doi = {10.1109/VLSI-SOC54400.2022.9939609},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KatsanosA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Kavun22,
author = {Elif Bilge Kavun},
title = {A Power Reduction Technique Based on Linear Transformations for Block
Ciphers},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939628},
doi = {10.1109/VLSI-SOC54400.2022.9939628},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Kavun22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KefalasT22,
author = {Nikolaos Kefalas and
George Theodoridis},
title = {An {FPGA} implementation of the {VESA} Display Stream Compression
decoder},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939648},
doi = {10.1109/VLSI-SOC54400.2022.9939648},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KefalasT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KeyserGG22,
author = {Michael Keyser and
Roman Gauchi and
Pierre{-}Emmanuel Gaillardon},
title = {An Energy-Efficient Three-Independent-Gate {FET} Cell Library for
Low-Power Edge Computing},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939636},
doi = {10.1109/VLSI-SOC54400.2022.9939636},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KeyserGG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KhanGKJN22,
author = {Mohammad Humam Khan and
Ruchika Gupta and
Vedika J. Kulkarni and
John Jose and
Sukumar Nandi},
title = {Hardware Trojan Mitigation for Securing On-chip Networks from Dead
Flit Attacks},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939569},
doi = {10.1109/VLSI-SOC54400.2022.9939569},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KhanGKJN22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KoliogeorgiMXS22,
author = {Konstantina Koliogeorgi and
Dimitris Mylonakis and
Sotirios Xydis and
Dimitrios Soudris},
title = {High Level Synthesis Acceleration of Change Detection in Multi-Temporal
High Resolution Sentinel-2 Satellite Images},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939617},
doi = {10.1109/VLSI-SOC54400.2022.9939617},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KoliogeorgiMXS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KottarasSPIPPS22,
author = {Georgios Kottaras and
Theodoros Sarris and
Athanasios M. Psomoulis and
Ilias Ioakeimidis and
Angelos Papathanasiou and
David Pitchford and
Ingmar Sandberg},
title = {A low-power, radiation-hardened Single Event Effect rate detection
System on a Chip for Real Time Monitoring of Single Event Effects
on Low Earth Orbit satellites},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939638},
doi = {10.1109/VLSI-SOC54400.2022.9939638},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KottarasSPIPPS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KuknerKEG22,
author = {Halil K{\"{u}}kner and
G{\"{o}}khan Kaplayan and
Ahmet Efe and
Mehmet Ali G{\"{u}}lden},
title = {{RISC-V} Processor Trace Encoder with Multiple Instructions Retirement
Support},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939596},
doi = {10.1109/VLSI-SOC54400.2022.9939596},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KuknerKEG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KumarCTGCA22,
author = {Shubham Kumar and
Swetaki Chatterjee and
Simon Thomann and
Paul R. Genssler and
Yogesh Singh Chauhan and
Hussam Amrouch},
title = {Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional
Computing},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939626},
doi = {10.1109/VLSI-SOC54400.2022.9939626},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KumarCTGCA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KumarRPA22,
author = {Gaurav Kumar and
Anjum Riaz and
Yamuna Prasad and
Satyadev Ahlawat},
title = {Power Analysis Attack on Locking {SIB} based {IJTAG} Achitecture},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939634},
doi = {10.1109/VLSI-SOC54400.2022.9939634},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KumarRPA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KumarSJ22,
author = {Yogesh Kumar and
S. Sivakumar and
John Jose},
title = {{ENDURA} : Enhancing Durability of Multi Level Cell {STT-RAM} based
Non Volatile Memory Last Level Caches},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939583},
doi = {10.1109/VLSI-SOC54400.2022.9939583},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KumarSJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Laubeuf22,
author = {Nathan Laubeuf},
title = {Analog Compute in Memory and Breaking Digital Number Representations},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939611},
doi = {10.1109/VLSI-SOC54400.2022.9939611},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Laubeuf22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeonLSVB22,
author = {Vasileios Leon and
George Lentaris and
Dimitrios Soudris and
Simon Vellas and
Mathieu Bernou},
title = {Towards Employing {FPGA} and {ASIP} Acceleration to Enable Onboard
{AI/ML} in Space Applications},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939566},
doi = {10.1109/VLSI-SOC54400.2022.9939566},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LeonLSVB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeonPLBMBRS22,
author = {Vasileios Leon and
Elissaios{-}Alexios Papatheofanous and
George Lentaris and
Charalampos Bezaitis and
Nikolaos Mastorakis and
Georgios Bampilis and
Dionysios I. Reisis and
Dimitrios Soudris},
title = {Combining Fault Tolerance Techniques and {COTS} SoC Accelerators for
Payload Processing in Space},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939621},
doi = {10.1109/VLSI-SOC54400.2022.9939621},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LeonPLBMBRS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeonPS22,
author = {Vasileios Leon and
Kiamal Z. Pekmestzi and
Dimitrios Soudris},
title = {Systematic Embedded Development and Implementation Techniques on Intel
Myriad VPUs},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939592},
doi = {10.1109/VLSI-SOC54400.2022.9939592},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LeonPS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Levantino22,
author = {Salvatore Levantino},
title = {Frequency Synthesizers for 5G Applications},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939577},
doi = {10.1109/VLSI-SOC54400.2022.9939577},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Levantino22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LongcharDK22,
author = {Imlijungla Longchar and
Palash Das and
Hemangee K. Kapoor},
title = {ZaLoBI: Zero avoiding Load Balanced Inference accelerator},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939591},
doi = {10.1109/VLSI-SOC54400.2022.9939591},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LongcharDK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LopacinskiHPMGK22,
author = {Lukasz Lopacinski and
Alireza Hasani and
Goran Panic and
Nebojsa Maletic and
Jes{\'{u}}s Guti{\'{e}}rrez and
Milos Krstic and
Eckhard Grass},
title = {High-Speed {SC} Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm
{CMOS}},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939603},
doi = {10.1109/VLSI-SOC54400.2022.9939603},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LopacinskiHPMGK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MadhvarajMB22,
author = {Manasa Madhvaraj and
Salvador Mir and
Manuel J. Barrag{\'{a}}n},
title = {A self-referenced on-chip jitter {BIST} with sub-picosecond resolution
in 28 nm {FD-SOI} technology},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939620},
doi = {10.1109/VLSI-SOC54400.2022.9939620},
timestamp = {Wed, 28 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MadhvarajMB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MalikBKJS22,
author = {Raiyyan Malik and
Shubham Baunthiyal and
Puneet Kumar and
Srinath J and
Sneh Saurabh},
title = {A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational
Equivalence Checking},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939646},
doi = {10.1109/VLSI-SOC54400.2022.9939646},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MalikBKJS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ManourasP22,
author = {Vasileios Manouras and
Ioannis Papananos},
title = {A Wideband High-Gain Power Amplifier Operating in the {D} Band},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--5},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939613},
doi = {10.1109/VLSI-SOC54400.2022.9939613},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ManourasP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Marques-GarciaA22,
author = {Jorge Marqu{\'{e}}s{-}Garc{\'{\i}}a and
Alberto Arcusa{-}Puente and
Antonio D. Mart{\'{\i}}nez{-}P{\'{e}}rez and
Francisco Aznar},
title = {Modeling frequency response of gm-boosted inductorless Common-Gate
{LNA}},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939625},
doi = {10.1109/VLSI-SOC54400.2022.9939625},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Marques-GarciaA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MerkLK22,
author = {Jonathan Merk and
Changhai Lin and
Matthias Kamuf},
title = {Assessing {IMD} of a Direct-to-RF Platform},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939605},
doi = {10.1109/VLSI-SOC54400.2022.9939605},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MerkLK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MichailidisNS22,
author = {Anastasios Michailidis and
Thomas Noulis and
Kostas Siozios},
title = {Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939575},
doi = {10.1109/VLSI-SOC54400.2022.9939575},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MichailidisNS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuzaffarE22,
author = {Shahzad Muzaffar and
Ibrahim Abe M. Elfadel},
title = {Logic Locking of Finite-State Machines Using Transition Obfuscation},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939610},
doi = {10.1109/VLSI-SOC54400.2022.9939610},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MuzaffarE22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PapatheofanousT22,
author = {Elissaios{-}Alexios Papatheofanous and
Ph. Tziolos and
V. Kalekis and
Tzouma Amrou and
George E. Konstantoulakis and
Georgios Venitourakis and
Dionysios I. Reisis},
title = {SoC {FPGA} Acceleration for Semantic Segmentation of Clouds in Satellite
Images},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939585},
doi = {10.1109/VLSI-SOC54400.2022.9939585},
timestamp = {Thu, 04 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PapatheofanousT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PaschalisCTTK22,
author = {Antonis M. Paschalis and
Panagiotis Chatziantoniou and
Dimitris Theodoropoulos and
Antonis Tsigkanos and
Nektarios Kranitis},
title = {High-Performance Hardware Accelerators for Next Generation On-Board
Data Processing},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939616},
doi = {10.1109/VLSI-SOC54400.2022.9939616},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PaschalisCTTK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ReveilMMDMKLLPO22,
author = {Lucas R{\'{e}}veil and
Chhandak Mukherjee and
Cristell Maneux and
Marina Deng and
Fran{\c{c}}ois Marc and
Abhishek Kumar and
Aur{\'{e}}lie Lecestre and
Guilhem Larrieu and
Arnaud Poittevin and
Ian O'Connor and
Oskar Baumgartner and
David Pirker},
title = {Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less
Transistors},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939576},
doi = {10.1109/VLSI-SOC54400.2022.9939576},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ReveilMMDMKLLPO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SahaBS22,
author = {Kritanta Saha and
Pritha Banerjee and
Susmita Sur{-}Kolay},
title = {Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939588},
doi = {10.1109/VLSI-SOC54400.2022.9939588},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SahaBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SamarasTH22,
author = {Dimitrios Samaras and
Andreas Tsimpos and
Alkis A. Hatzopoulos},
title = {A novel wide frequency range 65nm {CMOS} {VCO}},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939581},
doi = {10.1109/VLSI-SOC54400.2022.9939581},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SamarasTH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SarmanSKNJJ22,
author = {Akshay Sarman and
Alwin Shaju and
Rose George Kunthara and
K. Neethu and
Rekha K. James and
John Jose},
title = {RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939590},
doi = {10.1109/VLSI-SOC54400.2022.9939590},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SarmanSKNJJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SilvaGM22,
author = {Pedro Aquino Silva and
Mateus Grellert and
Cristina Meinhardt},
title = {Exploring Approximate Comparator Circuits on Power Efficient Design
of Decision Trees},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939599},
doi = {10.1109/VLSI-SOC54400.2022.9939599},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SilvaGM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SilvaGM22a,
author = {Pedro Aquino Silva and
Mateus Grellert and
Cristina Meinhardt},
title = {Approximation Workflow for Energy-Efficient Comparators in Decision
Tree Applications},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939637},
doi = {10.1109/VLSI-SOC54400.2022.9939637},
timestamp = {Mon, 25 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SilvaGM22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SinghBPLCM22,
author = {Simranjeet Singh and
Srinivasu Bodapati and
Sachin B. Patkar and
Rainer Leupers and
Anupam Chattopadhyay and
Farhad Merchant},
title = {{PA-PUF:} {A} Novel Priority Arbiter {PUF}},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939642},
doi = {10.1109/VLSI-SOC54400.2022.9939642},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SinghBPLCM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SorensenBSK22,
author = {Stian Gerlach S{\o}rensen and
Christian Bartsch and
Dominik Stoffel and
Wolfgang Kunz},
title = {Generation of Formal {CPU} Profiles for Embedded Systems},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939572},
doi = {10.1109/VLSI-SOC54400.2022.9939572},
timestamp = {Wed, 31 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SorensenBSK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SorianoNPPB22,
author = {Theo Soriano and
David Novo and
Guillaume Prenat and
Gregory di Pendina and
Pascal Benoit},
title = {MemCork: Exploration of Hybrid Memory Architectures for Intermittent
Computing at the Edge},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939630},
doi = {10.1109/VLSI-SOC54400.2022.9939630},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SorianoNPPB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SudarshanSKWW22,
author = {Chirag Sudarshan and
Taha Soliman and
Thomas K{\"{a}}mpfe and
Christian Weis and
Norbert Wehn},
title = {FeFET versus {DRAM} based {PIM} Architectures: {A} Comparative Study},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939629},
doi = {10.1109/VLSI-SOC54400.2022.9939629},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SudarshanSKWW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsaiL22,
author = {Chun{-}Jen Tsai and
Yi{-}De Lee},
title = {Embedded {TCP/IP} Controller for a {RISC-V} SoC},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939600},
doi = {10.1109/VLSI-SOC54400.2022.9939600},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/TsaiL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsantikidouS22,
author = {Kyriaki Tsantikidou and
Nicolas Sklavos},
title = {Flexible Security and Privacy, System Architecture for IoT, in Healthcare},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939659},
doi = {10.1109/VLSI-SOC54400.2022.9939659},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TsantikidouS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VasileiadisMLNS22,
author = {Nikolaos Vasileiadis and
Alexandros Mavropoulis and
Panagiotis Loukas and
Pascal Normand and
Georgios Ch. Sirakoulis and
Panagiotis Dimitrakis},
title = {Substrate Effect on Low-frequency Noise of synaptic {RRAM} devices},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--5},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939652},
doi = {10.1109/VLSI-SOC54400.2022.9939652},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/VasileiadisMLNS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VergosGPANSS22,
author = {George S. Vergos and
Vasiliki Gogolou and
C. Panagiotopoulou and
A. Avgoustidis and
Thomas Noulis and
Kostas Siozios and
Stilianos Siskos},
title = {Machine Learning based Power Converter Large Signal Simulation for
Energy Harvesting Applications},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--5},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939641},
doi = {10.1109/VLSI-SOC54400.2022.9939641},
timestamp = {Sun, 06 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/VergosGPANSS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VlachosB22,
author = {Evangelos Vlachos and
Kostas Blekos},
title = {Quantum Computing-Assisted Channel Estimation for Massive {MIMO} mmWave
Systems},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939656},
doi = {10.1109/VLSI-SOC54400.2022.9939656},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/VlachosB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZahediSCSWH22,
author = {Mahdi Zahedi and
Taha Shahroodi and
Geert Custers and
Abhairaj Singh and
Stephan Wong and
Said Hamdioui},
title = {System Design for Computation-in-Memory: From Primitive to Complex
Functions},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939571},
doi = {10.1109/VLSI-SOC54400.2022.9939571},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZahediSCSWH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZanandreaM22,
author = {Vinicius Zanandrea and
Cristina Meinhardt},
title = {Exploring Approximate Computing Approaches to Design Power-efficient
Multipliers},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939584},
doi = {10.1109/VLSI-SOC54400.2022.9939584},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZanandreaM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2021socs,
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-16818-5},
doi = {10.1007/978-3-031-16818-5},
isbn = {978-3-031-16817-8},
timestamp = {Tue, 29 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/2021socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2022,
title = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022},
doi = {10.1109/VLSI-SOC54400.2022},
isbn = {978-1-6654-9005-4},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/2022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Ahmed21,
author = {Qazi Arbab Ahmed},
title = {Hardware Trojans in Reconfigurable Computing},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606974},
doi = {10.1109/VLSI-SOC53125.2021.9606974},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Ahmed21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmrouchDGHP21,
author = {Hussam Amrouch and
Nan Du and
Anteneh Gebregiorgis and
Said Hamdioui and
Ilia Polian},
title = {Towards Reliable In-Memory Computing: From Emerging Devices to Post-von-Neumann
Architectures},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606966},
doi = {10.1109/VLSI-SOC53125.2021.9606966},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AmrouchDGHP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AzimiSPS21,
author = {Sarah Azimi and
Corrado De Sio and
Andrea Portaluri and
Luca Sterpone},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {Design and Mitigation Techniques of Radiation Induced SEEs on Open-Source
Embedded Static RAMs},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {135--153},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_7},
doi = {10.1007/978-3-031-16818-5\_7},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AzimiSPS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AzimiSS21,
author = {Sarah Azimi and
Corrado De Sio and
Luca Sterpone},
title = {On the Evaluation of SEEs on Open-Source Embedded Static RAMs},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606985},
doi = {10.1109/VLSI-SOC53125.2021.9606985},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AzimiSS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Baksi21,
author = {Anubhab Baksi},
title = {Classical and Physical Security of Symmetric Key Cryptographic Algorithms},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606988},
doi = {10.1109/VLSI-SOC53125.2021.9606988},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Baksi21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BalajiS21,
author = {Akshay Balaji and
Sneh Saurabh},
title = {Reducing Breakdown Voltage in a Bipolar Impact Ionization {MOSFET}
{(BI-MOS)} using Gate-Source Underlap},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606982},
doi = {10.1109/VLSI-SOC53125.2021.9606982},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BalajiS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BhattacharjeeRR21,
author = {Abhiroop Bhattacharjee and
Shubham Rai and
Ansh Rupani and
Michael Raitza and
Akash Kumar},
title = {Metastability with Emerging Reconfigurable Transistors: Exploiting
Ambipolarity for Throughput},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607015},
doi = {10.1109/VLSI-SOC53125.2021.9607015},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BhattacharjeeRR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BossuetB21,
author = {Lilian Bossuet and
El Mehdi Benhani},
title = {Security Assessment of Heterogeneous SoC-FPGA: On the Practicality
of Cache Timing Attacks},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607012},
doi = {10.1109/VLSI-SOC53125.2021.9607012},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BossuetB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BragaglioDGP21,
author = {Moreno Bragaglio and
Nicola Donatelli and
Samuele Germiniani and
Graziano Pravadelli},
title = {System-level bug explanation through program slicing and instruction
clusterization},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607008},
doi = {10.1109/VLSI-SOC53125.2021.9607008},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BragaglioDGP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BragaglioGP21,
author = {Moreno Bragaglio and
Samuele Germiniani and
Graziano Pravadelli},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {Exploiting Program Slicing and Instruction Clusterization to Identify
the Cause of Faulty Temporal Behaviours at System Level},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {71--92},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_4},
doi = {10.1007/978-3-031-16818-5\_4},
timestamp = {Tue, 22 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BragaglioGP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CaoZGG21,
author = {Zhaoyang Cao and
Tan{-}Tan Zhang and
Yuan Gao and
Wang Ling Goh},
title = {Design of Fully Differential Energy-Efficient Inverter-Based Low-Noise
Amplifier for Ultrasound Imaging},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606991},
doi = {10.1109/VLSI-SOC53125.2021.9606991},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CaoZGG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChatterjeeMH21,
author = {Durba Chatterjee and
Debdeep Mukhopadhyay and
Aritra Hazra},
title = {Formal Analysis of Physically Unclonable Functions},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607011},
doi = {10.1109/VLSI-SOC53125.2021.9607011},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChatterjeeMH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChongGOND21,
author = {Yi Sheng Chong and
Wang Ling Goh and
Yew Soon Ong and
Vishnu P. Nambiar and
Anh Tuan Do},
title = {Efficient Implementation of Activation Functions for {LSTM} accelerators},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606971},
doi = {10.1109/VLSI-SOC53125.2021.9606971},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChongGOND21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CollemanVMTV21,
author = {Steven Colleman and
Thomas Verelst and
Linyan Mei and
Tinne Tuytelaars and
Marian Verhelst},
title = {Processor Architecture Optimization for Spatially Dynamic Neural Networks},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607013},
doi = {10.1109/VLSI-SOC53125.2021.9607013},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CollemanVMTV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CopettiGB21,
author = {Thiago Santos Copetti and
Tobias Gemmeke and
Let{\'{\i}}cia Maria Veiras Bolzani},
title = {Validating a {DFT} Strategy's Detection Capability regarding Emerging
Faults in RRAMs},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606993},
doi = {10.1109/VLSI-SOC53125.2021.9606993},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CopettiGB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CopettiGP21,
author = {Thiago Santos Copetti and
Tobias Gemmeke and
Let{\'{\i}}cia Maria Bolzani P{\"{o}}hls},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {A DfT Strategy for Detecting Emerging Faults in RRAMs},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {93--111},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_5},
doi = {10.1007/978-3-031-16818-5\_5},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CopettiGP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CouriolCGG21,
author = {Matthieu Couriol and
Patsy Cadareanu and
Edouard Giacomin and
Pierre{-}Emmanuel Gaillardon},
title = {A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope
Field-Effect Transistors},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606989},
doi = {10.1109/VLSI-SOC53125.2021.9606989},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CouriolCGG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CouriolCGG21a,
author = {Matthieu Couriol and
Patsy Cadareanu and
Edouard Giacomin and
Pierre{-}Emmanuel Gaillardon},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect
Transistors in Ultra-Low Power Analog Design},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {205--224},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_10},
doi = {10.1007/978-3-031-16818-5\_10},
timestamp = {Tue, 22 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CouriolCGG21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CouriolGG21,
author = {Matthieu Couriol and
Edouard Giacomin and
Pierre{-}Emmanuel Gaillardon},
title = {A 12-pA Resolution Sigma Delta {ADC} Topology for Chemiresistive Sensor-Based
Applications},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606996},
doi = {10.1109/VLSI-SOC53125.2021.9606996},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CouriolGG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DagheroBXBCMPP21,
author = {Francesco Daghero and
Alessio Burrello and
Chen Xie and
Luca Benini and
Andrea Calimera and
Enrico Macii and
Massimo Poncino and
Daniele Jahier Pagliari},
title = {Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606986},
doi = {10.1109/VLSI-SOC53125.2021.9606986},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DagheroBXBCMPP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DagheroBXBCMPP21a,
author = {Francesco Daghero and
Alessio Burrello and
Chen Xie and
Luca Benini and
Andrea Calimera and
Enrico Macii and
Massimo Poncino and
Daniele Jahier Pagliari},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {Low-Overhead Early-Stopping Policies for Efficient Random Forests
Inference on Microcontrollers},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {25--47},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_2},
doi = {10.1007/978-3-031-16818-5\_2},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DagheroBXBCMPP21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DecouduMF21,
author = {Yoan Decoudu and
Katell Morin{-}Allory and
Laurent Fesquet},
title = {A High-Level Design Flow for Locally Body Biased Asynchronous Circuits},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606977},
doi = {10.1109/VLSI-SOC53125.2021.9606977},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/DecouduMF21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DeepsitaDM21,
author = {S. Skandha Deepsita and
Kuchipudi Divya and
Sk. Noor Mahammad},
title = {Energy Efficient and Multiplierless Approximate Integer {DCT} Implementation
for {HEVC}},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606995},
doi = {10.1109/VLSI-SOC53125.2021.9606995},
timestamp = {Sat, 19 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/DeepsitaDM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/El-KadyFTHP21,
author = {Alexander El{-}Kady and
Apostolos P. Fournaris and
Thanasis Tsakoulis and
Evangelos Haleplidis and
Vassilis Paliouras},
title = {High-Level Synthesis design approach for Number-Theoretic Transform
Implementations},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607003},
doi = {10.1109/VLSI-SOC53125.2021.9607003},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/El-KadyFTHP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GasquezGBMMWP21,
author = {J. Gasquez and
Bastien Giraud and
P. Boivin and
Y. Moustapha{-}Rabault and
Vincenzo Della Marca and
Jean{-}Pierre Walder and
Jean{-}Michel Portal},
title = {A Self-referenced and regulated sensing solution for {PCM} with {OTS}
selector},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606969},
doi = {10.1109/VLSI-SOC53125.2021.9606969},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GasquezGBMMWP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GasquezGBMMWP21a,
author = {J. Gasquez and
Bastien Giraud and
P. Boivin and
Y. Moustapha{-}Rabault and
Vincenzo Della Marca and
Jean{-}Michel Walder and
Jean{-}Michel Portal},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {A Regulated Sensing Solution Based on a Self-reference Principle for
{PCM} + {OTS} Memory Array},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {225--243},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_11},
doi = {10.1007/978-3-031-16818-5\_11},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GasquezGBMMWP21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GuptaC21,
author = {Naina Gupta and
Anupam Chattopadhyay},
title = {In Quest for Fast and Secure SoC},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607004},
doi = {10.1109/VLSI-SOC53125.2021.9607004},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GuptaC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HanRWLPLDE21,
author = {Zhao Han and
Gabriel Rutsch and
Deyan Wang and
Bowen Li and
Sebastian Siegfried Prebeck and
Daniela Sanchez Lopera and
Keerthikumara Devarajegowda and
Wolfgang Ecker},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {Transformative Hardware Design Following the Model-Driven Architecture
Vision},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {49--70},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_3},
doi = {10.1007/978-3-031-16818-5\_3},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HanRWLPLDE21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HanWRLPLDE21,
author = {Zhao Han and
Deyan Wang and
Gabriel Rutsch and
Bowen Li and
Sebastian Siegfried Prebeck and
Daniela Sanchez Lopera and
Keerthikumara Devarajegowda and
Wolfgang Ecker},
title = {Aspect-Oriented Design Automation with Model Transformation},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606984},
doi = {10.1109/VLSI-SOC53125.2021.9606984},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HanWRLPLDE21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LaiLBAJ21,
author = {Xinhui Lai and
Thomas Lange and
Aneesh Balakrishnan and
Dan Alexandrescu and
Maksim Jenihhin},
title = {On Antagonism Between Side-Channel Security and Soft-Error Reliability
in {BNN} Inference Engines},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606981},
doi = {10.1109/VLSI-SOC53125.2021.9606981},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LaiLBAJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiFLL21,
author = {Hongwei Li and
Xuemei Fan and
Qiang Li and
Hao Liu},
title = {An Efficient Light-weight Configurable Approximate Adder Design},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607010},
doi = {10.1109/VLSI-SOC53125.2021.9607010},
timestamp = {Mon, 06 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LiFLL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MacielGRR21,
author = {Vitor Hugo F. Maciel and
Germano Girondi and
Elias de Almeida Ramos and
Ricardo Reis},
title = {Exploring a New Tool for Automatic Layout Synthesis for {FDSOI} 28
nm},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607005},
doi = {10.1109/VLSI-SOC53125.2021.9607005},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MacielGRR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MiteloudiCBM21,
author = {Konstantina Miteloudi and
Lukasz Chmielewski and
Lejla Batina and
Nele Mentens},
title = {Evaluating the {ROCKY} Countermeasure for Side-Channel Leakage},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606973},
doi = {10.1109/VLSI-SOC53125.2021.9606973},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MiteloudiCBM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MocerinoRPCM21,
author = {Luca Mocerino and
Roberto Giorgio Rizzo and
Valentino Peluso and
Andrea Calimera and
Enrico Macii},
title = {AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606980},
doi = {10.1109/VLSI-SOC53125.2021.9606980},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MocerinoRPCM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MocerinoRPCM21a,
author = {Luca Mocerino and
Roberto Giorgio Rizzo and
Valentino Peluso and
Andrea Calimera and
Enrico Macii},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy
for Reliable Embedded ConvNets},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {1--23},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_1},
doi = {10.1007/978-3-031-16818-5\_1},
timestamp = {Tue, 22 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MocerinoRPCM21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NousiasPMLM21,
author = {Stavros Nousias and
Erion{-}Vasilis M. Pikoulis and
Christos Mavrokefalidis and
Aris S. Lalos and
Konstantinos Moustakas},
title = {Accelerating 3D scene analysis for autonomous driving on embedded
{AI} computing platforms},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606990},
doi = {10.1109/VLSI-SOC53125.2021.9606990},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NousiasPMLM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PetrellisCZMKVA21,
author = {Nikos Petrellis and
Panagiotis Christakos and
Stavros Zogas and
Panagiotis Mousouliotis and
Georgios Keramidas and
Nikolaos S. Voros and
Christos P. Antonopoulos},
title = {Challenges Towards Hardware Acceleration of the Deformable Shape Tracking
Application},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606999},
doi = {10.1109/VLSI-SOC53125.2021.9606999},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PetrellisCZMKVA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RaiGBRRTM021,
author = {Shubham Rai and
Nishant Gupta and
Abhiroop Bhattacharjee and
Ansh Rupani and
Michael Raitza and
Jens Trommer and
Thomas Mikolajick and
Akash Kumar},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {{END-TRUE:} Emerging Nanotechnology-Based Double-Throughput True Random
Number Generator},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {175--203},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_9},
doi = {10.1007/978-3-031-16818-5\_9},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RaiGBRRTM021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RaoOKE21,
author = {Vikas Rao and
Haden Ondricek and
Priyank Kalla and
Florian Enescu},
title = {Algebraic Techniques for Rectification of Finite Field Circuits},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606976},
doi = {10.1109/VLSI-SOC53125.2021.9606976},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RaoOKE21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RaviCB21,
author = {Prasanna Ravi and
Anupam Chattopadhyay and
Shivam Bhasin},
title = {Practical Side-Channel and Fault Attacks on Lattice-Based Cryptography},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607000},
doi = {10.1109/VLSI-SOC53125.2021.9607000},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RaviCB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RieseHGD21,
author = {Frank Riese and
Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Metamorphic Testing for Processor Verification: {A} {RISC-V} Case
Study at the Instruction Level},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606997},
doi = {10.1109/VLSI-SOC53125.2021.9606997},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RieseHGD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RouxMBBCBGCL21,
author = {Julie Roux and
Katell Morin{-}Allory and
Vincent Beroulle and
Lilian Bossuet and
Fr{\'{e}}d{\'{e}}ric C{\'{e}}zilly and
Fr{\'{e}}d{\'{e}}ric Berthoz and
Gilles Gen{\'{e}}vrier and
Fran{\c{c}}ois Cerisier and
R{\'{e}}gis Leveugle},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {{FMEA} on Critical Systems: {A} Cross-Layer Approach Based on High-Level
Models},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {113--133},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_6},
doi = {10.1007/978-3-031-16818-5\_6},
timestamp = {Tue, 22 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RouxMBBCBGCL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RouxMBLBCBGC21,
author = {Julie Roux and
Katell Morin{-}Allory and
Vincent Beroulle and
R{\'{e}}gis Leveugle and
Lilian Bossuet and
Fr{\'{e}}d{\'{e}}ric C{\'{e}}zilly and
Fr{\'{e}}d{\'{e}}ric Berthoz and
Gilles Gen{\'{e}}vrier and
Fran{\c{c}}ois Cerisier},
title = {Cross-layer Approach to Assess {FMEA} on Critical Systems and Evaluate
High-Level Model Realism},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607001},
doi = {10.1109/VLSI-SOC53125.2021.9607001},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RouxMBLBCBGC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SahaMC21,
author = {Akashdeep Saha and
Debdeep Mukhopadhyay and
Rajat Subhra Chakraborty},
title = {Design and Analysis of Logic Locking Techniques},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606975},
doi = {10.1109/VLSI-SOC53125.2021.9606975},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SahaMC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SahooK21,
author = {Siva Satyendra Sahoo and
Akash Kumar},
title = {CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy
Optimization in Heterogeneous Embedded Systems},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606983},
doi = {10.1109/VLSI-SOC53125.2021.9606983},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SahooK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SahooK21a,
author = {Siva Satyendra Sahoo and
Akash Kumar},
title = {Using Monte Carlo Tree Search for {EDA} - {A} Case-study with Designing
Cross-layer Reliability for Heterogeneous Embedded Systems},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606987},
doi = {10.1109/VLSI-SOC53125.2021.9606987},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SahooK21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SepulvedaWSCO21,
author = {Johanna Sep{\'{u}}lveda and
Dominik Winkler and
Daniel Mauricio Sep{\'{u}}lveda and
Mario Cupelli and
Radek Olexa},
title = {Post-Quantum Cryptography in MPSoC Environments},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606978},
doi = {10.1109/VLSI-SOC53125.2021.9606978},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SepulvedaWSCO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SisejkovicL21,
author = {Dominik Sisejkovic and
Rainer Leupers},
title = {Trustworthy Hardware Design with Logic Locking},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606998},
doi = {10.1109/VLSI-SOC53125.2021.9606998},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SisejkovicL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SisejkovicRMML21,
author = {Dominik Sisejkovic and
Lennart M. Reimann and
Elmira Moussavi and
Farhad Merchant and
Rainer Leupers},
title = {Logic Locking at the Frontiers of Machine Learning: {A} Survey on
Developments and Opportunities},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606979},
doi = {10.1109/VLSI-SOC53125.2021.9606979},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SisejkovicRMML21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/StapfJBS21,
author = {Emmanuel Stapf and
Patrick Jauernig and
Ferdinand Brasser and
Ahmad{-}Reza Sadeghi},
title = {In Hardware We Trust? From {TPM} to Enclave Computing on {RISC-V}},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606968},
doi = {10.1109/VLSI-SOC53125.2021.9606968},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/StapfJBS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ValenteRB21,
author = {Luca Valente and
Davide Rossi and
Luca Benini},
title = {Hardware-In-The Loop Emulation for Agile Co-Design of Parallel Ultra-Low
Power IoT Processors},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607006},
doi = {10.1109/VLSI-SOC53125.2021.9607006},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ValenteRB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WongCD21,
author = {Ming Ming Wong and
Lu Chen and
Anh Tuan Do},
title = {A 25 {TOPS/W} High Power Efficiency Deterministic and Split Stochastic
{MAC} {(SC-MAC)} Design},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606972},
doi = {10.1109/VLSI-SOC53125.2021.9606972},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/WongCD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WongCD21a,
author = {Ming Ming Wong and
Lu Chen and
Anh Tuan Do},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {An Improved Deterministic Stochastic {MAC} {(SC-MAC)} for High Power
Efficiency Design},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {245--266},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_12},
doi = {10.1007/978-3-031-16818-5\_12},
timestamp = {Tue, 22 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/WongCD21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhaoG21,
author = {Jianming Zhao and
Yuan Gao},
title = {A 13.56 MHz Active Rectifier with {PMOS} {AC-DC} Interface for Wireless
Powered Medical Implants},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606992},
doi = {10.1109/VLSI-SOC53125.2021.9606992},
timestamp = {Thu, 17 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZhaoG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZolfaghariB21,
author = {Parya Zolfaghari and
S{\'{e}}bastien Le Beux},
title = {A Reconfigurable Nanophotonic Architecture based on Phase Change Material},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606967},
doi = {10.1109/VLSI-SOC53125.2021.9606967},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZolfaghariB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZolfaghariB21a,
author = {Parya Zolfaghari and
S{\'{e}}bastien Le Beux},
editor = {Victor Grimblatt and
Chip{-}Hong Chang and
Ricardo Reis and
Anupam Chattopadhyay and
Andrea Calimera},
title = {Design of a Reconfigurable Optical Computing Architecture Using Phase
Change Material},
booktitle = {VLSI-SoC: Technology Advancement on SoC Design - 29th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {661},
pages = {155--174},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-16818-5\_8},
doi = {10.1007/978-3-031-16818-5\_8},
timestamp = {Tue, 22 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZolfaghariB21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2020socs,
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-030-81641-4},
doi = {10.1007/978-3-030-81641-4},
isbn = {978-3-030-81640-7},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2020socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2021,
title = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021},
doi = {10.1109/VLSI-SOC53125.2021},
isbn = {978-1-6654-2614-5},
timestamp = {Fri, 19 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/2021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AghighiFT20,
author = {Amin Aghighi and
Behrouz Farhang{-}Boroujeny and
Armin Tajalli},
title = {Energy and Area Efficient Mixed-Mode {MCMC} {MIMO} Detector},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {105--110},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344098},
doi = {10.1109/VLSI-SOC46417.2020.9344098},
timestamp = {Wed, 17 Feb 2021 12:09:06 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AghighiFT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AghighiFT20a,
author = {Amin Aghighi and
Behrouz Farhang{-}Boroujeny and
Armin Tajalli},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {Mixed-Mode Signal Processing for Implementing {MCMC} {MIMO} Detector},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {21--37},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_2},
doi = {10.1007/978-3-030-81641-4\_2},
timestamp = {Wed, 28 Jul 2021 16:16:21 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AghighiFT20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AghighiTT20,
author = {Amin Aghighi and
Massood Tabib{-}Azar and
Armin Tajalli},
title = {An {ULP} Self-Supplied Brain Interface Circuit},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {100--104},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344092},
doi = {10.1109/VLSI-SOC46417.2020.9344092},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AghighiTT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AghighiTT20a,
author = {Amin Aghighi and
Armin Tajalli and
Mohammad Taherzadeh{-}Sani},
title = {A Low-Power 10 to 15 Gb/s Common-Gate {CTLE} Based on Optimized Active
Inductors},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {171--175},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344076},
doi = {10.1109/VLSI-SOC46417.2020.9344076},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AghighiTT20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AjayiKCFKSGCSBD20,
author = {Tutu Ajayi and
Sumanth Kamineni and
Yaswanth K. Cherivirala and
Morteza Fayazi and
Kyumin Kwon and
Mehdi Saligane and
Shourya Gupta and
Chien{-}Hen Chen and
Dennis Sylvester and
David T. Blaauw and
Ronald G. Dreslinski and
Benton H. Calhoun and
David D. Wentzloff},
title = {An Open-source Framework for Autonomous SoC Design with Analog Block
Generation},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {141--146},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344104},
doi = {10.1109/VLSI-SOC46417.2020.9344104},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AjayiKCFKSGCSBD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AjayiKFCKGDLCSS20,
author = {Tutu Ajayi and
Sumanth Kamineni and
Morteza Fayazi and
Yaswanth K. Cherivirala and
Kyumin Kwon and
Shourya Gupta and
Wenbo Duan and
Jeongsup Lee and
Chien{-}Hen Chen and
Mehdi Saligane and
Dennis Sylvester and
David T. Blaauw and
Ronald Dreslinski Jr. and
Benton H. Calhoun and
David D. Wentzloff},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog
and Mixed-Signal Circuits Generation},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {65--85},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_4},
doi = {10.1007/978-3-030-81641-4\_4},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AjayiKFCKGDLCSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AnandakumarSH20,
author = {N. Nalla Anandakumar and
Somitra Kumar Sanadhya and
Mohammad S. Hashmi},
title = {Design, Implementation and Analysis of Efficient Hardware-Based Security
Primitives},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {198--199},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344097},
doi = {10.1109/VLSI-SOC46417.2020.9344097},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AnandakumarSH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Carloni20,
author = {Luca P. Carloni},
title = {Scalable Open-Source System-on-Chip Design: (Invited Talk - Extended
Abstract)},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {7--9},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344077},
doi = {10.1109/VLSI-SOC46417.2020.9344077},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Carloni20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChenZCT20,
author = {Yongnan Chen and
Yanhan Zeng and
Junkai Chen and
Hong{-}Zhou Tan},
title = {{PT} controlled buck converter with adaptive {PCCM} using charge monitoring
and {NMOS} current sensing},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {176--180},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344074},
doi = {10.1109/VLSI-SOC46417.2020.9344074},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChenZCT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChowdhuryRM20,
author = {Siddhartha Chowdhury and
Debapriya Basu Roy and
Debdeep Mukhopadhyay},
title = {A Minimalistic Perspective on Koblitz Curve Scalar Multiplication
for {FPGA} Platforms},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {70--75},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344069},
doi = {10.1109/VLSI-SOC46417.2020.9344069},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChowdhuryRM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CondiaR20,
author = {Josie E. Rodriguez Condia and
Matteo Sonza Reorda},
title = {Testing the Divergence Stack Memory on GPGPUs: {A} Modular in-Field
Test Strategy},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {153--158},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344088},
doi = {10.1109/VLSI-SOC46417.2020.9344088},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CondiaR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CondiaR20a,
author = {Josie Esteban Rodriguez Condia and
Matteo Sonza Reorda},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {Modular Functional Testing: Targeting the Small Embedded Memories
in GPUs},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {205--233},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_10},
doi = {10.1007/978-3-030-81641-4\_10},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CondiaR20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CordovaCDRLNP20,
author = {David Cordova and
Wim Cops and
Yann Deval and
Francois Rivet and
Herv{\'{e}} Lapuyade and
Nicolas Nodenot and
Yohan Piccin},
title = {A 0.8V 875 MS/s 7b low-power {SAR} {ADC} for ADC-Based Wireline Receivers
in 22nm {FDSOI}},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {52--57},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344084},
doi = {10.1109/VLSI-SOC46417.2020.9344084},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CordovaCDRLNP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CordovaCDRLNP20a,
author = {David Cordova and
Wim Cops and
Yann Deval and
Fran{\c{c}}ois Rivet and
Herv{\'{e}} Lapuyade and
Nicolas Nodenot and
Yohan Piccin},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm
{FDSOI}},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {1--19},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_1},
doi = {10.1007/978-3-030-81641-4\_1},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CordovaCDRLNP20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CraftonSMKLR20,
author = {Brian Crafton and
Samuel Spetalnick and
Gauthaman Murali and
Tushar Krishna and
Sung Kyu Lim and
Arijit Raychowdhury},
title = {Breaking Barriers: Maximizing Array Utilization for Compute in-Memory
Fabrics},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {123--128},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344086},
doi = {10.1109/VLSI-SOC46417.2020.9344086},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CraftonSMKLR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CraftonSMKLR20a,
author = {Brian Crafton and
Samuel Spetalnick and
Gauthaman Murali and
Tushar Krishna and
Sung Kyu Lim and
Arijit Raychowdhury},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {Statistical Array Allocation and Partitioning for Compute In-Memory
Fabrics},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {323--341},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_15},
doi = {10.1007/978-3-030-81641-4\_15},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CraftonSMKLR20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DaiTLHRR20,
author = {Shanshan Dai and
Caleb R. Tulloss and
Xiaoyu Lian and
Kangping Hu and
Sherief Reda and
Jacob K. Rosenstein},
title = {Temperature and Supply Voltage Monitoring with Current-mode Relaxation
Oscillators},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {192--197},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344099},
doi = {10.1109/VLSI-SOC46417.2020.9344099},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/DaiTLHRR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DaiTLHRR20a,
author = {Shanshan Dai and
Caleb R. Tulloss and
Xiaoyu Lian and
Kangping Hu and
Sherief Reda and
Jacob K. Rosenstein},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {Low Power Current-Mode Relaxation Oscillators for Temperature and
Supply Voltage Monitoring},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {39--63},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_3},
doi = {10.1007/978-3-030-81641-4\_3},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DaiTLHRR20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EberleinP20,
author = {Matthias Eberlein and
Harald Pretl},
title = {Subthreshold-Hybrid Solutions for Thermal Sensor and Reference Circuits
in Advanced {CMOS}},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {186--191},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344105},
doi = {10.1109/VLSI-SOC46417.2020.9344105},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/EberleinP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EliahuHRK20,
author = {Adi Eliahu and
Rotem Ben Hur and
Ronny Ronen and
Shahar Kvatinsky},
title = {abstractPIM: Bridging the Gap Between Processing-In-Memory Technology
and Instruction Set Architecture},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {28--33},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344103},
doi = {10.1109/VLSI-SOC46417.2020.9344103},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/EliahuHRK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EliahuHRK20a,
author = {Adi Eliahu and
Rotem Ben Hur and
Ronny Ronen and
Shahar Kvatinsky},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {abstractPIM: {A} Technology Backward-Compatible Compilation Flow for
Processing-In-Memory},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {343--361},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_16},
doi = {10.1007/978-3-030-81641-4\_16},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/EliahuHRK20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GangulySG20,
author = {Samiran Ganguly and
Nikhil Shukla and
Avik W. Ghosh},
title = {Ultra-Compact, Scalable, Energy-Efficient {\textdollar}VO{\_}\{2\}{\textdollar}
Insulator-Metal-Transition Oxide Based Spiking Neurons for Liquid
State Machines},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {147--152},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344078},
doi = {10.1109/VLSI-SOC46417.2020.9344078},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GangulySG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Gava0O20,
author = {Jonas Gava and
Ricardo Reis and
Luciano Ost},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {{RAT:} {A} Lightweight Architecture Independent System-Level Soft
Error Mitigation Technique},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {235--253},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_11},
doi = {10.1007/978-3-030-81641-4\_11},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Gava0O20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GavaRO20,
author = {Jonas Gava and
Ricardo Augusto da Luz Reis and
Luciano Ost},
title = {{RAT:} {A} Lightweight System-level Soft Error Mitigation Technique},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {165--170},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344080},
doi = {10.1109/VLSI-SOC46417.2020.9344080},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GavaRO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GerminianiBP20,
author = {Samuele Germiniani and
Moreno Bragaglio and
Graziano Pravadelli},
title = {{MIST:} monitor generation from informal specifications for firmware
verification},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {111--116},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344072},
doi = {10.1109/VLSI-SOC46417.2020.9344072},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GerminianiBP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GerminianiBP20a,
author = {Samuele Germiniani and
Moreno Bragaglio and
Graziano Pravadelli},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {From Informal Specifications to an {ABV} Framework for Industrial
Firmware Verification},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {179--204},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_9},
doi = {10.1007/978-3-030-81641-4\_9},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GerminianiBP20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GiacominBRCG20,
author = {Edouard Giacomin and
J{\"{u}}rgen B{\"{o}}mmels and
Julien Ryckaert and
Francky Catthoor and
Pierre{-}Emmanuel Gaillardon},
title = {Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric
Process Flow},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {34--39},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344089},
doi = {10.1109/VLSI-SOC46417.2020.9344089},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GiacominBRCG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GiacominBRCG20a,
author = {Edouard Giacomin and
J{\"{u}}rgen B{\"{o}}mmels and
Julien Ryckaert and
Francky Catthoor and
Pierre{-}Emmanuel Gaillardon},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic
Designs},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {279--300},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_13},
doi = {10.1007/978-3-030-81641-4\_13},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GiacominBRCG20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HuHBCF20,
author = {Xuan Hu and
Naimul Hassan and
Wesley H. Brigner and
Maverick Chauwin and
Joseph S. Friedman},
title = {Device Modeling and Circuit Design for Scalable Beyond-CMOS Computing},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {210--211},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344091},
doi = {10.1109/VLSI-SOC46417.2020.9344091},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HuHBCF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HuYNN20,
author = {Yinghua Hu and
Kaixin Yang and
Shahin Nazarian and
Pierluigi Nuzzo},
title = {SANSCrypt: {A} Sporadic-Authentication-Based Sequential Logic Encryption
Scheme},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {129--134},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344079},
doi = {10.1109/VLSI-SOC46417.2020.9344079},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HuYNN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HuYNN20a,
author = {Yinghua Hu and
Kaixin Yang and
Shahin Nazarian and
Pierluigi Nuzzo},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {255--278},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_12},
doi = {10.1007/978-3-030-81641-4\_12},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HuYNN20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Kahng20,
author = {Andrew B. Kahng},
title = {Open-Source {EDA:} If We Build It, Who Will Come?},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344073},
doi = {10.1109/VLSI-SOC46417.2020.9344073},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Kahng20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KarimzadehR20,
author = {Foroozan Karimzadeh and
Arijit Raychowdhury},
title = {Memory and Energy Efficient Method Toward Sparse Neural Network Using
{LFSR} Indexing},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {206--207},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344090},
doi = {10.1109/VLSI-SOC46417.2020.9344090},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KarimzadehR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LaiJSGMP20,
author = {Xinhui Lai and
Maksim Jenihhin and
Georgios N. Selimis and
Sven Goossens and
Roel Maes and
Kolin Paul},
title = {Early {RTL} Analysis for {SCA} Vulnerability in Fuzzy Extractors of
Memory-Based {PUF} Enabled Devices},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {16--21},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344071},
doi = {10.1109/VLSI-SOC46417.2020.9344071},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LaiJSGMP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeleFTR20,
author = {Ashwin Sanjay Lele and
Yan Fang and
Justin Ting and
Arijit Raychowdhury},
title = {Online Reward-Based Training of Spiking Central Pattern Generator
for Hexapod Locomotion},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {208--209},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344100},
doi = {10.1109/VLSI-SOC46417.2020.9344100},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LeleFTR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LianRR20,
author = {Xiaoyu Lian and
Sherief Reda and
Jacob K. Rosenstein},
title = {Simultaneous Estimation of Temperature and Voltage from Digital Delay
Diversity},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {40--45},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344107},
doi = {10.1109/VLSI-SOC46417.2020.9344107},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LianRR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MiyasakaF20,
author = {Yukio Miyasaka and
Masahiro Fujita},
title = {SAT-Based Data-Flow Mapping Onto Array Processor},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {22--27},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344093},
doi = {10.1109/VLSI-SOC46417.2020.9344093},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MiyasakaF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MiyasakaFMW20,
author = {Yukio Miyasaka and
Masahiro Fujita and
Alan Mishchenko and
John Wawrzynek},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable
Arrays},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {113--131},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_6},
doi = {10.1007/978-3-030-81641-4\_6},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MiyasakaFMW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MoraitisDN20,
author = {Michail Moraitis and
Elena Dubrova and
Kalle Ngo},
title = {Breaking {ACORN} at Bitstream Level},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {117--122},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344082},
doi = {10.1109/VLSI-SOC46417.2020.9344082},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MoraitisDN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MoraitisSTK20,
author = {S. Moraitis and
D. Seitanidis and
George Theodoridis and
Odysseas G. Koufopavlou},
title = {Exploring the {FPGA} Implementations of the LBlock, Piccolo, Twine,
and Klein Ciphers},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {46--51},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344108},
doi = {10.1109/VLSI-SOC46417.2020.9344108},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MoraitisSTK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MorrisHGRYIAR20,
author = {Justin Morris and
Yilun Hao and
Saransh Gupta and
Ranganathan Ramkumar and
Jeffrey Yu and
Mohsen Imani and
Baris Aksanli and
Tajana Rosing},
title = {Multi-label {HD} Classification in 3D Flash},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {10--15},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344070},
doi = {10.1109/VLSI-SOC46417.2020.9344070},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MorrisHGRYIAR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MukherjeeDMMPOB20,
author = {Chhandak Mukherjee and
Marina Deng and
Fran{\c{c}}ois Marc and
Cristell Maneux and
Arnaud Poittevin and
Ian O'Connor and
S{\'{e}}bastien Le Beux and
C{\'{e}}dric Marchand and
Abhishek Kumar and
Aur{\'{e}}lie Lecestre and
Guilhem Larrieu},
title = {3D Logic Cells Design and Results Based on Vertical {NWFET} Technology
Including Tied Compact Model},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {76--81},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344094},
doi = {10.1109/VLSI-SOC46417.2020.9344094},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MukherjeeDMMPOB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PeledHRK20,
author = {Natan Peled and
Rotem Ben Hur and
Ronny Ronen and
Shahar Kvatinsky},
title = {{X-MAGIC:} Enhancing {PIM} Using Input Overwriting Capabilities},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {64--69},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344095},
doi = {10.1109/VLSI-SOC46417.2020.9344095},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PeledHRK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PelusoMC20,
author = {Valentino Peluso and
Enrico Macii and
Andrea Calimera},
title = {Optimization Tools for ConvNets on the Edge},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {204--205},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344075},
doi = {10.1109/VLSI-SOC46417.2020.9344075},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PelusoMC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PoittevinMOMLDB20,
author = {Arnaud Poittevin and
Chhandak Mukherjee and
Ian O'Connor and
Cristell Maneux and
Guilhem Larrieu and
Marina Deng and
S{\'{e}}bastien Le Beux and
Fran{\c{c}}ois Marc and
Aur{\'{e}}lie Lecestre and
C{\'{e}}dric Marchand and
Abhishek Kumar},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {3D Logic Cells Design and Results Based on Vertical {NWFET} Technology
Including Tied Compact Model},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {301--321},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_14},
doi = {10.1007/978-3-030-81641-4\_14},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PoittevinMOMLDB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RawatMS20,
author = {Mayank Rawat and
Sujit Kumar Muduli and
Pramod Subramanyan},
title = {Mining Hyperproperties from Behavioral Traces},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {88--93},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344106},
doi = {10.1109/VLSI-SOC46417.2020.9344106},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RawatMS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SadhukhanM20,
author = {Rajat Sadhukhan and
Debdeep Mukhopadhyay},
title = {Design Automation for Side Channel Resistant Lightweight Cryptography},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {202--203},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344085},
doi = {10.1109/VLSI-SOC46417.2020.9344085},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SadhukhanM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SahPIK20,
author = {Love Kumar Sah and
Srivarsha Polnati and
Sheikh Ariful Islam and
Srinivas Katkoori},
title = {Basic Block Encoding Based Run-time {CFI} Check for Embedded Software},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {135--140},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344102},
doi = {10.1109/VLSI-SOC46417.2020.9344102},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SahPIK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SaligramKBR20,
author = {Rakshith Saligram and
Ankit Kaul and
Muhannad S. Bakir and
Arijit Raychowdhury},
title = {A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet
Communication in 2.5D Integration},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {159--164},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344081},
doi = {10.1109/VLSI-SOC46417.2020.9344081},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SaligramKBR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SaligramKBR20a,
author = {Rakshith Saligram and
Ankit Kaul and
Muhannad S. Bakir and
Arijit Raychowdhury},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {149--178},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_8},
doi = {10.1007/978-3-030-81641-4\_8},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SaligramKBR20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SharmaKS20,
author = {Tannu Sharma and
Sumanth Kolluru and
Kenneth S. Stevens},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {Learning Based Timing Closure on Relative Timed Design},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {133--148},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_7},
doi = {10.1007/978-3-030-81641-4\_7},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SharmaKS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SharmaS20,
author = {Tannu Sharma and
Kenneth S. Stevens},
title = {Automatic Timing Closure for Relative Timed Designs},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {82--87},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344096},
doi = {10.1109/VLSI-SOC46417.2020.9344096},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SharmaS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SimonLZA20,
author = {William Andrew Simon and
Alexandre Levisse and
Marina Zapater and
David Atienza},
title = {A Hybrid Cache {HW/SW} Stack for Optimizing Neural Network Runtime,
Power and Endurance},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {94--99},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344087},
doi = {10.1109/VLSI-SOC46417.2020.9344087},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SimonLZA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VeronesiBK20,
author = {Alessandro Veronesi and
Davide Bertozzi and
Milos Krstic},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {Assessing the Configuration Space of the Open Source {NVDLA} Deep
Learning Accelerator on a Mainstream MPSoC Platform},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {87--112},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_5},
doi = {10.1007/978-3-030-81641-4\_5},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/VeronesiBK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VeronesiKB20,
author = {Alessandro Veronesi and
Milos Krstic and
Davide Bertozzi},
title = {Cross-Layer Hardware/Software Assessment of the Open-Source {NVDLA}
Configurable Deep Learning Accelerator},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {58--63},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344109},
doi = {10.1109/VLSI-SOC46417.2020.9344109},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/VeronesiKB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YadavLG20,
author = {Sonal Yadav and
Vijay Laxmi and
Manoj Singh Gaur},
title = {Multiple-NoC Exploration and Customization for Energy Efficient Traffic
Distribution},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {200--201},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344101},
doi = {10.1109/VLSI-SOC46417.2020.9344101},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/YadavLG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhiZZT20,
author = {Haochang Zhi and
Yanhan Zeng and
Wei Zhou and
Hongzhou Tan},
title = {Fast-transient, light-load efficient {DC-DC} converter using an auxiliary
{D-LDO}},
booktitle = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
pages = {181--185},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020.9344083},
doi = {10.1109/VLSI-SOC46417.2020.9344083},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZhiZZT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2019socs,
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-53273-4},
doi = {10.1007/978-3-030-53273-4},
isbn = {978-3-030-53272-7},
timestamp = {Mon, 27 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2019socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2020,
title = {28th {IFIP/IEEE} International Conference on Very Large Scale Integration,
{VLSI-SOC} 2020, Salt Lake City, UT, USA, October 5-7, 2020},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSI-SOC46417.2020},
doi = {10.1109/VLSI-SOC46417.2020},
isbn = {978-1-7281-5409-1},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/2020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AlbinagortaCCR19,
author = {Kevin A. C{\'{a}}ceres Albinagorta and
Calebe Concei{\c{c}}{\~{a}}o and
Carlos Silva C{\'{a}}rdenas and
Ricardo A. L. Reis},
title = {Exploring area and total wirelength using a cell merging technique},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {329--334},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920337},
doi = {10.1109/VLSI-SOC.2019.8920337},
timestamp = {Fri, 13 Dec 2019 13:34:41 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AlbinagortaCCR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AliKJA19,
author = {Ashfakh Ali and
Sai Kiran and
Arpan Jain and
Zia Abbas},
title = {A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor
for IoT Applications},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {293--298},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920345},
doi = {10.1109/VLSI-SOC.2019.8920345},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AliKJA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Atishay0STB19,
author = {Atishay and
Ankit Gupta and
Rashmi Sonawat and
Helik Kanti Thacker and
Prasanth B},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {A Statistical Wafer Scale Error and Redundancy Analysis Simulator},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {139--163},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_7},
doi = {10.1007/978-3-030-53273-4\_7},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Atishay0STB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AtishayGSTB19,
author = {Atishay and
Ankit Gupta and
Rashmi Sonawat and
Helik Kanti Thacker and
Prasanth B},
title = {{SEARS:} {A} Statistical Error and Redundancy Analysis Simulator},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {117--122},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920344},
doi = {10.1109/VLSI-SOC.2019.8920344},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AtishayGSTB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BandeiraORRO19,
author = {Vitor V. Bandeira and
Isadora Oliveira and
Felipe da Rosa and
Ricardo A. L. Reis and
Luciano Ost},
title = {Soft Error Reliability Analysis of Autonomous Vehicles Software Stack},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {253--254},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920372},
doi = {10.1109/VLSI-SOC.2019.8920372},
timestamp = {Thu, 13 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BandeiraORRO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BandeiraR0O19,
author = {Vitor V. Bandeira and
Felipe Rosa and
Ricardo Reis and
Luciano Ost},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault
Injection Techniques},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {115--137},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_6},
doi = {10.1007/978-3-030-53273-4\_6},
timestamp = {Thu, 13 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BandeiraR0O19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BandeiraRRO19,
author = {Vitor V. Bandeira and
Felipe Rosa and
Ricardo Augusto da Luz Reis and
Luciano Ost},
title = {Non-intrusive Fault Injection Techniques for Efficient Soft Error
Vulnerability Analysis},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {123--128},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920378},
doi = {10.1109/VLSI-SOC.2019.8920378},
timestamp = {Thu, 13 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BandeiraRRO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BoccoJ0DDF19,
author = {Andrea Bocco and
Tiago T. Jost and
Albert Cohen and
Florent de Dinechin and
Yves Durand and
Christian Fabre},
title = {Byte-Aware Floating-point Operations through a {UNUM} Computing Unit},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {323--328},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920387},
doi = {10.1109/VLSI-SOC.2019.8920387},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BoccoJ0DDF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BosioH019,
author = {Alberto Bosio and
Wilson{-}Javier P{\'{e}}rez{-}Holgu{\'{\i}}n and
Ernesto S{\'{a}}nchez},
title = {Exploiting Approximate Computing to Increase System Lifetime},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {311--316},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920315},
doi = {10.1109/VLSI-SOC.2019.8920315},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BosioH019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BrendlerZM019,
author = {Leonardo Heitich Brendler and
Alexandra L. Zimpeck and
Cristina Meinhardt and
Ricardo Reis},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Process Variability Impact on the {SET} Response of FinFET Multi-level
Design},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {89--113},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_5},
doi = {10.1007/978-3-030-53273-4\_5},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BrendlerZM019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BrendlerZMR19,
author = {Leonardo Heitich Brendler and
Alexandra L. Zimpeck and
Cristina Meinhardt and
Ricardo A. L. Reis},
title = {Evaluation of {SET} under Process Variability on FinFET Multi-level
Design},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {179--184},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920336},
doi = {10.1109/VLSI-SOC.2019.8920336},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BrendlerZMR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BrendlerZMR19a,
author = {Leonardo Heitich Brendler and
Alexandra L. Zimpeck and
Cristina Meinhardt and
Ricardo A. L. Reis},
title = {Impact of Process Variability and Single Event Transient on FinFET
Technology},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {249--250},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920355},
doi = {10.1109/VLSI-SOC.2019.8920355},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BrendlerZMR19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BrikLCOI19,
author = {Adil Brik and
Lioua Labrak and
Laurent Carrel and
Ian O'Connor and
Ramy Iskander},
title = {Fast extraction of predictive models for integrated circuits using
n-performance Pareto fronts},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {281--286},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920305},
doi = {10.1109/VLSI-SOC.2019.8920305},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BrikLCOI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CadareanuGGG19,
author = {Patsy Cadareanu and
Ganesh Gore and
Edouard Giacomin and
Pierre{-}Emmanuel Gaillardon},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {A Predictive Process Design Kit for Three-Independent-Gate Field-Effect
Transistors},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {307--322},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_14},
doi = {10.1007/978-3-030-53273-4\_14},
timestamp = {Mon, 27 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CadareanuGGG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChenMG19,
author = {Yu{-}Cheng Chen and
Vincent John Mooney and
Santiago Grijalva},
title = {A Survey of Attack Models for Cyber-Physical Security Assessment in
Electricity Grid},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {242--243},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920326},
doi = {10.1109/VLSI-SOC.2019.8920326},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChenMG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ConceicaoR19,
author = {Calebe Micael de Oliveira Concei{\c{c}}{\~{a}}o and
Ricardo Augusto da Luz Reis},
title = {Netlist Optimization by Gate Merging},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {236--237},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920291},
doi = {10.1109/VLSI-SOC.2019.8920291},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ConceicaoR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CoutinhoGENS19,
author = {Demetrios A. M. Coutinho and
Kyriakos Georgiou and
Kerstin I. Eder and
Jos{\'{e}} L. N{\'{u}}{\~{n}}ez{-}Y{\'{a}}{\~{n}}ez and
Samuel Xavier de Souza},
title = {Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous
Multi-Processing for Parallel Applications},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {232--233},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920384},
doi = {10.1109/VLSI-SOC.2019.8920384},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CoutinhoGENS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DamljanovicSGJ19,
author = {Aleksa Damljanovic and
Giovanni Squillero and
Cemil Cem G{\"{u}}rsoy and
Maksim Jenihhin},
title = {On NBTI-induced Aging Analysis in {IEEE} 1687 Reconfigurable Scan
Networks},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {335--340},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920313},
doi = {10.1109/VLSI-SOC.2019.8920313},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DamljanovicSGJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EliaPT19,
author = {Rafaella Elia and
George Plastiras and
Theocharis Theocharides},
title = {Towards an Embedded and Real-Time Joint Human-Machine Monitoring Framework:
Dataset optimization Techniques for Anomaly Detection},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {341--346},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920298},
doi = {10.1109/VLSI-SOC.2019.8920298},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/EliaPT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FalasKM19,
author = {Solon Falas and
Charalambos Konstantinou and
Maria K. Michael},
title = {A Hardware-based Framework for Secure Firmware Updates on Embedded
Systems},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {198--203},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920348},
doi = {10.1109/VLSI-SOC.2019.8920348},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FalasKM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FalasKM19a,
author = {Solon Falas and
Charalambos Konstantinou and
Maria K. Michael},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Hardware-Enabled Secure Firmware Updates in Embedded Systems},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {165--185},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_8},
doi = {10.1007/978-3-030-53273-4\_8},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FalasKM19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FeitozaBM19,
author = {Renato S. Feitoza and
Manuel J. Barrag{\'{a}}n and
Salvador Mir},
title = {Reduced-Code Techniques for On-Chip Static Linearity Test of {SAR}
ADCs},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {263--268},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920377},
doi = {10.1109/VLSI-SOC.2019.8920377},
timestamp = {Wed, 28 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FeitozaBM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FesquetDJLRDBME19,
author = {Laurent Fesquet and
Yoan Decoudu and
Alexis Rodrigo Iga Jadue and
Thiago Ferreira de Paiva Leite and
Otto Aureliano Rolloff and
M. Diallo and
Rodrigo Possamai Bastos and
Katell Morin{-}Allory and
Sylvain Engels},
title = {A Distributed Body-Biasing Strategy for Asynchronous Circuits},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {27--32},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920340},
doi = {10.1109/VLSI-SOC.2019.8920340},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FesquetDJLRDBME19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FettweisMWHDNH19,
author = {Gerhard P. Fettweis and
Emil Mat{\'{u}}s and
Robert Wittig and
Mattis Hasler and
Stefan A. Damjancevic and
Seungseok Nam and
Sebastian Haas},
title = {5G-and-Beyond Scalable Machines},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {105--109},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920308},
doi = {10.1109/VLSI-SOC.2019.8920308},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FettweisMWHDNH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ForlinRS19,
author = {Bruno Forlin and
Cezar Reinbrecht and
Johanna Sep{\'{u}}lveda},
title = {Attacking Real-time MPSoCs: Preemptive NoCs are Vulnerable},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {204--209},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920363},
doi = {10.1109/VLSI-SOC.2019.8920363},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ForlinRS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ForlinRS19a,
author = {Bruno Forlin and
Cezar Reinbrecht and
Johanna Sep{\'{u}}lveda},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities
of Preemptive NoCs},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {209--233},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_10},
doi = {10.1007/978-3-030-53273-4\_10},
timestamp = {Mon, 27 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ForlinRS19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GauchiKVNBMC19,
author = {Roman Gauchi and
Maha Kooli and
Pascal Vivet and
Jean{-}Philippe No{\"{e}}l and
Edith Beign{\'{e}} and
Subhasish Mitra and
Henri{-}Pierre Charles},
title = {Memory Sizing of a Scalable {SRAM} In-Memory Computing Tile Based
Architecture},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {166--171},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920373},
doi = {10.1109/VLSI-SOC.2019.8920373},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GauchiKVNBMC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GenerAGU19,
author = {Y. Serhan Gener and
Furkan Aydin and
Sezer G{\"{o}}ren and
H. Fatih Ugurdag},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Semi- and Fully-Random Access LUTs for Smooth Functions},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {279--306},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_13},
doi = {10.1007/978-3-030-53273-4\_13},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GenerAGU19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GenerGU19,
author = {Y. Serhan Gener and
Sezer G{\"{o}}ren and
H. Fatih Ugurdag},
title = {Lossless Look-Up Table Compression for Hardware Implementation of
Transcendental Functions},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {52--57},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920330},
doi = {10.1109/VLSI-SOC.2019.8920330},
timestamp = {Tue, 16 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GenerGU19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GerlachVB19,
author = {Lukas Gerlach and
Guillermo Pay{\'{a}} Vay{\'{a}} and
Holger Blume},
title = {{KAVUAKA:} {A} Low Power Application Specific Hearing Aid Processor},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {99--104},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920354},
doi = {10.1109/VLSI-SOC.2019.8920354},
timestamp = {Tue, 01 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GerlachVB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GhasempouriMDPF19,
author = {Tara Ghasempouri and
Jan Malburg and
Alessandro Danese and
Graziano Pravadelli and
G{\"{o}}rschwin Fey and
Jaan Raik},
title = {Engineering of an Effective Automatic Dynamic Assertion Mining Platform},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {111--116},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920331},
doi = {10.1109/VLSI-SOC.2019.8920331},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GhasempouriMDPF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GoreCGG19,
author = {Ganesh Gore and
Patsy Cadareanu and
Edouard Giacomin and
Pierre{-}Emmanuel Gaillardon},
title = {A Predictive Process Design Kit for Three-Independent-Gate Field-Effect
Transistors},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {172--177},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920358},
doi = {10.1109/VLSI-SOC.2019.8920358},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GoreCGG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GrossoRCR19,
author = {Michelangelo Grosso and
Salvatore Rinaudo and
Andrea Casalino and
Matteo Sonza Reorda},
title = {Software-Based Self-Test for Transition Faults: a Case Study},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {76--81},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920306},
doi = {10.1109/VLSI-SOC.2019.8920306},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GrossoRCR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GrossoRR19,
author = {Michelangelo Grosso and
Matteo Sonza Reorda and
Salvatore Rinaudo},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Software-Based Self-Test for Delay Faults},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {1--19},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_1},
doi = {10.1007/978-3-030-53273-4\_1},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GrossoRR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GuHZF19,
author = {Chenhao Gu and
Leilei Huang and
Xiaoyang Zeng and
Yibo Fan},
title = {A Micro-Code-Based Hardware Architecture of Integer Motion Estimation
for {HEVC}},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {269--274},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920393},
doi = {10.1109/VLSI-SOC.2019.8920393},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GuHZF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HsiehSD19,
author = {Chen{-}Ying Hsieh and
Ardalan Amiri Sani and
Nikil D. Dutt},
title = {{SURF:} Self-aware Unified Runtime Framework for Parallel Programs
on Heterogeneous Mobile Architectures},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {136--141},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920374},
doi = {10.1109/VLSI-SOC.2019.8920374},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HsiehSD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HsiehSD19a,
author = {Chen{-}Ying Hsieh and
Ardalan Amiri Sani and
Nikil D. Dutt},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Exploiting Heterogeneous Mobile Architectures Through a Unified Runtime
Framework},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {323--344},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_15},
doi = {10.1007/978-3-030-53273-4\_15},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HsiehSD19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Inoue19,
author = {Keisuke Inoue},
title = {An ILP-based Optimization Method for Radiation Hardened Register and
{ECC} Mixed Architectures},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {71--74},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920356},
doi = {10.1109/VLSI-SOC.2019.8920356},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Inoue19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/IranfarSZOSA19,
author = {Arman Iranfar and
Wellington Silva de Souza and
Marina Zapater and
Katzalin Olcoz and
Samuel Xavier de Souza and
David Atienza},
title = {A Machine Learning-Based Framework for Throughput Estimation of Time-Varying
Applications in Multi-Core Servers},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {211--216},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920309},
doi = {10.1109/VLSI-SOC.2019.8920309},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/IranfarSZOSA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JacquemodWLFPB19,
author = {Gilles Jacquemod and
Zhaopeng Wei and
Yves Leduc and
Emeric de Foucauld and
J{\'{e}}r{\^{o}}me Prouv{\'{e}}e and
B. Blampey},
title = {New design of analog and mixed-signal cells using back-gate cross-coupled
structure},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {21--26},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920390},
doi = {10.1109/VLSI-SOC.2019.8920390},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JacquemodWLFPB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JadueEF19,
author = {Alexis Rodrigo Iga Jadue and
Sylvain Engels and
Laurent Fesquet},
title = {A Digital Event-Based Strategy for {ASK} demodulation},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {244--245},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920304},
doi = {10.1109/VLSI-SOC.2019.8920304},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JadueEF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KirbyGRC19,
author = {Robert Kirby and
Saad Godil and
Rajarshi Roy and
Bryan Catanzaro},
title = {CongestionNet: Routing Congestion Prediction Using Deep Graph Neural
Networks},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {217--222},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920342},
doi = {10.1109/VLSI-SOC.2019.8920342},
timestamp = {Mon, 07 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KirbyGRC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LimnaiosSK19,
author = {Stavros Limnaios and
Nicolas Sklavos and
Odysseas G. Koufopavlou},
title = {Lightweight Efficient Simeck32/64 Crypto-Core Designs and Implementations,
for IoT Security},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {275--280},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920349},
doi = {10.1109/VLSI-SOC.2019.8920349},
timestamp = {Fri, 15 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LimnaiosSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LuGF19,
author = {Qi Lu and
Amir Masoud Gharehbaghi and
Masahiro Fujita},
title = {Approximate Arithmetic Circuit Design Using a Fast and Scalable Method},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {65--70},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920365},
doi = {10.1109/VLSI-SOC.2019.8920365},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LuGF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MachSZB19,
author = {Stefan Mach and
Fabian Schuiki and
Florian Zaruba and
Luca Benini},
title = {A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point
Unit for a 64 bit {RISC-V} Processor in 22nm {FD-SOI}},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {95--98},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920307},
doi = {10.1109/VLSI-SOC.2019.8920307},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MachSZB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MarquesMRLGBL19,
author = {Sandro Matheus V. N. Marques and
Thiarles S. Medeiros and
F{\'{a}}bio Diniz Rossi and
Marcelo Caggiani Luizelli and
Alessandro Gon{\c{c}}alves Girardi and
Antonio Carlos Schneider Beck and
Arthur Francisco Lorenzon},
title = {The Impact of Turbo Frequency on the Energy, Performance, and Aging
of Parallel Applications},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {149--154},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920389},
doi = {10.1109/VLSI-SOC.2019.8920389},
timestamp = {Tue, 16 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MarquesMRLGBL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MoraesZMR19,
author = {Leonardo B. Moraes and
Alexandra L. Zimpeck and
Cristina Meinhardt and
Ricardo Augusto da Luz Reis},
title = {Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {88--93},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920297},
doi = {10.1109/VLSI-SOC.2019.8920297},
timestamp = {Mon, 27 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MoraesZMR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MoraesZMR19a,
author = {Leonardo B. Moraes and
Alexandra L. Zimpeck and
Cristina Meinhardt and
Ricardo Augusto da Luz Reis},
title = {Robustness and Minimum Energy-Oriented FinFET Design},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {247--248},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920370},
doi = {10.1109/VLSI-SOC.2019.8920370},
timestamp = {Mon, 27 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MoraesZMR19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MoraesZMR19b,
author = {Leonardo B. Moraes and
Alexandra Lackmann Zimpeck and
Cristina Meinhardt and
Ricardo A. L. Reis},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Robust FinFET Schmitt Trigger Designs for Low Power Applications},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {45--68},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_3},
doi = {10.1007/978-3-030-53273-4\_3},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MoraesZMR19b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuzaffarE19,
author = {Shahzad Muzaffar and
Ibrahim Abe M. Elfadel},
title = {Double Data Rate Dynamic Edge-Coded Signaling for Low-Power IoT Communication},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {317--322},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920318},
doi = {10.1109/VLSI-SOC.2019.8920318},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MuzaffarE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NascimentoGES19,
author = {Diego V. Cirilo do Nascimento and
Kyriakos Georgiou and
Kerstin I. Eder and
Samuel Xavier de Souza},
title = {Exploiting guard band limits for energy gains in MPSoCs},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {1--2},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC46951.2019.9047904},
doi = {10.1109/VLSI-SOC46951.2019.9047904},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NascimentoGES19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NicholsGSCG19,
author = {Hunter Nichols and
Michael Grimes and
Jennifer Sowash and
Jesse Cirimelli{-}Low and
Matthew R. Guthaus},
title = {Automated Synthesis of Multi-Port Memories and Control},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {59--64},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920314},
doi = {10.1109/VLSI-SOC.2019.8920314},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NicholsGSCG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NunesAK19,
author = {Denis F. L. Nunes and
Silvio Roberto Fernandes de Araujo and
M{\'{a}}rcio Eduardo Kreutz},
title = {Optimizing an Architecture with Software Pipelining Strategies},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {299--304},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920368},
doi = {10.1109/VLSI-SOC.2019.8920368},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NunesAK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NunesK19,
author = {F. L. Denis Nunes and
M{\'{a}}rcio Eduardo Kreutz},
title = {Using {SDN} Strategies to Improve Resource Management On a NoC},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {224--225},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920321},
doi = {10.1109/VLSI-SOC.2019.8920321},
timestamp = {Mon, 13 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NunesK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OliveiraBRO19,
author = {Isadora Oliveira and
Vitor V. Bandeira and
Ricardo A. L. Reis and
Luciano Ost},
title = {Exploration of Techniques to Assess Soft Errors in Multicore Architectures},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {251--252},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920357},
doi = {10.1109/VLSI-SOC.2019.8920357},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/OliveiraBRO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OyeniranUJR19,
author = {Adeboye Stephen Oyeniran and
Raimund Ubar and
Maksim Jenihhin and
Jaan Raik},
title = {Implementation-Independent Functional Test Generation for {MSC} Microprocessors},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {82--87},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920323},
doi = {10.1109/VLSI-SOC.2019.8920323},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/OyeniranUJR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OyeniranUJR19a,
author = {Adeboye Stephen Oyeniran and
Raimund Ubar and
Maksim Jenihhin and
Jaan Raik},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {On Test Generation for Microprocessors for Extended Class of Functional
Faults},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {21--44},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_2},
doi = {10.1007/978-3-030-53273-4\_2},
timestamp = {Mon, 27 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/OyeniranUJR19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PelusoGC19,
author = {Valentino Peluso and
Matteo Grimaldi and
Andrea Calimera},
title = {Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT
Processors},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {142--147},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920341},
doi = {10.1109/VLSI-SOC.2019.8920341},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PelusoGC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PeterSFL19,
author = {Kenneth Peter and
Lars J. Svensson and
Christoffer Fougstedt and
Per Larsson{-}Edefors},
title = {Hardware Considerations for Selection Networks},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {40--45},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920322},
doi = {10.1109/VLSI-SOC.2019.8920322},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PeterSFL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ProtzeKEH0HSEM19,
author = {Florian Protze and
Martin Krei{\ss}ig and
Frank Ellinger and
Sebastian H{\"{o}}ppner and
Stephan Hartmann and
Stefan H{\"{a}}nzsche and
Stefan Scholze and
Georg Ellguth and
Christian Mayr},
title = {Performance Analysis of a Comparator Based Mixed-Signal Control Loop
in 28 nm {CMOS}},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {155--158},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920295},
doi = {10.1109/VLSI-SOC.2019.8920295},
timestamp = {Thu, 06 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ProtzeKEH0HSEM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RiosSLZA19,
author = {Marco Rios and
William Andrew Simon and
Alexandre Levisse and
Marina Zapater and
David Atienza},
title = {An Associativity-Agnostic in-Cache Computing Architecture Optimized
for Multiplication},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {34--39},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920317},
doi = {10.1109/VLSI-SOC.2019.8920317},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RiosSLZA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchvittzFRB19,
author = {Rafael B. Schvittz and
Denis Teixeira Franco and
Leomar S. da Rosa and
Paulo F. Butzen},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {An Improved Technique for Logic Gate Susceptibility Evaluation of
Single Event Transient Faults},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {69--88},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_4},
doi = {10.1007/978-3-030-53273-4\_4},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SchvittzFRB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchvittzFSB19,
author = {Rafael B. Schvittz and
Denis Teixeira Franco and
Leomar Soares and
Paulo Francisco Butzen},
title = {A Simplified Layout-Level method for Single Event Transient Faults
Susceptibility on Logic Gates},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {185--190},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920333},
doi = {10.1109/VLSI-SOC.2019.8920333},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SchvittzFSB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchvittzSB19,
author = {Rafael B. Schvittz and
Leomar Soares and
Paulo Francisco Butzen},
title = {Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability
Estimation},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {234--235},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920385},
doi = {10.1109/VLSI-SOC.2019.8920385},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SchvittzSB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SeckinerWK19,
author = {Soner Se{\c{c}}kiner and
Longfei Wang and
Sel{\c{c}}uk K{\"{o}}se},
title = {An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling
Control},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {191--196},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920381},
doi = {10.1109/VLSI-SOC.2019.8920381},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SeckinerWK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SilvaVO19,
author = {Diego A. Silva and
Orlando Verducci Jr. and
Duarte Lopes de Oliveira},
title = {Implementation of {DES} Algorithm in New Non-Synchronous Architecture
Aiming {DPA} Robustness},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {228--229},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920302},
doi = {10.1109/VLSI-SOC.2019.8920302},
timestamp = {Thu, 14 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SilvaVO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SouilemTDH19,
author = {Malek Souilem and
Jai Narayan Tripathi and
Wael Dghais and
Belgacem Hamdi},
title = {{I/O} Buffer Modelling for Power Supplies Noise Induced Jitter under
Simultaneous Switching Outputs {(SSO)}},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {226--227},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920351},
doi = {10.1109/VLSI-SOC.2019.8920351},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SouilemTDH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SouzaISZSOA19,
author = {Wellington Silva de Souza and
Arman Iranfar and
Anderson B. N. da Silva and
Marina Zapater and
Samuel Xavier de Souza and
Katzalin Olcoz and
David Atienza},
title = {A QoS and Container-Based Approach for Energy Saving and Performance
Profiling in Multi-Core Servers},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {230--231},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920379},
doi = {10.1109/VLSI-SOC.2019.8920379},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SouzaISZSOA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SzilagyiPH19,
author = {L{\'{a}}szl{\'{o}} Szil{\'{a}}gyi and
Jan Pl{\'{\i}}va and
Ronny Henker},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Offset-Compensation Systems for Multi-Gbit/s Optical Receivers},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {235--255},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_11},
doi = {10.1007/978-3-030-53273-4\_11},
timestamp = {Mon, 27 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SzilagyiPH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SzilagyiPHE19,
author = {L{\'{a}}szl{\'{o}} Szil{\'{a}}gyi and
Jan Pl{\'{\i}}va and
Ronny Henker and
Frank Ellinger},
title = {A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical
Receiver Frontends},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {46--51},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920361},
doi = {10.1109/VLSI-SOC.2019.8920361},
timestamp = {Wed, 10 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SzilagyiPHE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TonettoCBANAB19,
author = {Rafael Billig Tonetto and
Douglas Maciel Cardoso and
Marcelo Brandalero and
Luciano Agostini and
Gabriel L. Nazar and
Jos{\'{e}} Rodrigo Azambuja and
Antonio Carlos Schneider Beck},
title = {A Knapsack Methodology for Hardware-based {DMR} Protection against
Soft Errors in Superscalar Out-of-Order Processors},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {287--292},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920350},
doi = {10.1109/VLSI-SOC.2019.8920350},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/TonettoCBANAB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VieiraGQZTKAG19,
author = {Jo{\~{a}}o Vieira and
Edouard Giacomin and
Yasir Mahmood Qureshi and
Marina Zapater and
Xifan Tang and
Shahar Kvatinsky and
David Atienza and
Pierre{-}Emmanuel Gaillardon},
title = {A Product Engine for Energy-Efficient Execution of Binary Neural Networks
Using Resistive Memories},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {160--165},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920343},
doi = {10.1109/VLSI-SOC.2019.8920343},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/VieiraGQZTKAG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VieiraGQZTKAG19a,
author = {Jo{\~{a}}o Vieira and
Edouard Giacomin and
Yasir Mahmood Qureshi and
Marina Zapater and
Xifan Tang and
Shahar Kvatinsky and
David Atienza and
Pierre{-}Emmanuel Gaillardon},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Accelerating Inference on Binary Neural Networks with Digital {RRAM}
Processing},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {257--278},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_12},
doi = {10.1007/978-3-030-53273-4\_12},
timestamp = {Mon, 27 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/VieiraGQZTKAG19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WaheedE19,
author = {Owais Talaat Waheed and
Ibrahim Abe M. Elfadel},
title = {Domain-Specific Architecture for {IMU} Array Data Fusion},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {129--134},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920380},
doi = {10.1109/VLSI-SOC.2019.8920380},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/WaheedE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WangSK19,
author = {Longfei Wang and
Soner Se{\c{c}}kiner and
Sel{\c{c}}uk K{\"{o}}se},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient
Performance},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {187--208},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_9},
doi = {10.1007/978-3-030-53273-4\_9},
timestamp = {Mon, 27 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WangSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WittigHMF19,
author = {Robert Wittig and
Mattis Hasler and
Emil Mat{\'{u}}s and
Gerhard P. Fettweis},
title = {Probabilistic Models for Off-Line Arbiters in Embedded Systems},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {238--239},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920376},
doi = {10.1109/VLSI-SOC.2019.8920376},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/WittigHMF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WuG19,
author = {Bin Wu and
Matthew R. Guthaus},
title = {Bottom-Up Approach for High Speed {SRAM} Word-line Buffer Insertion
Optimization},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {305--310},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920325},
doi = {10.1109/VLSI-SOC.2019.8920325},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WuG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YasinSPC19,
author = {Atif Yasin and
Tiankai Su and
S{\'{e}}bastien Pillement and
Maciej J. Ciesielski},
title = {Functional Verification of Hardware Dividers using Algebraic Model},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {257--262},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920335},
doi = {10.1109/VLSI-SOC.2019.8920335},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/YasinSPC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZimpeckMAHKR19,
author = {Alexandra L. Zimpeck and
Cristina Meinhardt and
Laurent Artola and
Guillaume Hubert and
Fernanda Lima Kastensmidt and
Ricardo Augusto da Luz Reis},
title = {Circuit-Level Techniques to Mitigate Process Variability and Soft
Errors in FinFET Designs},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {240--241},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920383},
doi = {10.1109/VLSI-SOC.2019.8920383},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZimpeckMAHKR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2017socs,
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-15663-3},
doi = {10.1007/978-3-030-15663-3},
isbn = {978-3-030-15662-6},
timestamp = {Tue, 12 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2017socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2018socs,
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-23425-6},
doi = {10.1007/978-3-030-23425-6},
isbn = {978-3-030-23424-9},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2018socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2019,
title = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
publisher = {{IEEE}},
year = {2019},
url = {https://ieeexplore.ieee.org/xpl/conhome/8910139/proceeding},
isbn = {978-1-7281-3915-9},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/2019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/0001BLP18,
author = {Anna Bernasconi and
Antonio Boffa and
Fabrizio Luccio and
Linda Pagli},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {The Connection Layout in a Lattice of Four-Terminal Switches},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {32--52},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_3},
doi = {10.1007/978-3-030-23425-6\_3},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/0001BLP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AldegheriMB18,
author = {Stefano Aldegheri and
Silvia Manzato and
Nicola Bombieri},
title = {Enhancing Performance of Computer Vision Applications on Low-Power
Embedded Systems Through Heterogeneous Parallel Programming},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {119--124},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644937},
doi = {10.1109/VLSI-SOC.2018.8644937},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AldegheriMB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AnghelLNMVV18,
author = {Lorena Anghel and
Denys Ly and
Giorgio Di Natale and
Beno{\^{\i}}t Miramond and
Elena Ioana Vatajelu and
Elisa Vianello},
title = {Neuromorphic Computing - From Robust Hardware Architectures to Testing
Strategies},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {176--179},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644897},
doi = {10.1109/VLSI-SOC.2018.8644897},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AnghelLNMVV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AvramenkoANVRJ18,
author = {Serhiy Avramenko and
Siavoosh Payandeh Azad and
Behrad Niazmand and
Massimo Violante and
Jaan Raik and
Maksim Jenihhin},
title = {Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications
and Power Analysis},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {207--212},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644866},
doi = {10.1109/VLSI-SOC.2018.8644866},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AvramenkoANVRJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AwaisMP18,
author = {Muhammad Awais and
Hassan Ghasemzadeh Mohammadi and
Marco Platzner},
title = {An MCTS-based Framework for Synthesis of Approximate Circuits},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {219--224},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8645026},
doi = {10.1109/VLSI-SOC.2018.8645026},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AwaisMP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BarchiUAM18,
author = {Francesco Barchi and
Gianvito Urgese and
Andrea Acquaviva and
Enrico Macii},
title = {Directed Graph Placement for {SNN} Simulation into a multi-core {GALS}
Architecture},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {19--24},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644782},
doi = {10.1109/VLSI-SOC.2018.8644782},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BarchiUAM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BarchiUMA18,
author = {Francesco Barchi and
Gianvito Urgese and
Enrico Macii and
Andrea Acquaviva},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms:
Problem Formulation and Performance Analysis},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {167--186},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_9},
doi = {10.1007/978-3-030-23425-6\_9},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BarchiUMA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BenelliMF18,
author = {Gionata Benelli and
Gabriele Meoni and
Luca Fanucci},
title = {A low power keyword spotting algorithm for memory constrained embedded
systems},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {267--272},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644728},
doi = {10.1109/VLSI-SOC.2018.8644728},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BenelliMF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernasconiBLP18,
author = {Anna Bernasconi and
Antonio Boffa and
Fabrizio Luccio and
Linda Pagli},
title = {Two Combinatorial Problems on the Layout of Switching Lattices},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {137--142},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644855},
doi = {10.1109/VLSI-SOC.2018.8644855},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BernasconiBLP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernasconiCF18,
author = {Anna Bernasconi and
Valentina Ciriani and
Luca Frontini},
title = {Testability of Switching Lattices in the Stuck at Fault Model},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {213--218},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644806},
doi = {10.1109/VLSI-SOC.2018.8644806},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BernasconiCF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BigalkeL18,
author = {Steve Bigalke and
Jens Lienig},
title = {{FLUTE-EM:} Electromigration-Optimized Net Considering Topology Currents
and Mechanical Stress},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {225--230},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644965},
doi = {10.1109/VLSI-SOC.2018.8644965},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BigalkeL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BraunFMSS18,
author = {Konstantin Braun and
Tim Fritzmann and
Georg Maringer and
Thomas Schamberger and
Johanna Sep{\'{u}}lveda},
title = {Secure and Compact Full {NTRU} Hardware Implementation},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {89--94},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8645015},
doi = {10.1109/VLSI-SOC.2018.8645015},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BraunFMSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BrendlerZMR18,
author = {Leonardo Heitich Brendler and
Alexandra L. Zimpeck and
Cristina Meinhardt and
Ricardo Reis},
title = {Evaluating the Impact of Process Variability and Radiation Effects
on Different Transistor Arrangements},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {71--76},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644828},
doi = {10.1109/VLSI-SOC.2018.8644828},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BrendlerZMR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CantoroCF0RM18,
author = {Riccardo Cantoro and
Sara Carbonara and
Andrea Floridia and
Ernesto S{\'{a}}nchez and
Matteo Sonza Reorda and
Jan{-}Gerd Mess},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {Improved Test Solutions for COTS-Based Systems in Space Applications},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {187--206},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_10},
doi = {10.1007/978-3-030-23425-6\_10},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CantoroCF0RM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CantoroCFSRM18,
author = {Riccardo Cantoro and
Sara Carbonara and
Andrea Floridia and
Ernesto S{\'{a}}nchez and
Matteo Sonza Reorda and
Jan{-}Gerd Mess},
title = {An analysis of test solutions for COTS-based systems in space applications},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {59--64},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644846},
doi = {10.1109/VLSI-SOC.2018.8644846},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CantoroCFSRM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CentomoPF18,
author = {Stefano Centomo and
Marco Panato and
Franco Fummi},
title = {Cyber-Physical Systems Integration in a Production Line Simulator},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {237--242},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644836},
doi = {10.1109/VLSI-SOC.2018.8644836},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CentomoPF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChampacGFR18,
author = {V{\'{\i}}ctor H. Champac and
Andres F. Gomez and
Freddy Forero and
Kaushik Roy},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {Analysis of Bridge Defects in {STT-MRAM} Cells Under Process Variations
and a Robust {DFT} Technique for Their Detection},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {207--231},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_11},
doi = {10.1007/978-3-030-23425-6\_11},
timestamp = {Sun, 05 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChampacGFR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChenV18,
author = {Suyuan Chen and
Ranga Vemuri},
title = {On the Effectiveness of the Satisfiability Attack on Split Manufactured
Circuits},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {83--88},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644963},
doi = {10.1109/VLSI-SOC.2018.8644963},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChenV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DemroziCTP18,
author = {Florenc Demrozi and
Kevin Costa and
Federico Tramarin and
Graziano Pravadelli},
title = {A graph-based approach for mobile localization exploiting real and
virtual landmarks},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {249--254},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644877},
doi = {10.1109/VLSI-SOC.2018.8644877},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/DemroziCTP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DengWKWZ18,
author = {Erya Deng and
Zhaohao Wang and
Wang Kang and
Shaoqian Wei and
Weisheng Zhao},
title = {Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque
{MRAM}},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {184--187},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644729},
doi = {10.1109/VLSI-SOC.2018.8644729},
timestamp = {Mon, 02 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DengWKWZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DevarajegowdaE18,
author = {Keerthikumara Devarajegowda and
Wolfgang Ecker},
title = {Meta-model Based Automation of Properties for Pre-Silicon Verification},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {231--236},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644957},
doi = {10.1109/VLSI-SOC.2018.8644957},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/DevarajegowdaE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FeyGJMRR18,
author = {G{\"{o}}rschwin Fey and
Tara Ghasempouri and
Swen Jacobs and
Gianluca Martino and
Jaan Raik and
Heinz Riener},
title = {Design Understanding: From Logic to Specification\({}^{\mbox{*}}\)},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {172--175},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644732},
doi = {10.1109/VLSI-SOC.2018.8644732},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FeyGJMRR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FornoAKMU18,
author = {Evelina Forno and
Andrea Acquaviva and
Yuki Kobayashi and
Enrico Macii and
Gianvito Urgese},
title = {A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {31--36},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644777},
doi = {10.1109/VLSI-SOC.2018.8644777},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FornoAKMU18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FritzmannSFBMS18,
author = {Tim Fritzmann and
Thomas Schamberger and
Christoph Frisch and
Konstantin Braun and
Georg Maringer and
Johanna Sep{\'{u}}lveda},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {Efficient Hardware/Software Co-design for {NTRU}},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {257--280},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_13},
doi = {10.1007/978-3-030-23425-6\_13},
timestamp = {Fri, 05 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FritzmannSFBMS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GiacominG18,
author = {Edouard Giacomin and
Pierre{-}Emmanuel Gaillardon},
title = {Differential Power Analysis Mitigation Technique Using Three-Independent-Gate
Field Effect Transistors},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {107--112},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644747},
doi = {10.1109/VLSI-SOC.2018.8644747},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GiacominG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GomezFRC18,
author = {Andres F. Gomez and
Freddy Forero and
Kaushik Roy and
V{\'{\i}}ctor H. Champac},
title = {Robust Detection of Bridge Defects in {STT-MRAM} Cells Under Process
Variations},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {65--70},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8645022},
doi = {10.1109/VLSI-SOC.2018.8645022},
timestamp = {Sun, 05 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GomezFRC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GuptaIRSKE18,
author = {Utkarsh Gupta and
Irina Ilioaea and
Vikas Rao and
Arpitha Srinath and
Priyank Kalla and
Florian Enescu},
title = {On the Rectifiability of Arithmetic Circuits using Craig Interpolants
in Finite Fields},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {49--54},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644853},
doi = {10.1109/VLSI-SOC.2018.8644853},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GuptaIRSKE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GuptaIRSKE18a,
author = {Utkarsh Gupta and
Irina Ilioaea and
Vikas Rao and
Arpitha Srinath and
Priyank Kalla and
Florian Enescu},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {Rectification of Arithmetic Circuits with Craig Interpolants in Finite
Fields},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {79--106},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_5},
doi = {10.1007/978-3-030-23425-6\_5},
timestamp = {Wed, 26 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GuptaIRSKE18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HuangLY18,
author = {Juinn{-}Dar Huang and
Chia{-}Hung Liu and
Wei{-}Hao Yang},
title = {Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose
Digital Microfluidic Biochips},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {13--18},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644984},
doi = {10.1109/VLSI-SOC.2018.8644984},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HuangLY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HussainG18,
author = {Mubashir Hussain and
Hui Guo},
title = {A Bandwidth-Aware Authentication Scheme for Packet-Integrity Attack
Detection on Trojan Infected NoC},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {201--206},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8645051},
doi = {10.1109/VLSI-SOC.2018.8645051},
timestamp = {Fri, 31 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HussainG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JuniorB18,
author = {Luiz Antonio de Oliveira Junior and
Edna Barros},
title = {An FPGA-based Hardware Accelerator for Scene Text Character Recognition},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {125--130},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644776},
doi = {10.1109/VLSI-SOC.2018.8644776},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JuniorB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KelirisKSM18,
author = {Anastasis Keliris and
Charalambos Konstantinou and
Marios Sazos and
Michail Maniatakos},
title = {Low-budget Energy Sector Cyberattacks via Open Source Exploitation},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {101--106},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644775},
doi = {10.1109/VLSI-SOC.2018.8644775},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KelirisKSM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KernecFYLR18,
author = {Julien Le Kernec and
Francesco Fioranelli and
Shufan Yang and
Jordane Lorandel and
Olivier Romain},
title = {Radar for assisted living in the context of Internet of Things for
Health and beyond},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {163--167},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644816},
doi = {10.1109/VLSI-SOC.2018.8644816},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KernecFYLR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LamlihFBSKSBRB18,
author = {Achraf Lamlih and
Philippe Freitas and
Mohamed Moez Belhaj and
J{\'{e}}r{\'{e}}mie Salles and
Vincent Kerzerho and
Fabien Soulier and
Serge Bernard and
Tristan Rouyer and
Sylvain Bonhommeau},
title = {A Hybrid Bioimpedance Spectroscopy Architecture for a Wide Frequency
Exploration of Tissue Electrical Properties},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {168--171},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644829},
doi = {10.1109/VLSI-SOC.2018.8644829},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LamlihFBSKSBRB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiuKKSM18,
author = {Xiaorui Liu and
Anastasis Keliris and
Charalambos Konstantinou and
Marios Sazos and
Michail Maniatakos},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {Assessment of Low-Budget Targeted Cyberattacks Against Power Systems},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {232--256},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_12},
doi = {10.1007/978-3-030-23425-6\_12},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LiuKKSM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MahalatUSS18,
author = {Mahabub Hasan Mahalat and
Nikhil Ugale and
Rohit Shahare and
Bibhash Sen},
title = {Design of Latch based Configurable Ring Oscillator {PUF} Targeting
Secure {FPGA}},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {261--266},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644737},
doi = {10.1109/VLSI-SOC.2018.8644737},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MahalatUSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MandalBTC18,
author = {Swagata Mandal and
Debjyoti Bhattacharjee and
Yaswanth Tavva and
Anupam Chattopadhyay},
title = {ReRAM-based In-Memory Computation of Galois Field arithmetic},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644772},
doi = {10.1109/VLSI-SOC.2018.8644772},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MandalBTC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MandalTBC18,
author = {Swagata Mandal and
Yaswanth Tavva and
Debjyoti Bhattacharjee and
Anupam Chattopadhyay},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {ReRAM Based In-Memory Computation of Single Bit Error Correcting {BCH}
Code},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {128--146},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_7},
doi = {10.1007/978-3-030-23425-6\_7},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MandalTBC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MatsumotoHATNKN18,
author = {Kaori Matsumoto and
Tetsuya Hirose and
Hiroki Asano and
Yuto Tsuji and
Yuichiro Nakazawa and
Nobutaka Kuroki and
Masahiro Numa},
title = {An ultra-low power active diode using a hysteresis common gate comparator
for low-voltage and low-power energy harvesting systems},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {196--200},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644968},
doi = {10.1109/VLSI-SOC.2018.8644968},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MatsumotoHATNKN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MoreauMBAPGN18,
author = {Mathieu Moreau and
Eloi Muhr and
Marc Bocquet and
Hassen Aziza and
Jean{-}Michel Portal and
Bastien Giraud and
Jean{-}Philippe Noel},
title = {Reliable ReRAM-based Logic Operations for Computing in Memory},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {192--195},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644780},
doi = {10.1109/VLSI-SOC.2018.8644780},
timestamp = {Fri, 24 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MoreauMBAPGN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Murat18,
author = {Yakup Murat},
title = {Key Architectural Optimizations for Hardware Efficient {JPEG-LS} Encoder},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {243--248},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644996},
doi = {10.1109/VLSI-SOC.2018.8644996},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Murat18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuzaffarE18,
author = {Shahzad Muzaffar and
Ibrahim Abe M. Elfadel},
title = {An Instruction Set Architecture for Low-power, Dynamic IoT Communication},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {37--42},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644770},
doi = {10.1109/VLSI-SOC.2018.8644770},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MuzaffarE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuzaffarE18a,
author = {Shahzad Muzaffar and
Ibrahim Abe M. Elfadel},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT
Communication},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {14--31},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_2},
doi = {10.1007/978-3-030-23425-6\_2},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MuzaffarE18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OjimaNIA18,
author = {Naoki Ojima and
Toru Nakura and
Tetsuya Iizuka and
Kunihiro Asada},
title = {A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time
Conversion},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {55--58},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644879},
doi = {10.1109/VLSI-SOC.2018.8644879},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/OjimaNIA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OjimaNIA18a,
author = {Naoki Ojima and
Toru Nakura and
Tetsuya Iizuka and
Kunihiro Asada},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {A 65 nm {CMOS} Synthesizable Digital Low-Dropout Regulator Based on
Voltage-to-Time Conversion with 99.6{\%} Current Efficiency at 10-mA
Load},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {1--13},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_1},
doi = {10.1007/978-3-030-23425-6\_1},
timestamp = {Wed, 26 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/OjimaNIA18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OrConnorCMVSBMM18,
author = {Ian O'Connor and
Mayeul Cantan and
C{\'{e}}dric Marchand and
Bertrand Vilquin and
Stefan Slesazeck and
Evelyn T. Breyer and
Halid Mulaosmanovic and
Thomas Mikolajick and
Bastien Giraud and
Jean{-}Philippe Noel and
Adrian M. Ionescu and
Igor Stolichnov},
title = {Prospects for energy-efficient edge computing with integrated HfO2-based
ferroelectric devices},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {180--183},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644809},
doi = {10.1109/VLSI-SOC.2018.8644809},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/OrConnorCMVSBMM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PelusoC18,
author = {Valentino Peluso and
Andrea Calimera},
title = {Energy-Driven Precision Scaling for Fixed-Point ConvNets},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {113--118},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644902},
doi = {10.1109/VLSI-SOC.2018.8644902},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PelusoC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PelusoC18a,
author = {Valentino Peluso and
Andrea Calimera},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {Energy-Accuracy Scalable Deep Convolutional Neural Networks: {A} Pareto
Analysis},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {107--127},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_6},
doi = {10.1007/978-3-030-23425-6\_6},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PelusoC18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PerezVC18,
author = {Zahira Perez and
Hector Villacorta and
V{\'{\i}}ctor H. Champac},
title = {An accurate novel gate-sizing metric to optimize circuit performance
under local intra-die process variations},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {77--82},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644864},
doi = {10.1109/VLSI-SOC.2018.8644864},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PerezVC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RanjandishS18,
author = {Reza Ranjandish and
Alexandre Schmid},
title = {Implantable IoT System for Closed-Loop Epilepsy Control based on Electrical
Neuromodulation},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {155--158},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8645023},
doi = {10.1109/VLSI-SOC.2018.8645023},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RanjandishS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchiavoneSRMZHB18,
author = {Pasquale Davide Schiavone and
Ernesto S{\'{a}}nchez and
Annachiara Ruospo and
Francesco Minervini and
Florian Zaruba and
Germain Haugou and
Luca Benini},
title = {An Open-Source Verification Framework for Open-Source Cores: {A} {RISC-V}
Case Study},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {43--48},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644818},
doi = {10.1109/VLSI-SOC.2018.8644818},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SchiavoneSRMZHB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SenniOMSPBNTDPP18,
author = {Sophiane Senni and
Frederic Ouattara and
Jad Mohdad and
Kaan Sevin and
Guillaume Patrigeon and
Pascal Benoit and
Pascal Nouet and
Lionel Torres and
Fran{\c{c}}ois Duhem and
Gregory di Pendina and
Guillaume Prenat},
title = {From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {188--191},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644875},
doi = {10.1109/VLSI-SOC.2018.8644875},
timestamp = {Wed, 22 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SenniOMSPBNTDPP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ShresthaS18,
author = {Rahul Shrestha and
Ashutosh Sharma},
title = {VLSI-Architecture of Radix-2/4/8 {SISO} Decoder for Turbo Decoding
at Multiple Data-rates},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {131--136},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644753},
doi = {10.1109/VLSI-SOC.2018.8644753},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ShresthaS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SleebaJPJM18,
author = {Simi Zerine Sleeba and
John Jose and
Maurizio Palesi and
Rekha K. James and
Maniyelil Govindankutty Mini},
title = {Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {25--30},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8645011},
doi = {10.1109/VLSI-SOC.2018.8645011},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SleebaJPJM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SouchaudJCHRTS18,
author = {Marc Souchaud and
Pierre Jacob and
Camille Simon Chane and
Aymeric Histace and
Olivier Romain and
Maurice Tchuent{\'{e}} and
Denis Sereno},
title = {Mobile Phones Hematophagous Diptera Surveillance in the field using
Deep Learning and Wing Interference Patterns},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {159--162},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644845},
doi = {10.1109/VLSI-SOC.2018.8644845},
timestamp = {Wed, 25 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SouchaudJCHRTS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/StornaiuoloRSSC18,
author = {Luca Stornaiuolo and
Marco Rabozzi and
Marco D. Santambrogio and
Donatella Sciuto and
Catalin Bogdan Ciobanu and
Giulio Stramondo and
Ana Lucia Varbanescu},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {Building High-Performance, Easy-to-Use Polymorphic Parallel Memories
with {HLS}},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {53--78},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_4},
doi = {10.1007/978-3-030-23425-6\_4},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/StornaiuoloRSSC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/StornaiuoloRSSS18,
author = {Luca Stornaiuolo and
Marco Rabozzi and
Donatella Sciuto and
Marco D. Santambrogio and
Giulio Stramondo and
Catalin Bogdan Ciobanu and
Ana Lucia Varbanescu},
title = {{HLS} Support for Polymorphic Parallel Memories},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {143--148},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644899},
doi = {10.1109/VLSI-SOC.2018.8644899},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/StornaiuoloRSSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TalaB18,
author = {Mahdi Tala and
Davide Bertozzi},
title = {Understanding the Design Space of Wavelength-Routed Optical NoC Topologies
for Power-Performance Optimization},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {255--260},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644998},
doi = {10.1109/VLSI-SOC.2018.8644998},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/TalaB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TenaceC18,
author = {Valerio Tenace and
Andrea Calimera},
title = {Inferential Logic: a Machine Learning Inspired Paradigm for Combinational
Circuits},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {149--154},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644808},
doi = {10.1109/VLSI-SOC.2018.8644808},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TenaceC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WongPC18,
author = {Ming Ming Wong and
Vikramkumar Pudi and
Anupam Chattopadhyay},
title = {Lightweight and High Performance {SHA-256} using Architectural Folding
and 4-2 Adder Compressor},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {95--100},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644825},
doi = {10.1109/VLSI-SOC.2018.8644825},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/WongPC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZamanJK18,
author = {Md. Adnan Zaman and
Rajeev Joshi and
Srinivas Katkoori},
editor = {Nicola Bombieri and
Graziano Pravadelli and
Masahiro Fujita and
Todd M. Austin and
Ricardo Reis},
title = {Optimizing Performance and Energy Overheads Due to Fanout in In-Memory
Computing Systems},
booktitle = {VLSI-SoC: Design and Engineering of Electronics Systems Based on New
Computing Paradigms - 26th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October
8-10, 2018, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {561},
pages = {147--166},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-23425-6\_8},
doi = {10.1007/978-3-030-23425-6\_8},
timestamp = {Wed, 26 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZamanJK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZamanK18,
author = {Md. Adnan Zaman and
Srinivas Katkoori},
title = {Minimizing Performance and Energy Overheads Due to Fanout In Memristor
based Logic Implementations},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {7--12},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644723},
doi = {10.1109/VLSI-SOC.2018.8644723},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZamanK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2018soc,
title = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
publisher = {{IEEE}},
year = {2018},
url = {https://ieeexplore.ieee.org/xpl/conhome/8642560/proceeding},
isbn = {978-1-5386-4756-1},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2018soc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/0001BJFS17,
author = {Binod Kumar and
Kanad Basu and
Ankit Jindal and
Masahiro Fujita and
Virendra Singh},
title = {Improving post-silicon error detection with topological selection
of trace signals},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203485},
doi = {10.1109/VLSI-SOC.2017.8203485},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/0001BJFS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AdimulamMKS17,
author = {Mahesh Kumar Adimulam and
Krishna Kumar Movva and
Amit Kapoor and
M. B. Srinivas},
title = {A low power, programmable bias inverter quantizer {(BIQ)} flash {ADC}},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203489},
doi = {10.1109/VLSI-SOC.2017.8203489},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AdimulamMKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AgarwalK17,
author = {Sukarn Agarwal and
Hemangee K. Kapoor},
title = {Targeting inter set write variation to improve the lifetime of non-volatile
cache using fellow sets},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203453},
doi = {10.1109/VLSI-SOC.2017.8203453},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AgarwalK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AgarwalK17a,
author = {Sukarn Agarwal and
Hemangee K. Kapoor},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic
Associativity Management Techniques},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {46--71},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_3},
doi = {10.1007/978-3-030-15663-3\_3},
timestamp = {Tue, 12 Sep 2023 07:57:22 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AgarwalK17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AhmedNA17,
author = {Islam Ahmed and
Khaled Nouh and
Amr Abbas},
title = {Multiple reset domains verification using assertion based verification},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203467},
doi = {10.1109/VLSI-SOC.2017.8203467},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AhmedNA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AlagappanRDV17,
author = {Murugappan Alagappan and
Jeyavijayan Rajendran and
Milos Doroslovacki and
Guru Venkataramani},
title = {{DFS} covert channels on multi-core platforms},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203469},
doi = {10.1109/VLSI-SOC.2017.8203469},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AlagappanRDV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AldegheriB17,
author = {Stefano Aldegheri and
Nicola Bombieri},
title = {Extending OpenVX for model-based design of embedded vision applications},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203457},
doi = {10.1109/VLSI-SOC.2017.8203457},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AldegheriB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AldegheriB17a,
author = {Stefano Aldegheri and
Nicola Bombieri},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Integrating Simulink, OpenVX, and {ROS} for Model-Based Design of
Embedded Vision Applications},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {178--197},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_9},
doi = {10.1007/978-3-030-15663-3\_9},
timestamp = {Fri, 17 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AldegheriB17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Bakir17,
author = {Muhannad S. Bakir},
title = {PhD forum: Heterogeneous interconnection of ICs using stitch-chips},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203451},
doi = {10.1109/VLSI-SOC.2017.8203451},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Bakir17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernardiLPR0S17,
author = {Paolo Bernardi and
Sergio de Luca and
Davide Piumatti and
S. Regis and
Ernesto S{\'{a}}nchez and
Alessandro Sansonetti},
title = {On the in-field testing of spare modules in automotive microprocessors},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203459},
doi = {10.1109/VLSI-SOC.2017.8203459},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BernardiLPR0S17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CamposDTTT17,
author = {Pedro B. Campos and
Nizar Dahir and
Martin Trefzer and
Andy M. Tyrrell and
Gianluca Tempesti},
title = {LeAF: {A} low-overhead asymmetric frequency controller for NoC router
interconnects},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203454},
doi = {10.1109/VLSI-SOC.2017.8203454},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CamposDTTT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CesariniBB17,
author = {Daniele Cesarini and
Andrea Bartolini and
Luca Benini},
title = {Prediction horizon vs. efficiency of optimal dynamic thermal control
policies in {HPC} nodes},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203471},
doi = {10.1109/VLSI-SOC.2017.8203471},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CesariniBB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CesariniBB17a,
author = {Daniele Cesarini and
Andrea Bartolini and
Luca Benini},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Modeling and Evaluation of Application-Aware Dynamic Thermal Control
in {HPC} Nodes},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {198--219},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_10},
doi = {10.1007/978-3-030-15663-3\_10},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CesariniBB17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CimatoCDE17,
author = {Stelvio Cimato and
Valentina Ciriani and
Ernesto Damiani and
Maryam Ehsanpour},
title = {A multiple valued logic approach for the synthesis of garbled circuits},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--5},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203495},
doi = {10.1109/VLSI-SOC.2017.8203495},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CimatoCDE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CopettiBMP17,
author = {Thiago Santos Copetti and
Tiago R. Balen and
Guilherme Cardoso Medeiros and
Let{\'{\i}}cia Maria Bolzani Poehls},
title = {Analyzing the behavior of FinFET SRAMs with resistive defects},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203483},
doi = {10.1109/VLSI-SOC.2017.8203483},
timestamp = {Wed, 20 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CopettiBMP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CopettiMPB17,
author = {Thiago Santos Copetti and
Guilherme Cardoso Medeiros and
Let{\'{\i}}cia Maria Bolzani Poehls and
Tiago R. Balen},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {22--45},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_2},
doi = {10.1007/978-3-030-15663-3\_2},
timestamp = {Fri, 17 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CopettiMPB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FujitaKW17,
author = {Masahiro Fujita and
Yusuke Kimura and
Qinhao Wang},
title = {Template based synthesis for high performance computing},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203492},
doi = {10.1109/VLSI-SOC.2017.8203492},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FujitaKW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GharehbaghiF17,
author = {Amir Masoud Gharehbaghi and
Masahiro Fujita},
title = {A new approach for constructing logic functions after {ECO}},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203465},
doi = {10.1109/VLSI-SOC.2017.8203465},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GharehbaghiF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HuangCL17,
author = {Juinn{-}Dar Huang and
Yi{-}Hang Chen and
Jia{-}Shin Lu},
title = {Defect-aware synthesis for reconfigurable single-electron transistor
arrays},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203487},
doi = {10.1109/VLSI-SOC.2017.8203487},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HuangCL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Ismail17,
author = {Mohammed Ismail},
title = {A self-powered IoT SoC platform for wearable health care},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203450},
doi = {10.1109/VLSI-SOC.2017.8203450},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Ismail17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/IsmailE17,
author = {Ayman H. Ismail and
Ayman ElSayed},
title = {{\(\sum\)}-{\(\Delta\)} based force-feedback capacitive micro-machined
sensors: Extending the input signal range},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203482},
doi = {10.1109/VLSI-SOC.2017.8203482},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/IsmailE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JayakrishnanCK17,
author = {Mini Jayakrishnan and
Alan Chang and
Tony T. Kim},
title = {Library pruning and sigma corner libraries for power efficient variation
tolerant processor pipelines},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203484},
doi = {10.1109/VLSI-SOC.2017.8203484},
timestamp = {Sat, 06 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JayakrishnanCK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KerkhoffAWIP17,
author = {Hans G. Kerkhoff and
Ghazanfar Ali and
Jinbo Wan and
Ahmed Ibrahim and
Jerrin Pathrose},
title = {Applying IJTAG-compatible embedded instruments for lifetime enhancement
of analog front-ends of cyber-physical systems},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203464},
doi = {10.1109/VLSI-SOC.2017.8203464},
timestamp = {Wed, 08 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KerkhoffAWIP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KifleSMI17,
author = {Yonatan Kifle and
Hani H. Saleh and
Baker Mohammad and
Mohammed Ismail},
title = {A sub-{\(\mu\)}W bio-potential front end in 65nm {CMOS}},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203463},
doi = {10.1109/VLSI-SOC.2017.8203463},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KifleSMI17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimC17,
author = {Kyounghoon Kim and
Kiyoung Choi},
title = {Synthesis of multi-variate stochastic computing circuits},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203493},
doi = {10.1109/VLSI-SOC.2017.8203493},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KimC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Ma0Y17,
author = {Yuzhe Ma and
Xuan Zeng and
Bei Yu},
title = {Methodologies for layout decomposition and mask optimization: {A}
systematic review},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203477},
doi = {10.1109/VLSI-SOC.2017.8203477},
timestamp = {Mon, 01 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Ma0Y17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MichaelEMTP17,
author = {George Michael and
Nectarios Efstathiou and
Kyriacos Mantis and
Theocharis Theocharides and
Danilo Pau},
title = {Intelligent embedded and real-time ANN-based motor control for multi-rotor
unmanned aircraft systems},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203456},
doi = {10.1109/VLSI-SOC.2017.8203456},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MichaelEMTP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuzaffarE17,
author = {Shahzad Muzaffar and
Ibrahim M. Elfadel},
title = {A pulsed decimal technique for single-channel, dynamic signaling for
IoT applications},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203491},
doi = {10.1109/VLSI-SOC.2017.8203491},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MuzaffarE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuzaffarE17a,
author = {Shahzad Muzaffar and
Ibrahim Abe M. Elfadel},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Pulsed Decimal Encoding for IoT Single-Channel Dynamic Signaling},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {112--132},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_6},
doi = {10.1007/978-3-030-15663-3\_6},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MuzaffarE17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NakadaYNIUTH17,
author = {Takashi Nakada and
Hiroyuki Yanagihashi and
Hiroshi Nakamura and
Kunimaro Imai and
Hiroshi Ueki and
Takashi Tsuchiya and
Masanori Hayashikoshi},
title = {Energy-aware task scheduling for near real-time periodic tasks on
heterogeneous multicore processors},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203458},
doi = {10.1109/VLSI-SOC.2017.8203458},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NakadaYNIUTH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NautiyalGSDDK17,
author = {Vivek Nautiyal and
Lalit Gupta and
Gaurav Singla and
Jitendra Dasani and
Sagar Dwivedi and
Martin Kinkade},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port {SRAM}
Used in Low-Voltage IoT Applications},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {92--111},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_5},
doi = {10.1007/978-3-030-15663-3\_5},
timestamp = {Fri, 17 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NautiyalGSDDK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NautiyalSGDDK17,
author = {Vivek Nautiyal and
Gaurav Singla and
Lalit Gupta and
Jitendra Dasani and
Sagar Dwivedi and
Martin Kinkade},
title = {Robust, self-timed power-on reset circuit for low-voltage applications},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203474},
doi = {10.1109/VLSI-SOC.2017.8203474},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NautiyalSGDDK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NguyenYXTHF17,
author = {Hoang Anh Du Nguyen and
Jintao Yu and
Lei Xie and
Mottaqiallah Taouil and
Said Hamdioui and
Dietmar Fey},
title = {Memristive devices for computing: Beyond {CMOS} and beyond von Neumann},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--10},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203479},
doi = {10.1109/VLSI-SOC.2017.8203479},
timestamp = {Mon, 26 Mar 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NguyenYXTHF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Ovilla-Martinez17,
author = {Brisbane Ovilla{-}Martinez and
Lilian Bossuet},
title = {Restoration protocol: Lightweight and secur devices authentication
based on {PUF}},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203460},
doi = {10.1109/VLSI-SOC.2017.8203460},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Ovilla-Martinez17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Paul-PenaKKK17,
author = {David Paul{-}Pena and
Prashanth Krishnamurthy and
Ramesh Karri and
Farshad Khorrami},
title = {Process-aware side channel monitoring for embedded control system
security},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203468},
doi = {10.1109/VLSI-SOC.2017.8203468},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Paul-PenaKKK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RajDJ17,
author = {R. S. Reshma Raj and
Abhijit Das and
John Jose},
title = {Implementation and analysis of hotspot mitigation in mesh NoCs by
cost-effective deflection routing technique},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203461},
doi = {10.1109/VLSI-SOC.2017.8203461},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RajDJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RanaPD17,
author = {Vikas Rana and
Marco Pasotti and
F. Desantis},
title = {Single charge-pump generating high positive and negative voltages
driving common load},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203476},
doi = {10.1109/VLSI-SOC.2017.8203476},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RanaPD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ReisG17,
author = {Ricardo Reis and
Manfred Glesner},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {VLSI-SoC: An Enduring Tradition},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {240--255},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_12},
doi = {10.1007/978-3-030-15663-3\_12},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ReisG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RizzoPCZ17,
author = {Roberto Giorgio Rizzo and
Valentino Peluso and
Andrea Calimera and
Jun Zhou},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {On the Efficiency of Early Bird Sampling {(EBS)} an Error Detection-Correction
Scheme for Data-Driven Voltage Over-Scaling},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {153--177},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_8},
doi = {10.1007/978-3-030-15663-3\_8},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RizzoPCZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RizzoPCZL17,
author = {Roberto Giorgio Rizzo and
Valentino Peluso and
Andrea Calimera and
Jun Zhou and
Xin Liu},
title = {Early bird sampling: {A} short-paths free error detection-correction
strategy for data-driven {VOS}},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203472},
doi = {10.1109/VLSI-SOC.2017.8203472},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RizzoPCZL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SaadehA17,
author = {Wala Saadeh and
Muhammad Awais Bin Altaf},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {A Wearable Neuro-Degenerative Diseases Classification System Using
Human Gait Dynamics},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {72--91},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_4},
doi = {10.1007/978-3-030-15663-3\_4},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SaadehA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SaadehAB17,
author = {Wala Saadeh and
Muhammad Awais Bin Altaf and
Saad Adnan Butt},
title = {A wearable neuro-degenerative diseases detection system based on gait
dynamics},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203488},
doi = {10.1109/VLSI-SOC.2017.8203488},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SaadehAB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SerunjogiLRS17,
author = {Solomon Michael Serunjogi and
Kai{-}Wei Lin and
Mahmoud Rasras and
Mihai Sanduleanu},
title = {Low-jitter, plain vanilla {CMOS} {CDR} with half-rate linear {PD}
and half rate frequency detector},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203490},
doi = {10.1109/VLSI-SOC.2017.8203490},
timestamp = {Sun, 22 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SerunjogiLRS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Shoufan17,
author = {Abdulhadi Shoufan},
title = {Continuous authentication of {UAV} flight command data using behaviometrics},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203494},
doi = {10.1109/VLSI-SOC.2017.8203494},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Shoufan17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SimIKR17,
author = {Joonseop Sim and
Mohsen Imani and
Yeseong Kim and
Tajana Rosing},
title = {Enabling efficient system design using vertical nanowire transistor
current mode logic},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203486},
doi = {10.1109/VLSI-SOC.2017.8203486},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SimIKR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SongJS17,
author = {Youngsoo Song and
Jinwook Jung and
Youngsoo Shin},
title = {Redundant Via insertion in {SADP} process with cut merging and optimization},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203478},
doi = {10.1109/VLSI-SOC.2017.8203478},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SongJS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SongWLLLLK17,
author = {Ling{-}Yen Song and
Chun Wang and
Chien{-}Nan Jimmy Liu and
Yun{-}Jing Lin and
Meng{-}Jung Lee and
Yu{-}Lan Lo and
Shu{-}Yi Kao},
title = {Non-regression approach for the behavioral model generator in mixed-signal
system verification},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--5},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203462},
doi = {10.1109/VLSI-SOC.2017.8203462},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SongWLLLLK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ThieleBL17,
author = {Matthias Thiele and
Steve Bigalke and
Jens Lienig},
title = {Exploring the use of the finite element method for electromigration
analysis in future physical design},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203466},
doi = {10.1109/VLSI-SOC.2017.8203466},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ThieleBL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ThieleBL17a,
author = {Matthias Thiele and
Steve Bigalke and
Jens Lienig},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Electromigration Analysis of {VLSI} Circuits Using the Finite Element
Method},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {133--152},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_7},
doi = {10.1007/978-3-030-15663-3\_7},
timestamp = {Fri, 17 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ThieleBL17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/UsamiKYMA17,
author = {Kimiyoshi Usami and
Shunsuke Kogure and
Yusuke Yoshida and
Ryo Magasaki and
Hideharu Amano},
title = {Level-shifter-less approach for multi-VDD design to use body bias
control in {FD-SOI}},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203473},
doi = {10.1109/VLSI-SOC.2017.8203473},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/UsamiKYMA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/UsamiKYMA17a,
author = {Kimiyoshi Usami and
Shunsuke Kogure and
Yusuke Yoshida and
Ryo Magasaki and
Hideharu Amano},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body
Bias Control in {FD-SOI}},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {1--21},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_1},
doi = {10.1007/978-3-030-15663-3\_1},
timestamp = {Fri, 17 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/UsamiKYMA17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WamserS17,
author = {Markus Stefan Wamser and
Georg Sigl},
title = {Pushing the limits further: Sub-atomic {AES}},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203470},
doi = {10.1109/VLSI-SOC.2017.8203470},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/WamserS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WamserS17a,
author = {Markus Stefan Wamser and
Georg Sigl},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Pushing the Limits Further: Sub-Atomic {AES}},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {220--239},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_11},
doi = {10.1007/978-3-030-15663-3\_11},
timestamp = {Fri, 17 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WamserS17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/XueMY17,
author = {Yuan Xue and
Abraham Mcllvaine and
Chengmo Yang},
title = {Power-aware and cost-efficient state encoding in non-volatile memory
based FPGAs},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203455},
doi = {10.1109/VLSI-SOC.2017.8203455},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/XueMY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YasinS17,
author = {Muhammad Yasin and
Ozgur Sinanoglu},
title = {Evolution of logic locking},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203496},
doi = {10.1109/VLSI-SOC.2017.8203496},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/YasinS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZengZT17,
author = {Yanhan Zeng and
Xin Zhang and
Hong{-}Zhou Tan},
title = {A 86 nA and sub-1 {V} {CMOS} voltage reference without resistors and
special devices},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--5},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203480},
doi = {10.1109/VLSI-SOC.2017.8203480},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZengZT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhaoZC17,
author = {Shuangxing Zhao and
Chenchang Zhan and
Guigang Cai},
title = {A 2{\texttimes}VDD-enabled fully-integrated low-dropout regulator
with fast transient response},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203475},
doi = {10.1109/VLSI-SOC.2017.8203475},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZhaoZC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhongBT17,
author = {Xiaopeng Zhong and
Amine Bermak and
Chi{-}Ying Tsui},
title = {A low-offset dynamic comparator with area-efficient and low-power
offset cancellation},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203481},
doi = {10.1109/VLSI-SOC.2017.8203481},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhongBT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Zorian17,
author = {Yervant Zorian},
title = {Keynotes: Robustness challenges in the internet of things},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--5},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203452},
doi = {10.1109/VLSI-SOC.2017.8203452},
timestamp = {Tue, 19 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Zorian17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2016socs,
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-67104-8},
doi = {10.1007/978-3-319-67104-8},
isbn = {978-3-319-67103-1},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2016socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2017soc,
title = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
publisher = {{IEEE}},
year = {2017},
url = {https://ieeexplore.ieee.org/xpl/conhome/8168766/proceeding},
isbn = {978-1-5386-2880-5},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2017soc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/0002K16,
author = {Yuan He and
Masaaki Kondo},
title = {Opportunistic circuit-switching for energy efficient on-chip networks},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753550},
doi = {10.1109/VLSI-SOC.2016.7753550},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/0002K16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AbbasT16,
author = {Syed Mohsin Abbas and
Chi{-}Ying Tsui},
title = {Low-latency approximate matrix inversion for high-throughput linear
pre-coders in massive {MIMO}},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--5},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753561},
doi = {10.1109/VLSI-SOC.2016.7753561},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AbbasT16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AbbasT16a,
author = {Syed Mohsin Abbas and
Chi{-}Ying Tsui},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Approximate Matrix Inversion for Linear Pre-coders in Massive {MIMO}},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {192--212},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_10},
doi = {10.1007/978-3-319-67104-8\_10},
timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AbbasT16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AdeltKMBKS16,
author = {Peer Adelt and
Bastian Koppelmann and
Wolfgang M{\"{u}}ller and
Markus Becker and
Bernd Kleinjohann and
Christoph Scheytt},
title = {Fast dynamic fault injection for virtual microcontroller platforms},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753545},
doi = {10.1109/VLSI-SOC.2016.7753545},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AdeltKMBKS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AgarwalK16,
author = {Sukarn Agarwal and
Hemangee K. Kapoor},
title = {Restricting writes for energy-efficient hybrid cache in multi-core
architectures},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753551},
doi = {10.1109/VLSI-SOC.2016.7753551},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AgarwalK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmagasakiNTIS16,
author = {Motoki Amagasaki and
Yuji Nakamura and
Takuya Teraoka and
Masahiro Iida and
Toshinori Sueyoshi},
title = {A novel soft error tolerant {FPGA} architecture},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753574},
doi = {10.1109/VLSI-SOC.2016.7753574},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AmagasakiNTIS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmraniDK16,
author = {Elad Amrani and
Avishay Drori and
Shahar Kvatinsky},
title = {Logic design with unipolar memristors},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--5},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753564},
doi = {10.1109/VLSI-SOC.2016.7753564},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AmraniDK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BanerjeeMB16,
author = {Sabyasachee Banerjee and
Subhashis Majumder and
Bhargab B. Bhattacharya},
title = {Power-aware test optimization for core-based 3D-SOCs under TSV-constraints},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753537},
doi = {10.1109/VLSI-SOC.2016.7753537},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BanerjeeMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernardiBNGSV16,
author = {Paolo Bernardi and
Alberto Bosio and
Giorgio Di Natale and
Andrea Guerriero and
Ernesto S{\'{a}}nchez and
Federico Venini},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Improving Stress Quality for SoC Using Faster-than-At-Speed Execution
of Functional Programs},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {130--151},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_7},
doi = {10.1007/978-3-319-67104-8\_7},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BernardiBNGSV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernardiBNGV16,
author = {Paolo Bernardi and
Alberto Bosio and
Giorgio Di Natale and
Andrea Guerriero and
Federico Venini},
title = {Faster-than-at-speed execution of functional programs: An experimental
analysis},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753581},
doi = {10.1109/VLSI-SOC.2016.7753581},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BernardiBNGV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernardiniES16,
author = {Alessandro Bernardini and
Wolfgang Ecker and
Ulf Schlichtmann},
title = {Efficient handling of the fault space in functional safety analysis
utilizing formal methods},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--7},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753546},
doi = {10.1109/VLSI-SOC.2016.7753546},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BernardiniES16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernasconiCFT16,
author = {Anna Bernasconi and
Valentina Ciriani and
Luca Frontini and
Gabriella Trucco},
title = {Synthesis on switching lattices of Dimension-reducible Boolean functions},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753577},
doi = {10.1109/VLSI-SOC.2016.7753577},
timestamp = {Sat, 23 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BernasconiCFT16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BhattacharjeeMC16,
author = {Debjyoti Bhattacharjee and
Farhad Merchant and
Anupam Chattopadhyay},
title = {Enabling in-memory computation of binary {BLAS} using ReRAM crossbar
arrays},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753568},
doi = {10.1109/VLSI-SOC.2016.7753568},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BhattacharjeeMC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChakrabortyK16,
author = {Shounak Chakraborty and
Hemangee K. Kapoor},
title = {Static energy reduction by performance linked dynamic cache resizing},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753549},
doi = {10.1109/VLSI-SOC.2016.7753549},
timestamp = {Wed, 30 Jan 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChakrabortyK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChenMP16,
author = {Yukai Chen and
Enrico Macii and
Massimo Poncino},
title = {Frequency domain characterization of batteries for the design of energy
storage subsystems},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753548},
doi = {10.1109/VLSI-SOC.2016.7753548},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChenMP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DuS16,
author = {Boyang Du and
Luca Sterpone},
title = {An FPGA-based testing platform for the validation of automotive powertrain
{ECU}},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--7},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753553},
doi = {10.1109/VLSI-SOC.2016.7753553},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DuS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EckerS16,
author = {Wolfgang Ecker and
Johannes Schreiner},
title = {Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler
and more efficient hardware generators},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753576},
doi = {10.1109/VLSI-SOC.2016.7753576},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/EckerS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FrenkelLB16,
author = {Charlotte Frenkel and
Jean{-}Didier Legat and
David Bol},
title = {Comparative analysis of redundancy schemes for soft-error detection
in low-cost space applications},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753573},
doi = {10.1109/VLSI-SOC.2016.7753573},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FrenkelLB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GundlaC16,
author = {Abhiram Reddy Gundla and
Tom Chen},
title = {An efficient multi channel, 425{\(\mathrm{\mu}\)}W {QPSK} transmitter
with tuning for process variation in the Medical Implantable Communications
Service {(MICS)} band of 402-405MHz},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--5},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753540},
doi = {10.1109/VLSI-SOC.2016.7753540},
timestamp = {Mon, 02 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GundlaC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HashemiNN16,
author = {Seyedeh Hanieh Hashemi and
Reza Namazian and
Zainalabedin Navabi},
title = {Optimistic clock adjustment for preventing Better-than-worst-case
violations},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753571},
doi = {10.1109/VLSI-SOC.2016.7753571},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HashemiNN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HemmatKAP16,
author = {Maede Hemmat and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {Hybrid {TFET-MOSFET} circuits: An approach to design reliable ultra-low
power circuits in the presence of process variation},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753578},
doi = {10.1109/VLSI-SOC.2016.7753578},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HemmatKAP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HemmatKAP16a,
author = {Maedeh Hemmat and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Robust Hybrid {TFET-MOSFET} Circuits in Presence of Process Variations
and Soft Errors},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {41--59},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_3},
doi = {10.1007/978-3-319-67104-8\_3},
timestamp = {Tue, 05 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HemmatKAP16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HoangPDP16,
author = {Van{-}Phuc Hoang and
Thi{-}Thanh{-}Dung Phan and
Van{-}Lan Dao and
Cong{-}Kha Pham},
title = {A compact, ultra-low power {AES-CCM} {IP} core for wireless body area
networks},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753566},
doi = {10.1109/VLSI-SOC.2016.7753566},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HoangPDP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JayakrishnanCK16,
author = {Mini Jayakrishnan and
Alan Chang and
Tae{-}Hyoung Kim},
title = {Power and area efficient clock stretching and critical path reshaping
for error resilience},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753570},
doi = {10.1109/VLSI-SOC.2016.7753570},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JayakrishnanCK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimCLR16,
author = {Jaehyun Kim and
Kiyoung Choi and
Sang{-}Heon Lee and
Soojung Ryu},
title = {Dynamic clock synchronization scheme between voltage domains in multi-core
architecture},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753536},
doi = {10.1109/VLSI-SOC.2016.7753536},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimCLR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KoserKS16,
author = {Erol Koser and
Sebastian Krosche and
Walter Stechele},
title = {Integrated Soft Error Resilience and Self-Test},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753569},
doi = {10.1109/VLSI-SOC.2016.7753569},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KoserKS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KrafczykRF16,
author = {Niklas Krafczyk and
Heinz Riener and
G{\"{o}}rschwin Fey},
title = {{WCET} overapproximation for software in the context of a Cyber-Physical
System},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753559},
doi = {10.1109/VLSI-SOC.2016.7753559},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KrafczykRF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LarimiKAM16,
author = {Seyed Saber Nabavi Larimi and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Hamid Mahmoodi},
title = {Power and energy reduction of racetrack-based caches by exploiting
shared shift operations},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753563},
doi = {10.1109/VLSI-SOC.2016.7753563},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LarimiKAM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiHC16,
author = {Yanzhe Li and
Kai Huang and
Luc Claesen},
title = {SoC oriented real-time high-quality stereo vision system},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753558},
doi = {10.1109/VLSI-SOC.2016.7753558},
timestamp = {Wed, 01 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LiHC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiHC16a,
author = {Yanzhe Li and
Kai Huang and
Luc Claesen},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture
Design in {FPGA}},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {213--232},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_11},
doi = {10.1007/978-3-319-67104-8\_11},
timestamp = {Wed, 01 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LiHC16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiMGSN16,
author = {Xueqing Li and
Kaisheng Ma and
Sumitha George and
John Sampson and
Vijaykrishnan Narayanan},
title = {Enabling Internet-of-Things: Opportunities brought by emerging devices,
circuits, and architectures},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753542},
doi = {10.1109/VLSI-SOC.2016.7753542},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LiMGSN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiMGSN16a,
author = {Xueqing Li and
Kaisheng Ma and
Sumitha George and
John Sampson and
Vijaykrishnan Narayanan},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Enabling Internet-of-Things with Opportunities Brought by Emerging
Devices, Circuits and Architectures},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {1--23},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_1},
doi = {10.1007/978-3-319-67104-8\_1},
timestamp = {Tue, 05 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LiMGSN16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LinSK16,
author = {Minghao Lin and
Heming Sun and
Shinji Kimura},
title = {Power-efficient and slew-aware three dimensional gated clock tree
synthesis},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753535},
doi = {10.1109/VLSI-SOC.2016.7753535},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LinSK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ManoranjanSGS16,
author = {Jotham Vaddaboina Manoranjan and
Solomon Surya Tej Mano Sajjan and
Vivek B. Gujari and
Kenneth S. Stevens},
title = {Design of a multi-style and multi-frequency {FPGA}},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753538},
doi = {10.1109/VLSI-SOC.2016.7753538},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ManoranjanSGS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuzaffarSE16,
author = {Shahzad Muzaffar and
Numan Saeed and
Ibrahim M. Elfadel},
title = {Automatic protocol configuration in single-channel low-power dynamic
signaling for IoT devices},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753560},
doi = {10.1109/VLSI-SOC.2016.7753560},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MuzaffarSE16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NakadaHNUHS16,
author = {Takashi Nakada and
Tomoki Hatanaka and
Hiroshi Nakamura and
Hiroshi Ueki and
Masanori Hayashikoshi and
Toru Shimizu},
title = {An adaptive energy-efficient task scheduling under execution time
variation based on statistical analysis},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--7},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753565},
doi = {10.1109/VLSI-SOC.2016.7753565},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NakadaHNUHS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NasserianPM16,
author = {Mahshid Nasserian and
Ali Peiravi and
Farshad Moradi},
title = {A 1.62 {\(\mathrm{\mu}\)}W 8-channel ultra-high input impedance {EEG}
amplifier for dry and non-contact biopotential recording applications},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753539},
doi = {10.1109/VLSI-SOC.2016.7753539},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NasserianPM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NocuaVB0C16,
author = {Alejandro Nocua and
Arnaud Virazel and
Alberto Bosio and
Patrick Girard and
Cyril Chevalier},
title = {A Hybrid Power Estimation Technique to improve {IP} power models quality},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753582},
doi = {10.1109/VLSI-SOC.2016.7753582},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NocuaVB0C16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ObrebskiKZZ16,
author = {Dariusz Obrebski and
Cezary Kolacinski and
Michal Zbiec and
Przemyslaw Zagrajek},
title = {The multi-channel small signal readout system for THz spectroscopy
and imaging applications},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753562},
doi = {10.1109/VLSI-SOC.2016.7753562},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ObrebskiKZZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PelusoCMA16,
author = {Valentino Peluso and
Andrea Calimera and
Enrico Macii and
Massimo Alioto},
title = {Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor
SoCs},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753580},
doi = {10.1109/VLSI-SOC.2016.7753580},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PelusoCMA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PelusoRCMA16,
author = {Valentino Peluso and
Roberto Giorgio Rizzo and
Andrea Calimera and
Enrico Macii and
Massimo Alioto},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Beyond Ideal {DVFS} Through Ultra-Fine Grain Vdd-Hopping},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {152--172},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_8},
doi = {10.1007/978-3-319-67104-8\_8},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PelusoRCMA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PiccolboniP16,
author = {Luca Piccolboni and
Graziano Pravadelli},
title = {Stimuli generation through invariant mining for black-box verification},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753557},
doi = {10.1109/VLSI-SOC.2016.7753557},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PiccolboniP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PlassanPMRSB16,
author = {Guillaume Plassan and
Hans{-}J{\"{o}}rg Peter and
Katell Morin{-}Allory and
Fahim Rahim and
Shaker Sarwary and
Dominique Borrione},
title = {Conclusively verifying clock-domain crossings in very large hardware
designs},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753555},
doi = {10.1109/VLSI-SOC.2016.7753555},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PlassanPMRSB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PlassanPMSB16,
author = {Guillaume Plassan and
Hans{-}J{\"{o}}rg Peter and
Katell Morin{-}Allory and
Shaker Sarwary and
Dominique Borrione},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Improving the Efficiency of Formal Verification: The Case of Clock-Domain
Crossings},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {108--129},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_6},
doi = {10.1007/978-3-319-67104-8\_6},
timestamp = {Tue, 05 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PlassanPMSB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RaikOHC16,
author = {Jaan Raik and
Ian O'Connor and
Thomas Hollstein and
Krishnendu Chakrabarty},
title = {Foreword},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753411},
doi = {10.1109/VLSI-SOC.2016.7753411},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RaikOHC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RathSEE16,
author = {Alexander W. Rath and
Sebastian Simon and
Volkan Esen and
Wolfgang Ecker},
title = {Automatically comparing analog behavior using Earth Mover's Distance},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--8},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753556},
doi = {10.1109/VLSI-SOC.2016.7753556},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RathSEE16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RathSEE16a,
author = {Alexander W. Rath and
Sebastian Simon and
Volkan Esen and
Wolfgang Ecker},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Earth Mover's Distance as a Comparison Metric for Analog Behavior},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {173--191},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_9},
doi = {10.1007/978-3-319-67104-8\_9},
timestamp = {Tue, 05 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RathSEE16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchreinerE16,
author = {Johannes Schreiner and
Wolfgang Ecker},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Digital Hardware Design Based on Metamodels and Model Transformations},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {83--107},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_5},
doi = {10.1007/978-3-319-67104-8\_5},
timestamp = {Tue, 05 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SchreinerE16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SuWLCL16,
author = {Fang Su and
Zhibo Wang and
Jinyang Li and
Meng{-}Fan Chang and
Yongpan Liu},
title = {Design of nonvolatile processors and applications},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753543},
doi = {10.1109/VLSI-SOC.2016.7753543},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SuWLCL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TabacaruCEKN16,
author = {Bogdan{-}Andrei Tabacaru and
Moomen Chaari and
Wolfgang Ecker and
Thomas Kruse and
Cristiano Novello},
title = {Speeding up safety verification by fault abstraction and simulation
to transaction level},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753547},
doi = {10.1109/VLSI-SOC.2016.7753547},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TabacaruCEKN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TenaceCMP16,
author = {Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
title = {Multi-function logic synthesis of silicon and beyond-silicon ultra-low
power pass-gates circuits},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753575},
doi = {10.1109/VLSI-SOC.2016.7753575},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TenaceCMP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TenaceCMP16a,
author = {Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic
Circuits},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {60--82},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_4},
doi = {10.1007/978-3-319-67104-8\_4},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TenaceCMP16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TohidiMHM16,
author = {Mohammad Tohidi and
Jens Kargaard Madsen and
Martijn J. R. Heck and
Farshad Moradi},
title = {A low-power analog front-end neural acquisition design for seizure
detection},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753541},
doi = {10.1109/VLSI-SOC.2016.7753541},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TohidiMHM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TraiolaBMB16,
author = {Marcello Traiola and
Mario Barbareschi and
Antonino Mazzeo and
Alberto Bosio},
title = {XbarGen: {A} memristor based boolean logic synthesis tool},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753567},
doi = {10.1109/VLSI-SOC.2016.7753567},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TraiolaBMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WaldADK16,
author = {Nimrod Wald and
Elad Amrani and
Avishay Drori and
Shahar Kvatinsky},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Logic with Unipolar Memristors - Circuits and Design Methodology},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {24--40},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_2},
doi = {10.1007/978-3-319-67104-8\_2},
timestamp = {Tue, 05 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WaldADK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WuJ16,
author = {Lei Wu and
Ching{-}Chuen Jong},
title = {A {VLSI} architecture for real-time gradient guided image filtering},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753554},
doi = {10.1109/VLSI-SOC.2016.7753554},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WuJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YasunagaYY16,
author = {Moritoshi Yasunaga and
Naoki Yokoshima and
Ikuo Yoshihara},
title = {A passive equalizer and its design methodology for global interconnects
in VLSIs},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753552},
doi = {10.1109/VLSI-SOC.2016.7753552},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/YasunagaYY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZambranoK16,
author = {Andreina Zambrano and
Hans G. Kerkhoff},
title = {Online digital compensation Method for {AMR} sensors},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753579},
doi = {10.1109/VLSI-SOC.2016.7753579},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZambranoK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhaoKAZ16,
author = {Yi Zhao and
S. Saqib Khursheed and
Bashir M. Al{-}Hashimi and
Zhiwen Zhao},
title = {Co-optimization of fault tolerance, wirelength and temperature mitigation
in TSV-based 3D ICs},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753572},
doi = {10.1109/VLSI-SOC.2016.7753572},
timestamp = {Fri, 02 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhaoKAZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhaoQXHX16,
author = {Mengying Zhao and
Keni Qiu and
Yuan Xie and
Jingtong Hu and
Chun Jason Xue},
title = {Redesigning software and systems for non-volatile processors on self-powered
devices},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753544},
doi = {10.1109/VLSI-SOC.2016.7753544},
timestamp = {Sat, 20 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZhaoQXHX16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2015socs,
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-46097-0},
doi = {10.1007/978-3-319-46097-0},
isbn = {978-3-319-46096-3},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2015socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2016soc,
title = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/xpl/conhome/7744451/proceeding},
isbn = {978-1-5090-3561-8},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2016soc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AbbasizadehRL15,
author = {Hamed Abbasizadeh and
Behnam Samadpoor Rikan and
Kang{-}Yoon Lee},
title = {A fully on-chip 25MHz PVT-compensation {CMOS} Relaxation Oscillator},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {241--245},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314423},
doi = {10.1109/VLSI-SOC.2015.7314423},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AbbasizadehRL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AbdessaiedSDD15,
author = {Nabila Abdessaied and
Mathias Soeken and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Reversible circuit rewriting with simulated annealing},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {286--291},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314431},
doi = {10.1109/VLSI-SOC.2015.7314431},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AbdessaiedSDD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmagasakiTZIKS15,
author = {Motoki Amagasaki and
Yuto Takeuchi and
Qian Zhao and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Architecture exploration of 3D {FPGA} to minimize internal layer connection},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {110--115},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314401},
doi = {10.1109/VLSI-SOC.2015.7314401},
timestamp = {Wed, 18 Oct 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AmagasakiTZIKS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmaravatiCR15,
author = {Anvesha Amaravati and
Manan Chugh and
Arijit Raychowdhury},
title = {A time interleaved {DAC} sharing {SAR} Pipeline {ADC} for ultra-low
power camera front ends},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {231--236},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314421},
doi = {10.1109/VLSI-SOC.2015.7314421},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AmaravatiCR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmaravatiCR15a,
author = {Anvesha Amaravati and
Manan Chugh and
Arijit Raychowdhury},
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {A {SAR} Pipeline {ADC} Embedding Time Interleaved {DAC} Sharing for
Ultra-low Power Camera Front Ends},
booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
pages = {131--149},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-46097-0\_7},
doi = {10.1007/978-3-319-46097-0\_7},
timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AmaravatiCR15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BashizadeS15,
author = {Ramin Bashizade and
Hamid Sarbazi{-}Azad},
title = {Traffic-aware buffer reconfiguration in on-chip networks},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {201--206},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314416},
doi = {10.1109/VLSI-SOC.2015.7314416},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BashizadeS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BoccaSSMMP15,
author = {Alberto Bocca and
Alessandro Sassone and
Donghwa Shin and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {An equation-based battery cycle life model for various battery chemistries},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {57--62},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314392},
doi = {10.1109/VLSI-SOC.2015.7314392},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BoccaSSMMP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BoccaSSMMP15a,
author = {Alberto Bocca and
Alessandro Sassone and
Donghwa Shin and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {A Temperature-Aware Battery Cycle Life Model for Different Battery
Chemistries},
booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
pages = {109--130},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-46097-0\_6},
doi = {10.1007/978-3-319-46097-0\_6},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BoccaSSMMP15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BoguslawskiSHST15,
author = {Bartosz Boguslawski and
Hossam Sarhan and
Fr{\'{e}}d{\'{e}}ric Heitzmann and
Fabrice Seguin and
S{\'{e}}bastien Thuries and
Olivier Billoint and
Fabien Clermidy},
title = {Compact interconnect approach for networks of neural cliques using
3D technology},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {116--121},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314402},
doi = {10.1109/VLSI-SOC.2015.7314402},
timestamp = {Wed, 12 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BoguslawskiSHST15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BossuetBF15,
author = {Lilian Bossuet and
Pierre Bayon and
Viktor Fischer},
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {Electromagnetic Transmission of Intellectual Property Data to Protect
{FPGA} Designs},
booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
pages = {150--169},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-46097-0\_8},
doi = {10.1007/978-3-319-46097-0\_8},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BossuetBF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BossuetFB15,
author = {Lilian Bossuet and
Viktor Fischer and
Pierre Bayon},
title = {Contactless transmission of intellectual property data to protect
{FPGA} designs},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {19--24},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314385},
doi = {10.1109/VLSI-SOC.2015.7314385},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BossuetFB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChampacRG15,
author = {V{\'{\i}}ctor H. Champac and
Alejandra Nicte{-}ha Reyes and
Andres F. Gomez},
title = {Circuit performance optimization for local intra-die process variations
using a gate selection metric},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {165--170},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314410},
doi = {10.1109/VLSI-SOC.2015.7314410},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChampacRG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChangC15,
author = {Naehyuck Chang and
Kiyoung Choi},
title = {Message from the general chairs},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {VIII},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314376},
doi = {10.1109/VLSI-SOC.2015.7314376},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChangC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChenR15,
author = {Ying{-}Jung Chen and
Shanq{-}Jang Ruan},
title = {A cluster-based reliability- and thermal-aware 3D floorplanning using
redundant STSVs},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {349--354},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314442},
doi = {10.1109/VLSI-SOC.2015.7314442},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChenR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChoudharyGMF15,
author = {Shridhar Choudhary and
Amir Masoud Gharehbaghi and
Takeshi Matsumoto and
Masahiro Fujita},
title = {Trace signal selection methods for post silicon debugging},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {258--263},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314426},
doi = {10.1109/VLSI-SOC.2015.7314426},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChoudharyGMF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DaneseFGP15,
author = {Alessandro Danese and
Francesca Filini and
Tara Ghasempouri and
Graziano Pravadelli},
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {Automatic Generation and Qualification of Assertions on Control Signals:
{A} Time Window-Based Approach},
booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
pages = {193--221},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-46097-0\_10},
doi = {10.1007/978-3-319-46097-0\_10},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DaneseFGP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DaneseFP15,
author = {Alessandro Danese and
Francesca Filini and
Graziano Pravadelli},
title = {A time-window based approach for dynamic assertions mining on control
signals},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {246--251},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314424},
doi = {10.1109/VLSI-SOC.2015.7314424},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/DaneseFP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FlachMFPBJR15,
author = {Guilherme Flach and
Jucemar Monteiro and
Mateus Foga{\c{c}}a and
Julia Casarin Puget and
Paulo F. Butzen and
Marcelo O. Johann and
Ricardo Augusto da Luz Reis},
title = {An Incremental Timing-Driven flow using quadratic formulation for
detailed placement},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {1--6},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314382},
doi = {10.1109/VLSI-SOC.2015.7314382},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FlachMFPBJR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Fujita15,
author = {Masahiro Fujita},
title = {Analysis and testing on delays with two time frames},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {13--18},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314384},
doi = {10.1109/VLSI-SOC.2015.7314384},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Fujita15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Fujita15a,
author = {Masahiro Fujita},
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {Delay Testing Based on Multiple Faulty Behaviors},
booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
pages = {87--108},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-46097-0\_5},
doi = {10.1007/978-3-319-46097-0\_5},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Fujita15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GautschiTPBSFBA15,
author = {Michael Gautschi and
Andreas Traber and
Antonio Pullini and
Luca Benini and
Michele Scandale and
Alessandro Di Federico and
Michele Beretta and
Giovanni Agosta},
title = {Tailoring instruction-set extensions for an ultra-low power tightly-coupled
cluster of OpenRISC cores},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {25--30},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314386},
doi = {10.1109/VLSI-SOC.2015.7314386},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GautschiTPBSFBA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GharehbaghiF15,
author = {Amir Masoud Gharehbaghi and
Masahiro Fujita},
title = {Efficient signature-based sub-circuit matching},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {280--285},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314430},
doi = {10.1109/VLSI-SOC.2015.7314430},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GharehbaghiF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GhasempouriP15,
author = {Tara Ghasempouri and
Graziano Pravadelli},
title = {On the estimation of assertion interestingness},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {325--330},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314438},
doi = {10.1109/VLSI-SOC.2015.7314438},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GhasempouriP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GomezC15,
author = {Andres F. Gomez and
V{\'{\i}}ctor H. Champac},
title = {A new sizing approach for lifetime improvement of nanoscale digital
circuits due to {BTI} aging},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {297--302},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314433},
doi = {10.1109/VLSI-SOC.2015.7314433},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GomezC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Guo0W15,
author = {Jun Guo and
Peng Liu and
Weidong Wang},
title = {Physical-based modeling and fast simulation of wireline links},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {252--257},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314425},
doi = {10.1109/VLSI-SOC.2015.7314425},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Guo0W15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HuangCM15,
author = {Yuanwen Huang and
Anupam Chattopadhyay and
Prabhat Mishra},
title = {Trace Buffer Attack: Security versus observability study in post-silicon
debug},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {355--360},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314443},
doi = {10.1109/VLSI-SOC.2015.7314443},
timestamp = {Mon, 18 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HuangCM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/IturbeKOYBHC15,
author = {Xabier Iturbe and
Didier Keymeulen and
Emre Ozer and
Patrick Yiu and
Daniel Berisford and
Kevin P. Hand and
Robert Carlson},
title = {An integrated SoC for science data processing in next-generation space
flight instruments avionics},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {134--141},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314405},
doi = {10.1109/VLSI-SOC.2015.7314405},
timestamp = {Wed, 11 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/IturbeKOYBHC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/IturbeKYBCHO15,
author = {Xabier Iturbe and
Didier Keymeulen and
Patrick Yiu and
Daniel Berisford and
Robert Carlson and
Kevin P. Hand and
Emre Ozer},
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {On the Use of System-on-Chip Technology in Next-Generation Instruments
Avionics for Space Exploration},
booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
pages = {1--22},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-46097-0\_1},
doi = {10.1007/978-3-319-46097-0\_1},
timestamp = {Wed, 11 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/IturbeKYBCHO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JaiswalS15,
author = {Manish Kumar Jaiswal and
Hayden Kwok{-}Hay So},
title = {Dual-mode double precision / two-parallel single precision floating
point multiplier architecture},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {213--218},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314418},
doi = {10.1109/VLSI-SOC.2015.7314418},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JaiswalS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JayakrishnanCGH15,
author = {Mini Jayakrishnan and
Alan Chang and
Jos{\'{e}} Pineda de Gyvez and
Tae{-}Hyoung Kim},
title = {Slack-aware timing margin redistribution technique utilizing error
avoidance flip-flops and time borrowing},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {159--164},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314409},
doi = {10.1109/VLSI-SOC.2015.7314409},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JayakrishnanCGH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JoseAS15,
author = {John Jose and
Joe Augustine and
Sijin Sebastian},
title = {Dynamic migratory selection strategy for adaptive routing in mesh
NoCs},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {343--348},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314441},
doi = {10.1109/VLSI-SOC.2015.7314441},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JoseAS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KhanKBK15,
author = {Asim Khan and
Muhammad Umar Karim Khan and
Muhammad Bilal and
Chong{-}Min Kyung},
title = {Hardware architecture and optimization of sliding window based pedestrian
detection on {FPGA} for high resolution images by varying local features},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {142--148},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314406},
doi = {10.1109/VLSI-SOC.2015.7314406},
timestamp = {Fri, 10 Nov 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KhanKBK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KhanKBK15a,
author = {Asim Khan and
Muhammad Umar Karim Khan and
Muhammad Bilal and
Chong{-}Min Kyung},
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {A Hardware Accelerator for Real Time Sliding Window Based Pedestrian
Detection on High Resolution Images},
booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
pages = {46--66},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-46097-0\_3},
doi = {10.1007/978-3-319-46097-0\_3},
timestamp = {Fri, 10 Nov 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KhanKBK15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KhatibACASF15,
author = {Chadi Al Khatib and
Claire Aupetit and
Cyril Chevalier and
Chouki Aktouf and
Gilles Sicard and
Laurent Fesquet},
title = {A generic clock controller for low power systems: Experimentation
on an {AXI} bus},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {307--312},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314435},
doi = {10.1109/VLSI-SOC.2015.7314435},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KhatibACASF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimASC15,
author = {Namhyung Kim and
Junwhan Ahn and
Woong Seo and
Kiyoung Choi},
title = {Energy-efficient exclusive last-level hybrid caches consisting of
{SRAM} and {STT-RAM}},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {183--188},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314413},
doi = {10.1109/VLSI-SOC.2015.7314413},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimASC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimCL15,
author = {Gain Kim and
Raffaele Capoccia and
Yusuf Leblebici},
title = {Design optimization of polyphase digital down converters for extremely
high frequency wireless communications},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {207--212},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314417},
doi = {10.1109/VLSI-SOC.2015.7314417},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimCL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimFB15,
author = {Matthew M. Kim and
Karl M. Fant and
Paul Beckett},
title = {Design of asynchronous {RISC} {CPU} register-file Write-Back queue},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {31--36},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314387},
doi = {10.1109/VLSI-SOC.2015.7314387},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimFB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimKKPC15,
author = {S. E. Kim and
T. W. Kang and
S. W. Kang and
K. H. Park and
M. A. Chung},
title = {High-efficiency voltage regulation stage in energy harvesting systems},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {237--240},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314422},
doi = {10.1109/VLSI-SOC.2015.7314422},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimKKPC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeKBE15,
author = {Jae{-}Jin Lee and
Chan Kim and
Kyungjin Byun and
Nak{-}Woong Eum},
title = {Virtual prototype based on Aldebarn {CPU} core},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {303--306},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314434},
doi = {10.1109/VLSI-SOC.2015.7314434},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeKBE15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeKKK15,
author = {Jaemin Lee and
Seungwon Kim and
Youngmin Kim and
Seokhyeong Kang},
title = {An optimal operating point by using error monitoring circuits with
an error-resilient technique},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {69--73},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314394},
doi = {10.1109/VLSI-SOC.2015.7314394},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeKKK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiLWYYYL15,
author = {Zheng Li and
Chenchen Liu and
Yandan Wang and
Bonan Yan and
Chaofei Yang and
Jianlei Yang and
Hai Li},
title = {An overview on memristor crossabr based neuromorphic circuit and architecture},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {52--56},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314391},
doi = {10.1109/VLSI-SOC.2015.7314391},
timestamp = {Sun, 05 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LiLWYYYL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiouHCC15,
author = {Jing{-}Jia Liou and
Meng{-}Ta Hsieh and
Jun{-}Fei Cherng and
Harry H. Chen},
title = {Cost reduction of system-level tests with stressed structural tests
and {SVM}},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {177--182},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314412},
doi = {10.1109/VLSI-SOC.2015.7314412},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LiouHCC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LowSZ15,
author = {Qiong Wei Low and
Liter Siek and
Mi Zhou},
title = {A high efficiency rectifier for inductively power transfer application},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {270--273},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314428},
doi = {10.1109/VLSI-SOC.2015.7314428},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LowSZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MackoJC15,
author = {Dominik Macko and
Katar{\'{\i}}na Jelemensk{\'{a}} and
Pavel Cic{\'{a}}k},
title = {Power-management high-level synthesis},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {63--68},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314393},
doi = {10.1109/VLSI-SOC.2015.7314393},
timestamp = {Tue, 13 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MackoJC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuzaffarE15,
author = {Shahzad Muzaffar and
Ibrahim M. Elfadel},
title = {Timing and robustness analysis of Pulsed-Index protocols for single-channel
IoT communications},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {225--230},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314420},
doi = {10.1109/VLSI-SOC.2015.7314420},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MuzaffarE15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Nicolas-Nicolaz15,
author = {Pierre Nicolas{-}Nicolaz and
Kiyoung Choi},
title = {Dynamic error tracking and supply voltage adjustment for low power},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {74--79},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314395},
doi = {10.1109/VLSI-SOC.2015.7314395},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Nicolas-Nicolaz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PandiyanM15,
author = {Manikandan Pandiyan and
Geetha Mani},
title = {Embedded low power analog {CMOS} Fuzzy Logic Controller chip for industrial
applications},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {43--48},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314389},
doi = {10.1109/VLSI-SOC.2015.7314389},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PandiyanM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PandiyanM15a,
author = {Manikandan Pandiyan and
Geetha Mani},
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {Wearable {ECG} SoC for Wireless Body Area Networks: Implementation
with Fuzzy Decision Making Chip},
booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
pages = {67--86},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-46097-0\_4},
doi = {10.1007/978-3-319-46097-0\_4},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PandiyanM15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PandiyanMJS15,
author = {Manikandan Pandiyan and
Geetha Mani and
Jovitha Jerome and
Natarajan S.},
title = {Integrating wearable low power {CMOS} {ECG} acquisition SoC with decision
making system for {WSBN} applications},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {154--158},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314408},
doi = {10.1109/VLSI-SOC.2015.7314408},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PandiyanMJS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParkAPY15,
author = {Hyunsun Park and
Junwhan Ahn and
Eunhyeok Park and
Sungjoo Yoo},
title = {Locality-aware vertex scheduling for GPU-based graph computation},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {195--200},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314415},
doi = {10.1109/VLSI-SOC.2015.7314415},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ParkAPY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParkBE15,
author = {Seongmo Park and
Kyungjin Byun and
Nak{-}Woong Eum},
title = {A hybrid embedded compression codec engine for ultra {HD} video application},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {292--296},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314432},
doi = {10.1109/VLSI-SOC.2015.7314432},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ParkBE15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParkKYP15,
author = {Hyunsun Park and
Chanha Kim and
Sungjoo Yoo and
Chanik Park},
title = {Filtering dirty data in {DRAM} to reduce {PRAM} writes},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {319--324},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314437},
doi = {10.1109/VLSI-SOC.2015.7314437},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ParkKYP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParkLKK15,
author = {Hyungil Park and
Ingi Lim and
Sungweon Kang and
Whan{-}woo Kim},
title = {10Mbps human body communication SoC for {BAN}},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {149--153},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314407},
doi = {10.1109/VLSI-SOC.2015.7314407},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ParkLKK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParkSL15,
author = {Jaehyun Park and
Donghwa Shin and
Hyung Gyu Lee},
title = {Prefetch-based dynamic row buffer management for {LPDDR2-NVM} devices},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {98--103},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314399},
doi = {10.1109/VLSI-SOC.2015.7314399},
timestamp = {Mon, 19 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ParkSL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParkSL15a,
author = {Jaehyun Park and
Donghwa Shin and
Hyung Gyu Lee},
title = {Design space exploration of row buffer architecture for phase change
memory with {LPDDR2-NVM} interface},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {104--109},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314400},
doi = {10.1109/VLSI-SOC.2015.7314400},
timestamp = {Mon, 19 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ParkSL15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Parthasarathy15,
author = {Ananthanarayanan Parthasarathy},
title = {Design and analysis of search algorithms for lower power consumption
and faster convergence of {DAC} input of {SAR-ADC} in 65nm {CMOS}},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {274--279},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314429},
doi = {10.1109/VLSI-SOC.2015.7314429},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Parthasarathy15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PaulBS15,
author = {Sudipta Paul and
Pritha Banerjee and
Susmita Sur{-}Kolay},
title = {Flare reduction in {EUV} Lithography by perturbation of wire segments},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {7--12},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314383},
doi = {10.1109/VLSI-SOC.2015.7314383},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PaulBS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/QuiringOB15,
author = {Artur Quiring and
Markus Olbrich and
Erich Barke},
title = {Fast global interconnnect driven 3D floorplanning},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {313--318},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314436},
doi = {10.1109/VLSI-SOC.2015.7314436},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/QuiringOB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RakossySALC15,
author = {Zolt{\'{a}}n Endre R{\'{a}}kossy and
Dominik Stengele and
Gerd Ascheid and
Rainer Leupers and
Anupam Chattopadhyay},
title = {Exploiting scalable {CGRA} mapping of {LU} for energy efficiency using
the Layers architecture},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {337--342},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314440},
doi = {10.1109/VLSI-SOC.2015.7314440},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RakossySALC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RoyMGR15,
author = {Surajit Kumar Roy and
Supriyo Mandal and
Chandan Giri and
Hafizur Rahaman},
title = {A thermal estimation model for 3D {IC} using liquid cooled microchannels
and thermal TSVs},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {122--127},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314403},
doi = {10.1109/VLSI-SOC.2015.7314403},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RoyMGR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SaeedMAS15,
author = {Samah Mohamed Saeed and
Bodhisatwa Mazumdar and
Sk Subidh Ali and
Ozgur Sinanoglu},
title = {Timing attack on {NEMS} relay based design of {AES}},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {264--269},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314427},
doi = {10.1109/VLSI-SOC.2015.7314427},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SaeedMAS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SeoS15,
author = {Jae{-}sun Seo and
Mingoo Seok},
title = {Digital {CMOS} neuromorphic processor design featuring unsupervised
online learning},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {49--51},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314390},
doi = {10.1109/VLSI-SOC.2015.7314390},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SeoS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SeyidBL15,
author = {Kerem Seyid and
Sebastien Blanc and
Yusuf Leblebici},
title = {Hardware implementation of real-time multiple frame super-resolution},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {219--224},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314419},
doi = {10.1109/VLSI-SOC.2015.7314419},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SeyidBL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ShimS15,
author = {Seongbo Shim and
Youngsoo Shin},
title = {Physical design and mask optimization for directed self-assembly lithography
{(DSAL)}},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {80--85},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314396},
doi = {10.1109/VLSI-SOC.2015.7314396},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ShimS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ShinT15,
author = {Youngsoo Shin and
Chi{-}Ying Tsui},
title = {Message from the technical program chairs},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {IX},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314377},
doi = {10.1109/VLSI-SOC.2015.7314377},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ShinT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SrinivasanMB15,
author = {Manikantan Srinivasan and
C. Siva Ram Murthy and
Anusuya Balasubramanian},
title = {Modular performance analysis of Multicore SoC-based small cell {LTE}
base station},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {37--42},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314388},
doi = {10.1109/VLSI-SOC.2015.7314388},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SrinivasanMB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TangHM15,
author = {Jia Wei Tang and
Yuan Wen Hau and
Muhammad N. Marsono},
title = {Hardware/software partitioning of embedded System-on-Chip applications},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {331--336},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314439},
doi = {10.1109/VLSI-SOC.2015.7314439},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TangHM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsaiWS15,
author = {Chun{-}Jen Tsai and
Tsung{-}Han Wu and
Hung{-}Cheng Su},
title = {{JAIP-MP:} {A} four-core Java application processor},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {189--194},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314414},
doi = {10.1109/VLSI-SOC.2015.7314414},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TsaiWS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsaiWSC15,
author = {Chun{-}Jen Tsai and
Tsung{-}Han Wu and
Hung{-}Cheng Su and
Cheng{-}Yang Chen},
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {{JAIP-MP:} {A} Four-Core Java Application Processor for Embedded Systems},
booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
pages = {170--192},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-46097-0\_9},
doi = {10.1007/978-3-319-46097-0\_9},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TsaiWSC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/UbarJOR15,
author = {Raimund Ubar and
Lembit Jurimagi and
Elmet Orasson and
Jaan Raik},
title = {Scalable algorithm for structural fault collapsing in digital circuits},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {171--176},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314411},
doi = {10.1109/VLSI-SOC.2015.7314411},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/UbarJOR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/UbarJOR15a,
author = {Raimund Ubar and
Lembit J{\"{u}}rim{\"{a}}gi and
Elmet Orasson and
Jaan Raik},
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {Fault Collapsing in Digital Circuits Using Fast Fault Dominance and
Equivalence Analysis with SSBDDs},
booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
pages = {23--45},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-46097-0\_2},
doi = {10.1007/978-3-319-46097-0\_2},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/UbarJOR15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WeiZ15,
author = {Lin Wei and
Lei Zhou},
title = {An equilibrium partitioning method for multicast traffic in 3D NoC
architecture},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {128--133},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314404},
doi = {10.1109/VLSI-SOC.2015.7314404},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WeiZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/XueCYH15,
author = {Yuan Xue and
Patrick Cronin and
Chengmo Yang and
Jingtong Hu},
title = {Non-volatile memories in FPGAs: Exploiting logic similarity to accelerate
reconfiguration and increase programming cycles},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {92--97},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314398},
doi = {10.1109/VLSI-SOC.2015.7314398},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/XueCYH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YangV15,
author = {Chengmo Yang and
Maria Ruiz Varela},
title = {Qualifying non-volatile register files for embedded systems through
compiler-directed write minimization and balancing},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {86--91},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314397},
doi = {10.1109/VLSI-SOC.2015.7314397},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/YangV15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2013socs,
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-23799-2},
doi = {10.1007/978-3-319-23799-2},
isbn = {978-3-319-23798-5},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2013socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2014socs,
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-25279-7},
doi = {10.1007/978-3-319-25279-7},
isbn = {978-3-319-25278-0},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2014socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2015soc,
title = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
publisher = {{IEEE}},
year = {2015},
url = {https://ieeexplore.ieee.org/xpl/conhome/7304349/proceeding},
isbn = {978-1-4673-9140-5},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2015soc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/0001WWSB14,
author = {Matthias Jung and
Christian Weis and
Norbert Wehn and
MohammadSadegh Sadri and
Luca Benini},
editor = {Lorena Garcia},
title = {Optimized active and power-down mode refresh control in 3D-DRAMs},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004159},
doi = {10.1109/VLSI-SOC.2014.7004159},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/0001WWSB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AliSK14,
author = {Sk Subidh Ali and
Ozgur Sinanoglu and
Ramesh Karri},
editor = {Lorena Garcia},
title = {{AES} design space exploration new line for scan attack resiliency},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004193},
doi = {10.1109/VLSI-SOC.2014.7004193},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AliSK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmorPB14,
author = {Zeineb Bel Hadj Amor and
Laurence Pierre and
Dominique Borrione},
editor = {Lorena Garcia},
title = {A tool for the automatic TLM-to-RTL conversion of embedded systems
requirements for a seamless verification flow},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004196},
doi = {10.1109/VLSI-SOC.2014.7004196},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AmorPB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AurasDLA14,
author = {Dominik Auras and
Uwe Deidersen and
Rainer Leupers and
Gerd Ascheid},
editor = {Lorena Garcia},
title = {{VLSI} design of a parallel MCMC-based {MIMO} detector with multiplier-free
Gibbs samplers},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004160},
doi = {10.1109/VLSI-SOC.2014.7004160},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AurasDLA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AurasDLA14a,
author = {Dominik Auras and
Uwe Deidersen and
Rainer Leupers and
Gerd Ascheid},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {A Parallel MCMC-Based {MIMO} Detector: {VLSI} Design and Algorithm},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {149--169},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_9},
doi = {10.1007/978-3-319-25279-7\_9},
timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AurasDLA14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BabuKL14,
author = {Gunti Nagendra Babu and
Aman Khatri and
Karthikeyan Lingasubramanian},
editor = {Lorena Garcia},
title = {Realizing a security aware triple modular redundancy scheme for robust
integrated circuits},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004183},
doi = {10.1109/VLSI-SOC.2014.7004183},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BabuKL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BeroulleCCNDFHH14,
author = {Vincent Beroulle and
Philippe Candelier and
Stephan De Castro and
Giorgio Di Natale and
Jean{-}Max Dutertre and
Marie{-}Lise Flottes and
David H{\'{e}}ly and
Guillaume Hubert and
R{\'{e}}gis Leveugle and
Feng Lu and
Paolo Maistri and
Athanasios Papadimitriou and
Bruno Rouzeyre and
Cl{\'{e}}ment Tavernier and
Pierre Vanhauwaert},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {Laser-Induced Fault Effects in Security-Dedicated Circuits},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {220--240},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_12},
doi = {10.1007/978-3-319-25279-7\_12},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BeroulleCCNDFHH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BruniRTNKRP14,
author = {Giovanni Bruni and
Paolo Rech and
Lucas A. Tambara and
Gabriel L. Nazar and
Fernanda Gusm{\~{a}}o de Lima Kastensmidt and
Ricardo Reis and
Alessandro Paccagnella},
editor = {Lorena Garcia},
title = {Power dissipation effects on 28nm FPGA-based System on Chips neutron
sensitivity},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004195},
doi = {10.1109/VLSI-SOC.2014.7004195},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BruniRTNKRP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CaoFGDAO14,
author = {Ruping Cao and
John Ferguson and
Fabien Gays and
Youssef Drissi and
Alexandre Arriordaz and
Ian O'Connor},
editor = {Lorena Garcia},
title = {Silicon photonics design rule checking: Application of a programmable
modeling engine for non-Manhattan geometry verification},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004173},
doi = {10.1109/VLSI-SOC.2014.7004173},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CaoFGDAO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChibaniJPL14,
author = {K. Chibani and
Mohamed Ben Jrad and
Michele Portolan and
R{\'{e}}gis Leveugle},
editor = {Lorena Garcia},
title = {Fast accurate evaluation of register lifetime and criticality in a
pipelined microprocessor},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004158},
doi = {10.1109/VLSI-SOC.2014.7004158},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChibaniJPL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChusseauORJMTBVSLBRRR14,
author = {Laurent Chusseau and
Rachid Omarouayache and
J{\'{e}}r{\'{e}}my Raoult and
Sylvie Jarrix and
Philippe Maurine and
Karim Tobich and
Alexandre Boyer and
Bertrand Vrignon and
John Shepherd and
Thanh{-}Ha Le and
Ma{\"{e}}l Berthier and
Lionel Rivi{\`{e}}re and
Bruno Robisson and
Anne{-}Lise Ribotta},
editor = {Lorena Garcia},
title = {Electromagnetic analysis, deciphering and reverse engineering of integrated
circuits {(E-MATA} {HARI)}},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004189},
doi = {10.1109/VLSI-SOC.2014.7004189},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChusseauORJMTBVSLBRRR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CruzFM14,
author = {Alfonso Mart{\'{\i}}nez{-}Cruz and
Ricardo Barr{\'{o}}n Fern{\'{a}}ndez and
Her{\'{o}}n Molina{-}Lozano},
editor = {Lorena Garcia},
title = {Automated functional coverage directed for complex digital systems},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {155--156},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004172},
doi = {10.1109/VLSI-SOC.2014.7004172},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CruzFM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CucchettoLP14,
author = {Filippo Cucchetto and
Alessandro Lonardi and
Graziano Pravadelli},
editor = {Lorena Garcia},
title = {A common architecture for co-simulation of SystemC models in {QEMU}
and {OVP} virtual platforms},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004154},
doi = {10.1109/VLSI-SOC.2014.7004154},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CucchettoLP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DuboisSMB14,
author = {Matthieu Dubois and
Haralampos{-}G. D. Stratigopoulos and
Salvador Mir and
Manuel J. Barrag{\'{a}}n},
editor = {Lorena Garcia},
title = {Evaluation of digital ternary stimuli for dynamic test of {\(\Sigma\)}{\(\Delta\)}
ADCs},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004153},
doi = {10.1109/VLSI-SOC.2014.7004153},
timestamp = {Wed, 28 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DuboisSMB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DuboisSMB14a,
author = {Matthieu Dubois and
Haralampos{-}G. D. Stratigopoulos and
Salvador Mir and
Manuel J. Barrag{\'{a}}n},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {Statistical Evaluation of Digital Techniques for {\textdollar}{\textbackslash}sum{\textbackslash}varDelta{\textdollar}
{ADC} {BIST}},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {129--148},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_8},
doi = {10.1007/978-3-319-25279-7\_8},
timestamp = {Wed, 28 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DuboisSMB14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FigueroaA14,
author = {Javier Osorio Figueroa and
M{\'{o}}nico Linares Aranda},
editor = {Lorena Garcia},
title = {Study of on-chip vias of resonant rotary traveling wave oscillators},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {157--158},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004165},
doi = {10.1109/VLSI-SOC.2014.7004165},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FigueroaA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FujitaM14,
author = {Masahiro Fujita and
Alan Mishchenko},
editor = {Lorena Garcia},
title = {Logic synthesis and verification on fixed topology},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004155},
doi = {10.1109/VLSI-SOC.2014.7004155},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FujitaM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GastelVS14,
author = {Bernard van Gastel and
Freek Verbeek and
Julien Schmaltz},
editor = {Lorena Garcia},
title = {Inference of channel types in micro-architectural models of on-chip
communication networks},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004168},
doi = {10.1109/VLSI-SOC.2014.7004168},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GastelVS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GhissoniCL14,
author = {Sidinei Ghissoni and
Eduardo A. C. da Costa and
Angelo Goncalves da Luz},
editor = {Lorena Garcia},
title = {Implementation of power efficient multicore {FFT} datapaths by reordering
the twiddle factors},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004162},
doi = {10.1109/VLSI-SOC.2014.7004162},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GhissoniCL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JungLS14,
author = {Jinwook Jung and
Dongsoo Lee and
Youngsoo Shin},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {Design and Optimization of Multiple-Mesh Clock Network},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {39--57},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_3},
doi = {10.1007/978-3-319-25279-7\_3},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JungLS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KenningsDB14,
author = {Andrew A. Kennings and
Nima Karimpour Darav and
Laleh Behjat},
editor = {Lorena Garcia},
title = {Detailed placement accounting for technology constraints},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004188},
doi = {10.1109/VLSI-SOC.2014.7004188},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KenningsDB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KumarLGDZ14,
author = {Manoj Kumar and
Vijay Laxmi and
Manoj Singh Gaur and
Masoud Daneshtalab and
Mark Zwolinski},
editor = {Lorena Garcia},
title = {A novel non-minimal turn model for highly adaptive routing in 2D NoCs},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004192},
doi = {10.1109/VLSI-SOC.2014.7004192},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KumarLGDZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeC14,
author = {Dongwoo Lee and
Kiyoung Choi},
editor = {Lorena Garcia},
title = {Energy-efficient partitioning of hybrid caches in multi-core architecture},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004174},
doi = {10.1109/VLSI-SOC.2014.7004174},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeC14a,
author = {Dongwoo Lee and
Kiyoung Choi},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {58--74},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_4},
doi = {10.1007/978-3-319-25279-7\_4},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeC14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeveugleMVLNFRPHBHCDSBLDCT14,
author = {R{\'{e}}gis Leveugle and
Paolo Maistri and
Pierre Vanhauwaert and
Feng Lu and
Giorgio Di Natale and
Marie{-}Lise Flottes and
Bruno Rouzeyre and
Athanasios Papadimitriou and
David H{\'{e}}ly and
Vincent Beroulle and
Guillaume Hubert and
Stephan De Castro and
Jean{-}Max Dutertre and
Alexandre Sarafianos and
Noemie Boher and
Mathieu Lisart and
Joel Damiens and
Philippe Candelier and
Cl{\'{e}}ment Tavernier},
editor = {Lorena Garcia},
title = {Laser-induced fault effects in security-dedicated circuits},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004184},
doi = {10.1109/VLSI-SOC.2014.7004184},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeveugleMVLNFRPHBHCDSBLDCT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiBOML14,
author = {Zhen Li and
S{\'{e}}bastien Le Beux and
Ian O'Connor and
Christelle Monat and
Xavier Letartre},
editor = {Lorena Garcia},
title = {Complementary logic interface for high performan optical computing
with {OLUT}},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004178},
doi = {10.1109/VLSI-SOC.2014.7004178},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LiBOML14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LonardiP14,
author = {Alessandro Lonardi and
Graziano Pravadelli},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {On the Co-simulation of SystemC with {QEMU} and {OVP} Virtual Platforms},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {110--128},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_7},
doi = {10.1007/978-3-319-25279-7\_7},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LonardiP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MaistriLBAFRMMDL14,
author = {Paolo Maistri and
R{\'{e}}gis Leveugle and
Lilian Bossuet and
Alain Aubert and
Viktor Fischer and
Bruno Robisson and
Nicolas Moro and
Philippe Maurine and
Jean{-}Max Dutertre and
Mathieu Lisart},
editor = {Lorena Garcia},
title = {Electromagnetic analysis and fault injection onto secure circuits},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004182},
doi = {10.1109/VLSI-SOC.2014.7004182},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MaistriLBAFRMMDL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MannaCS14,
author = {Kanchan Manna and
Santanu Chattopadhyay and
Indranil Sengupta},
editor = {Lorena Garcia},
title = {Through silicon via placement and mapping strategy for 3D mesh based
Network-on-Chip},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004177},
doi = {10.1109/VLSI-SOC.2014.7004177},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MannaCS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MarconiSPC14,
author = {Thomas Marconi and
Christian Spagnol and
Emanuel M. Popovici and
Sorin Cotofana},
editor = {Lorena Garcia},
title = {Towards energy effective {LDPC} decoding by exploiting channel noise
variability},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004180},
doi = {10.1109/VLSI-SOC.2014.7004180},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MarconiSPC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MarconiSPC14a,
author = {Thomas Marconi and
Christian Spagnol and
Emanuel M. Popovici and
Sorin Cotofana},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {Transmission Channel Noise Aware Energy Effective {LDPC} Decoding},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {198--219},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_11},
doi = {10.1007/978-3-319-25279-7\_11},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MarconiSPC14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/McDanielGB14,
author = {Jeffrey McDaniel and
Daniel T. Grissom and
Philip Brisk},
editor = {Lorena Garcia},
title = {Multi-terminal {PCB} escape routing for digital microfluidic biochips
using negotiated congestion},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004181},
doi = {10.1109/VLSI-SOC.2014.7004181},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/McDanielGB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/McDanielPB14,
author = {Jeffrey McDaniel and
Brendon Parker and
Philip Brisk},
editor = {Lorena Garcia},
title = {Simulated annealing-based placement for microfluidic large scale integration
(mLSI) chips},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004170},
doi = {10.1109/VLSI-SOC.2014.7004170},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/McDanielPB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Mendoza-BonillaCVRG14,
author = {Jesus{-}Andres Mendoza{-}Bonilla and
Alejandro Cortez{-}Ibarra and
Edgar{-}Andrei Vega{-}Ochoa and
Francisco Rangel{-}Patino and
Brandon Gore},
editor = {Lorena Garcia},
title = {Backplane/FDA correlation-FDA replacing commercial backplanes for
SoC ethernet electrical validation},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004190},
doi = {10.1109/VLSI-SOC.2014.7004190},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Mendoza-BonillaCVRG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MiorandiGNB14,
author = {Gabriele Miorandi and
Alberto Ghiribaldi and
Steven M. Nowick and
Davide Bertozzi},
editor = {Lorena Garcia},
title = {Crossbar replication vs. sharing for virtual channel flow control
in asynchronous NoCs: {A} comparative study},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004164},
doi = {10.1109/VLSI-SOC.2014.7004164},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MiorandiGNB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MoradiM14,
author = {Farshad Moradi and
Jens Kargaard Madsen},
editor = {Lorena Garcia},
title = {Improved read and write margins using a novel 8T-SRAM cell},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--5},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004186},
doi = {10.1109/VLSI-SOC.2014.7004186},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MoradiM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MoradiTZM14,
author = {Farshad Moradi and
Mohammad Tohidi and
Behzad Zeinali and
Jens Kargaard Madsen},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {8T-SRAM Cell with Improved Read and Write Margins in 65 nm {CMOS}
Technology},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {95--109},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_6},
doi = {10.1007/978-3-319-25279-7\_6},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MoradiTZM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MoreiraC14,
author = {Matheus T. Moreira and
Ney Laert Vilar Calazans},
editor = {Lorena Garcia},
title = {Advances on the state of the art in {QDI} design},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {163--164},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004169},
doi = {10.1109/VLSI-SOC.2014.7004169},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MoreiraC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuthyalaT14,
author = {Sreenivaas S. Muthyala and
Nur A. Touba},
editor = {Lorena Garcia},
title = {Reducing test time for 3D-ICs by improved utilization of test elevators},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004157},
doi = {10.1109/VLSI-SOC.2014.7004157},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MuthyalaT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuthyalaT14a,
author = {Sreenivaas S. Muthyala and
Nur A. Touba},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {21--38},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_2},
doi = {10.1007/978-3-319-25279-7\_2},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MuthyalaT14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NakanishiMY14,
author = {Masaki Nakanishi and
Miki Matsuyama and
Yumi Yokoo},
editor = {Lorena Garcia},
title = {A quantum algorithm processor architecture based on register reordering},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004175},
doi = {10.1109/VLSI-SOC.2014.7004175},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NakanishiMY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Nannarelli14,
author = {Alberto Nannarelli},
editor = {Lorena Garcia},
title = {Decimal engine for energy-efficient multicore processors},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004176},
doi = {10.1109/VLSI-SOC.2014.7004176},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Nannarelli14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PendyalaK14,
author = {Shilpa Pendyala and
Srinivas Katkoori},
editor = {Lorena Garcia},
title = {Self similarity and interval arithmetic based leakage optimization
in {RTL} datapaths},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004171},
doi = {10.1109/VLSI-SOC.2014.7004171},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PendyalaK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PendyalaK14a,
author = {Shilpa Pendyala and
Srinivas Katkoori},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {Interval Arithmetic and Self Similarity Based Subthreshold Leakage
Optimization in {RTL} Datapaths},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {75--94},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_5},
doi = {10.1007/978-3-319-25279-7\_5},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PendyalaK14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PopovicL14,
author = {Vladan Popovic and
Yusuf Leblebici},
editor = {Lorena Garcia},
title = {Reconfigurable forward homography estimation system for real-time
applications},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004161},
doi = {10.1109/VLSI-SOC.2014.7004161},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PopovicL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Rakossy14,
author = {Zolt{\'{a}}n Endre R{\'{a}}kossy},
editor = {Lorena Garcia},
title = {Modeling, analysis and exploration of layers: {A} 3D computing architecture},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {159--160},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004167},
doi = {10.1109/VLSI-SOC.2014.7004167},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Rakossy14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RakossyMANC14,
author = {Zolt{\'{a}}n Endre R{\'{a}}kossy and
Farhad Merchant and
Axel Acosta{-}Aponte and
S. K. Nandy and
Anupam Chattopadhyay},
editor = {Lorena Garcia},
title = {Scalable and energy-efficient reconfigurable accelerator for column-wise
givens rotation},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004166},
doi = {10.1109/VLSI-SOC.2014.7004166},
timestamp = {Tue, 22 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RakossyMANC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RaviGB14,
author = {Hari Anand Ravi and
Mayank Goel and
Prasad Bhilawadi},
editor = {Lorena Garcia},
title = {Circuit to reduce Gate Induced Drain Leakage in {CMOS} output buffers},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--5},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004187},
doi = {10.1109/VLSI-SOC.2014.7004187},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RaviGB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SabenaRS14,
author = {Davide Sabena and
Matteo Sonza Reorda and
Luca Sterpone},
editor = {Lorena Garcia},
title = {Soft error effects analysis and mitigation in {VLIW} safety-critical
applications},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004194},
doi = {10.1109/VLSI-SOC.2014.7004194},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SabenaRS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SeokPCK14,
author = {Moon Gi Seok and
Daejin Park and
Geun Rae Cho and
Tag Gon Kim},
editor = {Lorena Garcia},
title = {Framework for simulation of the Verilog/SPICE mixed model: Interoperation
of Verilog and {SPICE} simulators using {HLA/RTI} for model reusability},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004185},
doi = {10.1109/VLSI-SOC.2014.7004185},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SeokPCK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SeyidCPASL14,
author = {Kerem Seyid and
{\"{O}}mer {\c{C}}ogal and
Vladan Popovic and
Hossein Afshari and
Alexandre Schmid and
Yusuf Leblebici},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {Real-Time Omnidirectional Imaging System with Interconnected Network
of Cameras},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {170--197},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_10},
doi = {10.1007/978-3-319-25279-7\_10},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SeyidCPASL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsaiLLN14,
author = {Wei{-}Yu Tsai and
Huichu Liu and
Xueqing Li and
Vijaykrishnan Narayanan},
editor = {Lorena Garcia},
title = {Low-power high-speed current mode logic using Tunnel-FETs},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004179},
doi = {10.1109/VLSI-SOC.2014.7004179},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TsaiLLN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WangWM14,
author = {Liang Wang and
Xiaohang Wang and
Terrence S. T. Mak},
editor = {Lorena Garcia},
title = {Dynamic programming-based lifetime aware adaptive routing algorithm
for Network-on-Chip},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004156},
doi = {10.1109/VLSI-SOC.2014.7004156},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WangWM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WangWM14a,
author = {Liang Wang and
Xiaohang Wang and
Terrence S. T. Mak},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {1--20},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_1},
doi = {10.1007/978-3-319-25279-7\_1},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WangWM14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YamauchiS14,
author = {Hiroyuki Yamauchi and
Worawit Somha},
editor = {Lorena Garcia},
title = {Deconvolution algorithm dependencies of estimation errors of {RTN}
effects on subnano-scaled {SRAM} margin variation},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004191},
doi = {10.1109/VLSI-SOC.2014.7004191},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/YamauchiS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhangZZG14,
author = {Shuping Zhang and
Jinjia Zhou and
Dajiang Zhou and
Satoshi Goto},
editor = {Lorena Garcia},
title = {A low power 720p motion estimation processor with 3D stacked memory},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004163},
doi = {10.1109/VLSI-SOC.2014.7004163},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhangZZG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2014soc,
editor = {Lorena Garcia},
title = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
publisher = {{IEEE}},
year = {2014},
url = {https://ieeexplore.ieee.org/xpl/conhome/6996506/proceeding},
isbn = {978-1-4799-6016-3},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2014soc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AdelLS13,
author = {Hussein Adel and
Marie{-}Minerve Lou{\"{e}}rat and
Marc Sabut},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Design considerations for low gain amplifier in the {MDAC} of digitally
calibrated pipelined ADCs},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {23--26},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673239},
doi = {10.1109/VLSI-SOC.2013.6673239},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AdelLS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AdiZHFKJA13,
author = {Wael Adi and
Shaza Zeitouni and
X. Huang and
Marc Fyrbiak and
Christian Kison and
Marc Jeske and
Z. Alnahhas},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {IP-core protection for a non-volatile Self-reconfiguring SoC environment},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {252--255},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673284},
doi = {10.1109/VLSI-SOC.2013.6673284},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AdiZHFKJA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AdibelliH13,
author = {Yusuf Adibelli and
Ilker Hamzaoglu},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A high performance and low energy hardware for intra prediction with
Template Matching},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {282--285},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673290},
doi = {10.1109/VLSI-SOC.2013.6673290},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AdibelliH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AkinBGSL13,
author = {Abdulkadir Akin and
Ipek Baz and
Luis Manuel Gaemperle and
Alexandre Schmid and
Yusuf Leblebici},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Compressed look-up-table based real-time rectification hardware},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {272--277},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673288},
doi = {10.1109/VLSI-SOC.2013.6673288},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AkinBGSL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AkinGNSL13,
author = {Abdulkadir Akin and
Luis Manuel Gaemperle and
Halima Najibi and
Alexandre Schmid and
Yusuf Leblebici},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {227--248},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_11},
doi = {10.1007/978-3-319-23799-2\_11},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AkinGNSL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AksoyFM13,
author = {Levent Aksoy and
Paulo F. Flores and
Jos{\'{e}} Monteiro},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Towards the least complex time-multiplexed constant multiplication},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {328--331},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673302},
doi = {10.1109/VLSI-SOC.2013.6673302},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AksoyFM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AliSSK13,
author = {Sk Subidh Ali and
Ozgur Sinanoglu and
Samah Mohamed Saeed and
Ramesh Karri},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {New scan-based attack using only the test mode},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {234--239},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673281},
doi = {10.1109/VLSI-SOC.2013.6673281},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AliSSK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AliSSK13a,
author = {Sk Subidh Ali and
Samah Mohamed Saeed and
Ozgur Sinanoglu and
Ramesh Karri},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {New Scan-Based Attack Using Only the Test Mode and an Input Corruption
Countermeasure},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {48--68},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_3},
doi = {10.1007/978-3-319-23799-2\_3},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AliSSK13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AlzaherT13,
author = {Hussain A. Alzaher and
Noman Tasadduq},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Fully electronically programmable complex filter for multistandard
applications},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {13--18},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673237},
doi = {10.1109/VLSI-SOC.2013.6673237},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AlzaherT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ArtesAFRC13,
author = {Antonio Art{\'{e}}s and
Jos{\'{e}} Luis Ayala and
Robert Fasthuber and
Praveen Raghavan and
Francky Catthoor},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Energy impact in the design space exploration of loop buffer schemes
in embedded systems},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {216--221},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673278},
doi = {10.1109/VLSI-SOC.2013.6673278},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ArtesAFRC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AshouriZXPS13,
author = {Amir Hossein Ashouri and
Vittorio Zaccaria and
Sotirios Xydis and
Gianluca Palermo and
Cristina Silvano},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A framework for Compiler Level statistical analysis over customized
{VLIW} architecture},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {124--129},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673262},
doi = {10.1109/VLSI-SOC.2013.6673262},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AshouriZXPS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AykenarOSE13,
author = {Mehmet Burak Aykenar and
Muhammet Ozgur and
Osman Seckin Simsek and
Oguz Ergin},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Adapting the columns of storage components for lower static energy
dissipation},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {222--227},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673279},
doi = {10.1109/VLSI-SOC.2013.6673279},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AykenarOSE13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AysuSC13,
author = {Aydin Aysu and
Murat Sayinta and
Cevahir Cigla},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Low cost {FPGA} design and implementation of a stereo matching system
for 3D-TV applications},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {204--209},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673276},
doi = {10.1109/VLSI-SOC.2013.6673276},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AysuSC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AzghadiAIA13,
author = {Mostafa Rahimi Azghadi and
Said F. Al{-}Sarawi and
Nicolangelo Iannella and
Derek Abbott},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A new compact analog {VLSI} model for Spike Timing Dependent Plasticity},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {7--12},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673236},
doi = {10.1109/VLSI-SOC.2013.6673236},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AzghadiAIA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BaiAMHCGG13,
author = {Yuhui Bai and
Syed Zahid Ahmed and
Imen Mhedhbi and
Khalil Hachicha and
Cedric Champion and
Patrick Garda and
Bertrand Granado},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {{FPGA} vs {DSP:} {A} throughput and power efficiency comparison for
Hierarchical Enumerative Coding},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {318--321},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673300},
doi = {10.1109/VLSI-SOC.2013.6673300},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BaiAMHCGG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BanerjeeZRZ13,
author = {Soumya Banerjee and
Kai Da Zhao and
Wenjing Rao and
Milos Zefran},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Decentralized self-balancing systems},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {340--343},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673305},
doi = {10.1109/VLSI-SOC.2013.6673305},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BanerjeeZRZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Bayrakci13,
author = {Alp Arslan Bayrakci},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {On the accuracy of Monte Carlo yield estimators},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {56--57},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673247},
doi = {10.1109/VLSI-SOC.2013.6673247},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Bayrakci13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BeltSD13,
author = {Jonathan van de Belt and
Paul D. Sutton and
Linda Doyle},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Accelerating software radio: Iris on the Zynq SoC},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {294--295},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673295},
doi = {10.1109/VLSI-SOC.2013.6673295},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BeltSD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BentobacheBEKM13,
author = {Mohand Bentobache and
Ahc{\`{e}}ne Bounceur and
Reinhardt Euler and
Yann Kieffer and
Salvador Mir},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {New techniques for selecting test frequencies for linear analog circuits},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {90--95},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673256},
doi = {10.1109/VLSI-SOC.2013.6673256},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BentobacheBEKM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BentobacheBEMK13,
author = {Mohand Bentobache and
Ahc{\`{e}}ne Bounceur and
Reinhardt Euler and
Salvador Mir and
Yann Kieffer},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {Minimizing Test Frequencies for Linear Analog Circuits: New Models
and Efficient Solution Methods},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {188--207},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_9},
doi = {10.1007/978-3-319-23799-2\_9},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BentobacheBEMK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernasconiCTV13,
author = {Anna Bernasconi and
Valentina Ciriani and
Gabriella Trucco and
Tiziano Villa},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Minimization of EP-SOPs via Boolean relations},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {112--117},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673260},
doi = {10.1109/VLSI-SOC.2013.6673260},
timestamp = {Sat, 23 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BernasconiCTV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BeuxLMLO13,
author = {S{\'{e}}bastien Le Beux and
Zhen Li and
Christelle Monat and
Xavier Letartre and
Ian O'Connor},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Reconfigurable photonic switching: Towards all-optical FPGAs},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {180--185},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673272},
doi = {10.1109/VLSI-SOC.2013.6673272},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BeuxLMLO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ConosMP13,
author = {Nathaniel A. Conos and
Saro Meguerdichian and
Miodrag Potkonjak},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Gate sizing in the presence of gate switching activity and input vector
control},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {138--143},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673265},
doi = {10.1109/VLSI-SOC.2013.6673265},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ConosMP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ConosMP13a,
author = {Nathaniel A. Conos and
Saro Meguerdichian and
Miodrag Potkonjak},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {Gate Sizing Under Uncertainty},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {23--47},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_2},
doi = {10.1007/978-3-319-23799-2\_2},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ConosMP13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ElloumiKM13,
author = {Manel Elloumi and
Mohamed Krid and
Dorra Sellami Masmoudi},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Implementation of Neuro-Fuzzy System based image edge detection},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {60--61},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673249},
doi = {10.1109/VLSI-SOC.2013.6673249},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ElloumiKM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EshghabadiBNMMS13,
author = {Farshad Eshghabadi and
Fatemeh Banitorfian and
Norlaili Mohd Noh and
Mohd Tafir Mustaffa and
Asrulnizam Bin Abd Manaf and
Othman Sidek},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Multi-band tunable low noise amplifiers operating at 850MHz and 1900MHz
standards},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {64--65},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673251},
doi = {10.1109/VLSI-SOC.2013.6673251},
timestamp = {Mon, 13 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/EshghabadiBNMMS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EzeON13,
author = {Melvin Eze and
Ozcan Ozturk and
Vijaykrishnan Narayanan},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Staggered latch bus: {A} reliable offset switched architecture for
long on-chip interconnect},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {296--301},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673296},
doi = {10.1109/VLSI-SOC.2013.6673296},
timestamp = {Thu, 17 Aug 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/EzeON13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FilguerasGAJMLN13,
author = {Antonio Filgueras and
Eduard Gil and
Carlos {\'{A}}lvarez and
Daniel Jim{\'{e}}nez{-}Gonz{\'{a}}lez and
Xavier Martorell and
Jan Langer and
Juanjo Noguera},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Heterogeneous tasking on {SMP/FPGA} SoCs: The case of OmpSs and the
Zynq},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {290--291},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673293},
doi = {10.1109/VLSI-SOC.2013.6673293},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/FilguerasGAJMLN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FletcherHKD13,
author = {Christopher W. Fletcher and
Rachael Harding and
Omer Khan and
Srinivas Devadas},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A framework to accelerate sequential programs on homogeneous multicores},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {344--347},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673306},
doi = {10.1109/VLSI-SOC.2013.6673306},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FletcherHKD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FujitaMJ13,
author = {Masahiro Fujita and
Takeshi Matsumoto and
Satoshi Jo},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {{FOF:} Functionally Observable Fault and its {ATPG} techniques},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {108--111},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673259},
doi = {10.1109/VLSI-SOC.2013.6673259},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FujitaMJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GuthmullerPG13,
author = {Eric Guthmuller and
Ivan Miro Panades and
Alain Greiner},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Architectural exploration of a fine-grained 3D cache for high performance
in a manycore context},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {302--307},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673297},
doi = {10.1109/VLSI-SOC.2013.6673297},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GuthmullerPG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HamadaZAIKS13,
author = {Tetsuro Hamada and
Qian Zhao and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Three-dimensional stacking {FPGA} architecture using face-to-face
integration},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {192--197},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673274},
doi = {10.1109/VLSI-SOC.2013.6673274},
timestamp = {Wed, 18 Oct 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HamadaZAIKS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HamoudaAMB13,
author = {Assia Hamouda and
R{\"{u}}diger Arnold and
Otto Manck and
Nour{-}Eddine Bouguechal},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {7.72 ppm/{\textdegree}C, ultralow power, high {PSRR} {CMOS} bandgap
reference voltage},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {364--367},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673310},
doi = {10.1109/VLSI-SOC.2013.6673310},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HamoudaAMB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HassanpourghadiS13,
author = {Mohsen Hassanpourghadi and
Mohammad Sharifkhani},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Step response analysis of third order OpAmps With slew-rate},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {62--63},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673250},
doi = {10.1109/VLSI-SOC.2013.6673250},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HassanpourghadiS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HeCL13,
author = {Yajuan He and
Bo Chen and
Qiang Li},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Blind-LMS based digital background calibration for a 14-Bit 200-MS/s
pipelined {ADC}},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {348--351},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673307},
doi = {10.1109/VLSI-SOC.2013.6673307},
timestamp = {Wed, 09 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HeCL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JiaoK13,
author = {Hailong Jiao and
Volkan Kursun},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Characterization of mode transition timing overhead for net energy
savings in low-noise {MTCMOS} circuits},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {150--155},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673267},
doi = {10.1109/VLSI-SOC.2013.6673267},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JiaoK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KamranN13,
author = {Arezoo Kamran and
Zainalabedin Navabi},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Online periodic test mechanism for homogeneous many-core processors},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {256--259},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673285},
doi = {10.1109/VLSI-SOC.2013.6673285},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KamranN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KarimiHMT13,
author = {Elmira Karimi and
Mohammad Hashem Haghbayan and
Adele Maleki and
Mahmoud Tabandeh},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Graph based fault model definition for bus testing},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {54--55},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673246},
doi = {10.1109/VLSI-SOC.2013.6673246},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KarimiHMT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimF13,
author = {Sungho Kim and
Urs Frey},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {An inverter-based neural amplifier for neural spike detection},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {45--49},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673243},
doi = {10.1109/VLSI-SOC.2013.6673243},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KnochGM13,
author = {Joachim Knoch and
Thomas Grap and
Marcel M{\"{u}}ller},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Gate-controlled doping in carbon-based FETs},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {162--167},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673269},
doi = {10.1109/VLSI-SOC.2013.6673269},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KnochGM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KomurcuPD13,
author = {Giray K{\"{o}}m{\"{u}}rc{\"{u}} and
Ali Emre Pusane and
G{\"{u}}nhan D{\"{u}}ndar},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Analysis of Ring Oscillator structures to develop a design methodology
for {RO-PUF} circuits},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {332--335},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673303},
doi = {10.1109/VLSI-SOC.2013.6673303},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KomurcuPD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KuoJ13,
author = {Chien{-}Hung Kuo and
Cin{-}De Jhang},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A center-aligned digital pulse-width modulator for envelope modulation
of polar transmitters},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {386--389},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673314},
doi = {10.1109/VLSI-SOC.2013.6673314},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KuoJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LaurenciuWC13,
author = {Nicoleta Cucu Laurenciu and
Yao Wang and
Sorin Dan Cotofana},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A direct measurement scheme of amalgamated aging effects with novel
on-chip sensor},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {246--251},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673283},
doi = {10.1109/VLSI-SOC.2013.6673283},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LaurenciuWC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeCT13,
author = {Chien{-}Min Lee and
Chi{-}Kang Chen and
Ren{-}Song Tsay},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A basic-block power annotation approach for fast and accurate embedded
software power estimation},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {118--123},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673261},
doi = {10.1109/VLSI-SOC.2013.6673261},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeCT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeG13,
author = {Seogoo Lee and
Andreas Gerstlauer},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Fine grain word length optimization for dynamic precision scaling
in {DSP} systems},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {266--271},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673287},
doi = {10.1109/VLSI-SOC.2013.6673287},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeG13a,
author = {Seogoo Lee and
Andreas Gerstlauer},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {Fine Grain Precision Scaling for Datapath Approximations in Digital
Signal Processing Systems},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {119--143},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_6},
doi = {10.1007/978-3-319-23799-2\_6},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LeeG13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MatosRMS13,
author = {Debora Matos and
Cezar Reinbrecht and
Tiago Motta and
Altamiro Amadeu Susin},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A power-efficient hierarchical network-on-chip topology for stacked
3D ICs},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {308--313},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673298},
doi = {10.1109/VLSI-SOC.2013.6673298},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MatosRMS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MelikyanBDSSMM13,
author = {Vazgen Melikyan and
Abraham Balabanyan and
Armen Durgaryan and
Harutyun Stepanyan and
Karen Sloyan and
Hovik Musayelyan and
Gayane Markosyan},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {{PVT} variation detection and compensation methods for high-speed
systems},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {322--327},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673301},
doi = {10.1109/VLSI-SOC.2013.6673301},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MelikyanBDSSMM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MengZC13,
author = {Jie Meng and
Tiansheng Zhang and
Ayse K. Coskun},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Dynamic cache pooling for improving energy efficiency in 3D stacked
multicore processors},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {210--215},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673277},
doi = {10.1109/VLSI-SOC.2013.6673277},
timestamp = {Tue, 23 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MengZC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MinwegenAA13,
author = {Andreas Minwegen and
Dominik Auras and
Gerd Ascheid},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {A Flexible {ASIC} for Time-Domain Decision-Directed Channel Estimation
in {MIMO-OFDM} Systems},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {249--265},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_12},
doi = {10.1007/978-3-319-23799-2\_12},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MinwegenAA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Morin-AlloryJB13,
author = {Katell Morin{-}Allory and
Fatemeh Negin Javaheri and
Dominique Borrione},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {SyntHorus-2: Automatic prototyping from {PSL}},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {72--77},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673253},
doi = {10.1109/VLSI-SOC.2013.6673253},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Morin-AlloryJB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MullerMAMSR13,
author = {Christoph Thomas Muller and
Steffen Malkowsky and
Oskar Andersson and
Babak Mohammadi and
Jens Spars{\o} and
Joachim Neves Rodrigues},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A 65-nm {CMOS} area optimized de-synchronization flow for sub-VT designs},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {380--385},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673313},
doi = {10.1109/VLSI-SOC.2013.6673313},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MullerMAMSR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MysurPMM13,
author = {Kaushik Triyambaka Mysur and
Mihai Pricopi and
Thomas Marconi and
Tulika Mitra},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Implementation of core coalition on FPGAs},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {198--203},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673275},
doi = {10.1109/VLSI-SOC.2013.6673275},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MysurPMM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NassifPA13,
author = {Sani R. Nassif and
Yale N. Patt and
Magdy S. Abadir},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Keynote 1 - {VLSI} 2.0: R{\&}D Post Moore},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673229},
doi = {10.1109/VLSI-SOC.2013.6673229},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NassifPA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NunesRR13,
author = {Leandro Nunes and
Tiago Reimann and
Ricardo Reis},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {{GR-PA:} {A} cost pre-allocation model for global routing},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {134--137},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673264},
doi = {10.1109/VLSI-SOC.2013.6673264},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NunesRR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OshimaMF13,
author = {Kosuke Oshima and
Takeshi Matsumoto and
Masahiro Fujita},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A debugging method for gate level circuit designs by introducing programmability},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {78--83},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673254},
doi = {10.1109/VLSI-SOC.2013.6673254},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/OshimaMF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OshimaMF13a,
author = {Kosuke Oshima and
Takeshi Matsumoto and
Masahiro Fujita},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {Debugging Methods Through Identification of Appropriate Functions
for Internal Gates},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {1--22},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_1},
doi = {10.1007/978-3-319-23799-2\_1},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/OshimaMF13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OzTKT13,
author = {Isil {\"{O}}z and
Haluk Rahmi Topcuoglu and
Mahmut T. Kandemir and
Oguz Tosun},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Examining Thread Vulnerability analysis using fault-injection},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {240--245},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673282},
doi = {10.1109/VLSI-SOC.2013.6673282},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/OzTKT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OzanogluT13,
author = {Kemal Ozanoglu and
Sel{\c{c}}uk Talay},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Effects of the positive feedback loop in self biased bandgap reference
circuits},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {50--51},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673244},
doi = {10.1109/VLSI-SOC.2013.6673244},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/OzanogluT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/OzgulLNV13,
author = {Baris {\"{O}}zg{\"{u}}l and
Jan Langer and
Juanjo Noguera and
Kees A. Vissers},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Software-programmable digital pre-distortion on the Zynq SoC},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {288--289},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673292},
doi = {10.1109/VLSI-SOC.2013.6673292},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/OzgulLNV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PapadimitriouTD13,
author = {Kyprianos Papadimitriou and
Sotiris Thomas and
Apostolos Dollas},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {An FPGA-Based Real-Time System for 3D Stereo Matching, Combining Absolute
Differences and Census with Aggregation and Belief Propagation},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {168--187},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_8},
doi = {10.1007/978-3-319-23799-2\_8},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PapadimitriouTD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParkJYK13,
author = {Jongbum Park and
Jongpil Jung and
Kang Yi and
Chong{-}Min Kyung},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Static energy minimization of 3D stacked {L2} cache with selective
cache compression},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {228--233},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673280},
doi = {10.1109/VLSI-SOC.2013.6673280},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ParkJYK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Pelloux-PrayerVGTNFB13,
author = {Bertrand Pelloux{-}Prayer and
Alexandre Valentian and
Bastien Giraud and
Yvain Thonnart and
Jean{-}Philippe Noel and
Philippe Flatresse and
Edith Beign{\'{e}}},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Fine grain multi-VT co-integration methodology in {UTBB} {FD-SOI}
technology},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {168--173},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673270},
doi = {10.1109/VLSI-SOC.2013.6673270},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Pelloux-PrayerVGTNFB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PovoaLHSG13,
author = {Ricardo Povoa and
Nuno Louren{\c{c}}o and
Nuno Horta and
Rui Santos{-}Tavares and
Jo{\~{a}}o Goes},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Single-stage amplifiers with gain enhancement and improved energy-efficiency
employing voltage-combiners},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {19--22},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673238},
doi = {10.1109/VLSI-SOC.2013.6673238},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PovoaLHSG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/QiuZFX13,
author = {Keni Qiu and
Mengying Zhao and
Chenchen Fu and
Chun Jason Xue},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Data re-allocation enabled cache locking for embedded systems},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {130--133},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673263},
doi = {10.1109/VLSI-SOC.2013.6673263},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/QiuZFX13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RajskiPSCNGG13,
author = {Janusz Rajski and
Miodrag Potkonjak and
Adit D. Singh and
Abhijit Chatterjee and
Zain Navabi and
Matthew R. Guthaus and
Sezer G{\"{o}}ren},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates
to transistors},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673230},
doi = {10.1109/VLSI-SOC.2013.6673230},
timestamp = {Tue, 16 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RajskiPSCNGG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RenN13,
author = {Yuan Ren and
Tobias G. Noll},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {An accurate power estimation model for low-power hierarchical-architecture
SRAMs},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {144--149},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673266},
doi = {10.1109/VLSI-SOC.2013.6673266},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RenN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RenN13a,
author = {Yuan Ren and
Tobias G. Noll},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture
SRAMs Based on Accurate Cost Models},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {69--93},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_4},
doi = {10.1007/978-3-319-23799-2\_4},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RenN13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RichardsonSMH13,
author = {Stephen Richardson and
Ofer Shacham and
Dejan Markovic and
Mark Horowitz},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {An area-efficient minimum-time {FFT} schedule using single-ported
memory},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {39--44},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673242},
doi = {10.1109/VLSI-SOC.2013.6673242},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RichardsonSMH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SabenaRS13,
author = {Davide Sabena and
Matteo Sonza Reorda and
Luca Sterpone},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {On the development of diagnostic test programs for {VLIW} processors},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {84--89},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673255},
doi = {10.1109/VLSI-SOC.2013.6673255},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SabenaRS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SabenaRS13a,
author = {Davide Sabena and
Matteo Sonza Reorda and
Luca Sterpone},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {Partition-Based Faults Diagnosis of a {VLIW} Processor},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {208--226},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_10},
doi = {10.1007/978-3-319-23799-2\_10},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SabenaRS13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Sanchis-CasesMC13,
author = {Francisco{-}Jose Sanchis{-}Cases and
Antonio Mart{\'{\i}}nez{-}{\'{A}}lvarez and
Sergio Cuenca{-}Asensi},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Automatic mapping of OpenCV based systems on new heterogeneous SoCs},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {292--293},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673294},
doi = {10.1109/VLSI-SOC.2013.6673294},
timestamp = {Mon, 06 Nov 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Sanchis-CasesMC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchaffnerHCFGGS13,
author = {Michael Schaffner and
Pascal A. Hager and
Lukas Cavigelli and
Z. Fang and
Pierre Greisen and
Frank K. G{\"{u}}rkaynak and
Aljoscha Smolic and
Hubert Kaeslin and
Luca Benini},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {A Complete Real-Time Feature Extraction and Matching System Based
on Semantic Kernels Binarized},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {144--167},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_7},
doi = {10.1007/978-3-319-23799-2\_7},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SchaffnerHCFGGS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchaffnerHCGGK13,
author = {Michael Schaffner and
Pascal Hager and
Lukas Cavigelli and
Pierre Greisen and
Frank K. G{\"{u}}rkaynak and
Hubert Kaeslin},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A real-time 720p feature extraction core based on Semantic Kernels
Binarized},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {27--32},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673240},
doi = {10.1109/VLSI-SOC.2013.6673240},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SchaffnerHCGGK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SheshadriAA13,
author = {Vijay Sheshadri and
Vishwani D. Agrawal and
Prathima Agrawal},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Power-aware SoC test optimization through dynamic voltage and frequency
scaling},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {102--107},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673258},
doi = {10.1109/VLSI-SOC.2013.6673258},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SheshadriAA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SudevI13,
author = {Bharath Sudev and
Leandro Soares Indrusiak},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {{PFT} - {A} low overhead predictability enhancement technique for
non-preemptive NoCs},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {314--317},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673299},
doi = {10.1109/VLSI-SOC.2013.6673299},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SudevI13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TanurhanW13,
author = {Yankin Tanurhan and
Pieter van der Wolf},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Processors as SoC building blocks},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {286--287},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673291},
doi = {10.1109/VLSI-SOC.2013.6673291},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TanurhanW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ThomasPD13,
author = {Sotiris Thomas and
Kyprianos Papadimitriou and
Apostolos Dollas},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Architecture and implementation of real-time 3D stereo vision on a
Xilinx {FPGA}},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {186--191},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673273},
doi = {10.1109/VLSI-SOC.2013.6673273},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ThomasPD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TimarchiSFG13,
author = {Somayeh Timarchi and
Maryam Saremi and
Mahmood Fazlali and
Georgi Gaydadjiev},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {High-speed Binary Signed-Digit {RNS} adder with posibit and negabit
encoding},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {58--59},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673248},
doi = {10.1109/VLSI-SOC.2013.6673248},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TimarchiSFG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TossonGA13,
author = {Amr M. S. Tosson and
Siddharth Garg and
Mohab H. Anis},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Tagged probabilistic simulation based error probability estimation
for better-than-worst case circuit design},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {368--373},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673311},
doi = {10.1109/VLSI-SOC.2013.6673311},
timestamp = {Wed, 26 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TossonGA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsoumanisEMP13,
author = {Kostas Tsoumanis and
Constantinos Efstathiou and
Nikolaos Moschopoulos and
Kiamal Z. Pekmestzi},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {On the design of modulo 2\({}^{\mbox{n}}\){\(\pm\)}1 residue generators},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {33--38},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673241},
doi = {10.1109/VLSI-SOC.2013.6673241},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TsoumanisEMP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/UgurdagTG13,
author = {H. Fatih Ugurdag and
Fatih Temizkan and
Sezer G{\"{o}}ren},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Generating fast logic circuits for m-select n-port Round Robin Arbitration},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {260--265},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673286},
doi = {10.1109/VLSI-SOC.2013.6673286},
timestamp = {Tue, 16 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/UgurdagTG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/UlusSB13,
author = {Dogan Ulus and
Alper Sen and
I. Faik Baskaya},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Analog layer extensions for analog/mixed-signal assertion languages},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {66--71},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673252},
doi = {10.1109/VLSI-SOC.2013.6673252},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/UlusSB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VijS13,
author = {Vikas S. Vij and
Kenneth S. Stevens},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Automatic addition of reset in asynchronous sequential control circuits},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {374--379},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673312},
doi = {10.1109/VLSI-SOC.2013.6673312},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/VijS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VourkasSS13,
author = {Ioannis Vourkas and
Dimitrios Stathis and
Georgios Ch. Sirakoulis},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Improved read voltage margins with alternative topologies for memristor-based
crossbar memories},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {336--339},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673304},
doi = {10.1109/VLSI-SOC.2013.6673304},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/VourkasSS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WangCYKTCLWC13,
author = {Po{-}Hao Wang and
Wei{-}Chung Cheng and
Yung{-}Hui Yu and
Tang{-}Chieh Kao and
Chi{-}Lun Tsai and
Pei{-}Yao Chang and
Tay{-}Jyi Lin and
Jinn{-}Shyan Wang and
Tien{-}Fu Chen},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Variation-aware and adaptive-latency accesses for reliable low voltage
caches},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {358--363},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673309},
doi = {10.1109/VLSI-SOC.2013.6673309},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WangCYKTCLWC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/XiangLCF13,
author = {Dong Xiang and
Gang Liu and
Krishnendu Chakrabarty and
Hideo Fujiwara},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Thermal-aware test scheduling for NOC-based 3D integrated circuits},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {96--101},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673257},
doi = {10.1109/VLSI-SOC.2013.6673257},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/XiangLCF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YeknamiA13,
author = {Ali Fazli Yeknami and
Atila Alvandpour},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {A 0.7-V 400-nW fourth-order active-passive {\(\Delta\)}{\(\Sigma\)}
modulator with one active stage},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673235},
doi = {10.1109/VLSI-SOC.2013.6673235},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/YeknamiA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YeknamiA13a,
author = {Ali Fazli Yeknami and
Atila Alvandpour},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {Low-Power Low-Voltage {\(\Delta\)}{\(\Sigma\)} Modulator Using Switched-Capacitor
Passive Filters},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {94--118},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_5},
doi = {10.1007/978-3-319-23799-2\_5},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/YeknamiA13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZamaniED13,
author = {Majid Zamani and
Clemens Eder and
Andreas Demosthenous},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Analog-to-digital converters power dissipation limits of CBSC-based
pipelined},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {352--357},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673308},
doi = {10.1109/VLSI-SOC.2013.6673308},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZamaniED13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZamanzadehJ13,
author = {Sharareh Zamanzadeh and
Ali Jahanian},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Automatic netlist scrambling methodology in {ASIC} design flow to
hinder the reverse engineering},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {52--53},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673245},
doi = {10.1109/VLSI-SOC.2013.6673245},
timestamp = {Sat, 30 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZamanzadehJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhangCDLN13,
author = {Yu Zhang and
Gong Chen and
Qing Dong and
Mingyu Li and
Shigetoshi Nakatake},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Performance-driven {SRAM} macro design with parameterized cell considering
layout-dependent effects},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {156--161},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673268},
doi = {10.1109/VLSI-SOC.2013.6673268},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhangCDLN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhaoKWZRQRC13,
author = {Weisheng Zhao and
Jacques{-}Olivier Klein and
Zhaohao Wang and
Yue Zhang and
Nesrine Ben Romdhane and
Damien Querlioz and
Dafine Ravelosona and
Claude Chappert},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Spin-electronics based logic fabrics},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {174--179},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673271},
doi = {10.1109/VLSI-SOC.2013.6673271},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhaoKWZRQRC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhuGTP13,
author = {Qiuling Zhu and
Navjot Garg and
Yun{-}Ta Tsai and
Kari Pulli},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {An energy efficient time-sharing pyramid pipeline for multi-resolution
computer vision},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {278--281},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673289},
doi = {10.1109/VLSI-SOC.2013.6673289},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhuGTP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2012socs,
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-45073-0},
doi = {10.1007/978-3-642-45073-0},
isbn = {978-3-642-45072-3},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2012socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2013soc,
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
publisher = {{IEEE}},
year = {2013},
url = {https://ieeexplore.ieee.org/xpl/conhome/6662534/proceeding},
isbn = {978-1-4799-0522-5},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2013soc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AsgharRR12,
author = {Sohail Asghar and
Roc{\'{\i}}o del R{\'{\i}}o and
Jos{\'{e}} M. de la Rosa},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A 0.2-to-2MHz BW, 50-to-86dB SNDR, 16-to-22mW flexible 4\({}^{\mbox{th}}\)-order
{\(\Sigma\)}{\(\Delta\)} modulator with DC-to-44MHz tunable center
frequency in 1.2-V 90-nm {CMOS}},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {47--52},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379004},
doi = {10.1109/VLSI-SOC.2012.6379004},
timestamp = {Tue, 06 Sep 2022 16:02:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AsgharRR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BeanatoLMLB12,
author = {Giulia Beanato and
Igor Loi and
Giovanni De Micheli and
Yusuf Leblebici and
Luca Benini},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {3D-LIN: {A} configurable low-latency interconnect for multi-core clusters
with 3D stacked {L1} memory},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {30--35},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379001},
doi = {10.1109/VLSI-SOC.2012.6379001},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BeanatoLMLB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BeanatoLMLB12a,
author = {Giulia Beanato and
Igor Loi and
Giovanni De Micheli and
Yusuf Leblebici and
Luca Benini},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {Configurable Low-Latency Interconnect for Multi-core Clusters},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {107--124},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_6},
doi = {10.1007/978-3-642-45073-0\_6},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BeanatoLMLB12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BelfantiBBHB12,
author = {Sandro Belfanti and
Christian Benkeser and
Karim Badawi and
Qiuting Huang and
Andreas Burg},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Successive interference cancellation for 3G downlink: Algorithm and
{VLSI} architecture},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {279--282},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379046},
doi = {10.1109/VLSI-SOC.2012.6379046},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BelfantiBBHB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BenkeserRH12,
author = {Christian Benkeser and
Christoph Roth and
Qiuting Huang},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Turbo decoder design for high code rates},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {71--75},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379008},
doi = {10.1109/VLSI-SOC.2012.6379008},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BenkeserRH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BezzamKM12,
author = {Ignatius Bezzam and
Shoba Krishnan and
Chakravarthy Mathiazhagan},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Low power SoCs with resonant dynamic logic using inductors for energy
recovery},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {307--310},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379053},
doi = {10.1109/VLSI-SOC.2012.6379053},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BezzamKM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CharaniaCOS12,
author = {Tasreen Charania and
Pierce Chuang and
Ajoy Opal and
Manoj Sachdev},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Suppression of on-chip power supply noise generated by a 64-bit static
logic {ALU} block},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {201--206},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379030},
doi = {10.1109/VLSI-SOC.2012.6379030},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CharaniaCOS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChattopadhyayP12,
author = {Anupam Chattopadhyay and
Goutam Paul},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Exploring security-performance trade-offs during hardware accelerator
design of stream cipher {RC4}},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {251--254},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379039},
doi = {10.1109/VLSI-SOC.2012.6379039},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChattopadhyayP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChoudharyDR12,
author = {Niket K. Choudhary and
Brandon H. Dwiel and
Eric Rotenberg},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A physical design study of fabscalar-generated superscalar cores},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {165--170},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379024},
doi = {10.1109/VLSI-SOC.2012.6379024},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChoudharyDR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ConstantinDAMRAB12,
author = {Jeremy Constantin and
Ahmed Yasir Dogan and
Oskar Andersson and
Pascal Andreas Meinerzhagen and
Joachim Neves Rodrigues and
David Atienza and
Andreas Burg},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {TamaRISC-CS: An ultra-low-power application-specific processor for
compressed sensing},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {159--164},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379023},
doi = {10.1109/VLSI-SOC.2012.6379023},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ConstantinDAMRAB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ConstantinDAMRAB12a,
author = {Jeremy Constantin and
Ahmed Yasir Dogan and
Oskar Andersson and
Pascal Andreas Meinerzhagen and
Joachim Neves Rodrigues and
David Atienza and
Andreas Burg},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories
for Compressed Sensing},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {88--106},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_5},
doi = {10.1007/978-3-642-45073-0\_5},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ConstantinDAMRAB12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CorintoAG12,
author = {Fernando Corinto and
Alon Ascoli and
Marco Gilli},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A novel elementary memristive system},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {76--81},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379009},
doi = {10.1109/VLSI-SOC.2012.6379009},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CorintoAG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DavidBM12,
author = {Radu David and
Paul Bogdan and
Radu Marculescu},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Dynamic power management for multicores: Case study using the intel
{SCC}},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {147--152},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379021},
doi = {10.1109/VLSI-SOC.2012.6379021},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DavidBM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Dutta12,
author = {Avijit Dutta},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Low cost adjacent double error correcting code with complete elimination
of miscorrection within a dispersion window for Multiple Bit Upset
tolerant memory},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {287--290},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379048},
doi = {10.1109/VLSI-SOC.2012.6379048},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Dutta12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FaustZSSM12,
author = {Gregory G. Faust and
Runjie Zhang and
Kevin Skadron and
Mircea R. Stan and
Brett H. Meyer},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {ArchFP: Rapid prototyping of pre-RTL floorplans},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {183--188},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379027},
doi = {10.1109/VLSI-SOC.2012.6379027},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FaustZSSM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GaillardonSBLM12,
author = {Pierre{-}Emmanuel Gaillardon and
Davide Sacchetto and
Shashikanth Bobba and
Yusuf Leblebici and
Giovanni De Micheli},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {{GMS:} Generic memristive structure for non-volatile FPGAs},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {94--98},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379012},
doi = {10.1109/VLSI-SOC.2012.6379012},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GaillardonSBLM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GaoAS12,
author = {Ligang Gao and
Fabien Alibart and
Dmitri B. Strukov},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Analog-input analog-weight dot-product operation with Ag/a-Si/Pt memristive
devices},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {88--93},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379011},
doi = {10.1109/VLSI-SOC.2012.6379011},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GaoAS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Gimmler-DumontBW12,
author = {Christina Gimmler{-}Dumont and
Christian Brehm and
Norbert Wehn},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Reliability study on system memories of an iterative {MIMO-BICM} system},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {255--258},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379040},
doi = {10.1109/VLSI-SOC.2012.6379040},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Gimmler-DumontBW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GreisenESHG12,
author = {Pierre Greisen and
Richard Emler and
Michael Schaffner and
Simon Heinzle and
Frank K. G{\"{u}}rkaynak},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A general-transformation {EWA} view rendering engine for 1080p video
in 130 nm {CMOS}},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {105--110},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379014},
doi = {10.1109/VLSI-SOC.2012.6379014},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GreisenESHG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GreisenSLMHGS12,
author = {Pierre Greisen and
Michael Schaffner and
Danny Luu and
Val Mikos and
Simon Heinzle and
Frank K. G{\"{u}}rkaynak and
Aljoscha Smolic},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {Spatially-Varying Image Warping: Evaluations and {VLSI} Implementations},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {64--87},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_4},
doi = {10.1007/978-3-642-45073-0\_4},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GreisenSLMHGS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GrissomOPPDLB12,
author = {Daniel T. Grissom and
Kenneth O'Neal and
Benjamin Preciado and
Hiral Patel and
Robert Doherty and
Nick Liao and
Philip Brisk},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A digital microfluidic biochip synthesis framework},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {177--182},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379026},
doi = {10.1109/VLSI-SOC.2012.6379026},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GrissomOPPDLB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GuarM12,
author = {Abhishek Guar and
Hamid Mahmoodi},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Impact of technology scaling on performance of domino logic in nano-scale
{CMOS}},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {295--298},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379050},
doi = {10.1109/VLSI-SOC.2012.6379050},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GuarM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Guthaus12,
author = {Matthew R. Guthaus},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Welcome from the general chair},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6378990},
doi = {10.1109/VLSI-SOC.2012.6378990},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Guthaus12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HafeezDS12,
author = {K. T. Hafeez and
Ashudeb Dutta and
Shiv Govind Singh},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Efficient adaptive switch design for charge pumps in micro-scale energy
harvesting},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {311--314},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379054},
doi = {10.1109/VLSI-SOC.2012.6379054},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HafeezDS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JungKLYK12,
author = {Jongpil Jung and
Kyungsu Kang and
Jae{-}Jin Lee and
Youngjun Yoon and
Chong{-}Min Kyung},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Cost-effective {TSV} redundancy configuration},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {263--266},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379042},
doi = {10.1109/VLSI-SOC.2012.6379042},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JungKLYK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KangBM12,
author = {Kyungsu Kang and
Luca Benini and
Giovanni De Micheli},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A high-throughput and low-latency interconnection network for multi-core
Clusters with 3-D stacked {L2} tightly-coupled data memory},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {283--286},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379047},
doi = {10.1109/VLSI-SOC.2012.6379047},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KangBM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KiaA12,
author = {Hamed Sajjadi Kia and
Cristinel Ababei},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A new reliability evaluation methodology and its application to network-on-chip
routers},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {259--262},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379041},
doi = {10.1109/VLSI-SOC.2012.6379041},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KiaA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimG12,
author = {Seokjoong Kim and
Matthew R. Guthaus},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Dynamic voltage scaling for SEU-tolerance in low-power memories},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {207--212},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379031},
doi = {10.1109/VLSI-SOC.2012.6379031},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimG12a,
author = {Seokjoong Kim and
Matthew R. Guthaus},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array
Architecture},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {181--195},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_10},
doi = {10.1007/978-3-642-45073-0\_10},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimG12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KologeskiCKC12,
author = {Anelise Kologeski and
Caroline Concatto and
Fernanda Lima Kastensmidt and
Luigi Carro},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {{ATARDS:} An adaptive fault-tolerant strategy to cope with massive
defects in Network-on-Chip interconnections},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {24--29},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379000},
doi = {10.1109/VLSI-SOC.2012.6379000},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KologeskiCKC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KologeskiCKC12a,
author = {Anelise Kologeski and
Caroline Concatto and
Fernanda Lima Kastensmidt and
Luigi Carro},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {Fault-Tolerant Techniques to Manage Yield and Power Constraints in
Network-on-Chip Interconnections},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {144--161},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_8},
doi = {10.1007/978-3-642-45073-0\_8},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KologeskiCKC12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MadhavanS12,
author = {Advait Madhavan and
Dmitri B. Strukov},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Mapping of image and network processing tasks on high-throughput {CMOL}
{FPGA} circuits},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {82--87},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379010},
doi = {10.1109/VLSI-SOC.2012.6379010},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MadhavanS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MahmoodPLM12,
author = {Haroon Mahmood and
Massimo Poncino and
Mirko Loghi and
Enrico Macii},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Aging-aware caches with graceful degradation of performance},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {237--242},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379036},
doi = {10.1109/VLSI-SOC.2012.6379036},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MahmoodPLM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Mahmoodi12,
author = {Hamid Mahmoodi},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Reliability enhancement of power gating transistor under time dependent
dielectric breakdown},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {189--194},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379028},
doi = {10.1109/VLSI-SOC.2012.6379028},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Mahmoodi12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MatsumotoOF12,
author = {Takeshi Matsumoto and
Shohei Ono and
Masahiro Fujita},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {An efficient method to localize and correct bugs in high-level designs
using counterexamples and potential dependence},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {291--294},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379049},
doi = {10.1109/VLSI-SOC.2012.6379049},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MatsumotoOF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MengKHC12,
author = {Jie Meng and
Fulya Kaplan and
Ming{-}yu Hsieh and
Ayse K. Coskun},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Topology-aware reliability optimization for multiprocessor systems},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {243--246},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379037},
doi = {10.1109/VLSI-SOC.2012.6379037},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MengKHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MinwegenAA12,
author = {Andreas Minwegen and
Dominik Auras and
Gerd Ascheid},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A multimode decision-directed channel estimation {ASIC} for {MIMO-OFDM}},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {65--70},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379007},
doi = {10.1109/VLSI-SOC.2012.6379007},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MinwegenAA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MottenCP12,
author = {Andy Motten and
Luc Claesen and
Yun Pan},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Trinocular disparity processor using a hierarchic classification structure},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {247--250},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379038},
doi = {10.1109/VLSI-SOC.2012.6379038},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MottenCP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MottenCP12a,
author = {Andy Motten and
Luc Claesen and
Yun Pan},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {Trinocular Stereo Vision Using a Multi Level Hierarchical Classification
Structure},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {45--63},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_3},
doi = {10.1007/978-3-642-45073-0\_3},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MottenCP12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuehlberghuberKFP12,
author = {Michael Muehlberghuber and
Christoph Keller and
Norbert Felber and
Christian Pendl},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {100 Gbit/s authenticated encryption based on quantum key distribution},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {123--128},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379017},
doi = {10.1109/VLSI-SOC.2012.6379017},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MuehlberghuberKFP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MuehlberghuberKGF12,
author = {Michael Muehlberghuber and
Christoph Keller and
Frank K. G{\"{u}}rkaynak and
Norbert Felber},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {FPGA-Based High-Speed Authenticated Encryption System},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {1--20},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_1},
doi = {10.1007/978-3-642-45073-0\_1},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MuehlberghuberKGF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NishitaniIAIKS12,
author = {Yuki Nishitani and
Kazuki Inoue and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Evaluation of fault tolerant technique based on homogeneous {FPGA}
architecture},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {225--230},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379034},
doi = {10.1109/VLSI-SOC.2012.6379034},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NishitaniIAIKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NunnaMYM12,
author = {Krishna Chaitanya Nunna and
Farhad Mehdipour and
Masayoshi Yoshimura and
Kazuaki J. Murakami},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Methodology for early estimation of hierarchical routing resources
in 3D FPGAs},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {213--218},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379032},
doi = {10.1109/VLSI-SOC.2012.6379032},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NunnaMYM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ONealGB12,
author = {Kenneth O'Neal and
Daniel T. Grissom and
Philip Brisk},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Force-Directed List Scheduling for Digital Microfluidic Biochips},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {7--11},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6378997},
doi = {10.1109/VLSI-SOC.2012.6378997},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ONealGB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PappasKSV12,
author = {Ilias Pappas and
Vasilios Kalenteridis and
Stylianos Siskos and
Spiridon Vlassis},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A complete over-current/short-circuit protection system for Low-Drop
Out regulators},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {303--306},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379052},
doi = {10.1109/VLSI-SOC.2012.6379052},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PappasKSV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParsanS12,
author = {Farhad Alibeygi Parsan and
Scott C. Smith},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {{CMOS} implementation of static threshold gates with hysteresis: {A}
new approach},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {41--45},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379003},
doi = {10.1109/VLSI-SOC.2012.6379003},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ParsanS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParsanS12a,
author = {Farhad Alibeygi Parsan and
Scott C. Smith},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {{CMOS} Implementation of Threshold Gates with Hysteresis},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {196--216},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_11},
doi = {10.1007/978-3-642-45073-0\_11},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ParsanS12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PatelF12,
author = {Ravi Patel and
Eby G. Friedman},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Arithmetic encoding for memristive multi-bit storage},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {99--104},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379013},
doi = {10.1109/VLSI-SOC.2012.6379013},
timestamp = {Mon, 07 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PatelF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PendyalaK12,
author = {Shilpa Pendyala and
Srinivas Katkoori},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Interval arithmetic based input vector control for {RTL} subthreshold
leakage minimization},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {141--146},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379020},
doi = {10.1109/VLSI-SOC.2012.6379020},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PendyalaK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PietriDRRO12,
author = {Stefano Pietri and
Chris Dao and
Juxiang Ren and
Jehoda Refaeli and
Alfredo Olmos},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Safety oriented automotive {MCU} power management},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {36--40},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379002},
doi = {10.1109/VLSI-SOC.2012.6379002},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PietriDRRO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RabBT12,
author = {Muhammad Tauseef Rab and
Asad Amin Bawa and
Nur A. Touba},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Using asymmetric layer repair capability to reduce the cost of yield
enhancement in 3D stacked memories},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {195--200},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379029},
doi = {10.1109/VLSI-SOC.2012.6379029},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RabBT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RavishankarKA12,
author = {Chirag Ravishankar and
Andrew A. Kennings and
Jason Helge Anderson},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {{FPGA} power reduction by guarded evaluation considering physical
information},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {271--274},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379044},
doi = {10.1109/VLSI-SOC.2012.6379044},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RavishankarKA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SabenaRS12,
author = {Davide Sabena and
Matteo Sonza Reorda and
Luca Sterpone},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {On the optimized generation of Software-Based Self-Test programs for
{VLIW} processors},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {129--134},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379018},
doi = {10.1109/VLSI-SOC.2012.6379018},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SabenaRS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SabenaSR12,
author = {Davide Sabena and
Luca Sterpone and
Matteo Sonza Reorda},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {On the Automatic Generation of Software-Based Self-Test Programs for
Functional Test and Diagnosis of {VLIW} Processors},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {162--180},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_9},
doi = {10.1007/978-3-642-45073-0\_9},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SabenaSR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SankaranarayananG12,
author = {Rajsaktish Sankaranarayanan and
Matthew R. Guthaus},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A single-VDD ultra-low energy sub-threshold {FPGA}},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {219--224},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379033},
doi = {10.1109/VLSI-SOC.2012.6379033},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SankaranarayananG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ShahNS12,
author = {Jaspal Singh Shah and
David Nairn and
Manoj Sachdev},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A soft error robust 32kb {SRAM} macro featuring access transistor-less
8T cell in 65-nm},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {275--278},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379045},
doi = {10.1109/VLSI-SOC.2012.6379045},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ShahNS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SharmaY12,
author = {Surya Sharma and
Trond Ytterdal},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Low noise front-end amplifier design for medical ultrasound imaging
applications},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {12--17},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6378998},
doi = {10.1109/VLSI-SOC.2012.6378998},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SharmaY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SilvaFW12,
author = {Victor Frederico Silva and
Cantidio de Oliveira Fontes and
Fl{\'{a}}vio Rech Wagner},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {The impact of synchronization in message passing while scaling multi-core
MPSoC systems},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {267--270},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379043},
doi = {10.1109/VLSI-SOC.2012.6379043},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SilvaFW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SkinnerHG12,
author = {Haven Blake Skinner and
Xuchu Hu and
Matthew R. Guthaus},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Harmonic resonant clocking},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {59--64},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379006},
doi = {10.1109/VLSI-SOC.2012.6379006},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SkinnerHG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SpignaSJMF12,
author = {Neil Di Spigna and
Daniel Schinke and
Srikant Jayanti and
Veena Misra and
Paul D. Franzon},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A novel double floating-gate unified memory device},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {53--58},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379005},
doi = {10.1109/VLSI-SOC.2012.6379005},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SpignaSJMF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SpignaSJMF12a,
author = {Neil Di Spigna and
Daniel Schinke and
Srikant Jayanti and
Veena Misra and
Paul D. Franzon},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {Simulation and Experimental Characterization of a Unified Memory Device
with Two Floating-Gates},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {217--233},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_12},
doi = {10.1007/978-3-642-45073-0\_12},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SpignaSJMF12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SteinhorstH12,
author = {Sebastian Steinhorst and
Lars Hedrich},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Equivalence checking of nonlinear analog circuits for hierarchical
{AMS} System Verification},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {135--140},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379019},
doi = {10.1109/VLSI-SOC.2012.6379019},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SteinhorstH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TabkhiS12,
author = {Hamed Tabkhi and
Gunar Schirner},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {{ARRA:} Application-guided reliability-enhanced registerfile architecture
for embedded processors},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {299--302},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379051},
doi = {10.1109/VLSI-SOC.2012.6379051},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TabkhiS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ThieleVMRB12,
author = {Cristiano Thiele and
Bruno Boessio Vizzotto and
Andr{\'{e}} L. M. Martinez and
Vagner Santos Da Rosa and
Sergio Bampi},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A low-cost and high efficiency entropy encoder architecture for {H.264/AVC}},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {117--122},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379016},
doi = {10.1109/VLSI-SOC.2012.6379016},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ThieleVMRB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsepurovBDJRT12,
author = {Anton Tsepurov and
Gunter Bartsch and
Rainer Dorsch and
Maksim Jenihhin and
Jaan Raik and
Valentin Tihhomirov},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A scalable model based {RTL} framework zamiaCAD for static analysis},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {171--176},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379025},
doi = {10.1109/VLSI-SOC.2012.6379025},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TsepurovBDJRT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WuL12,
author = {Bin Wu and
Peng Li},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Load-aware stochastic feedback control for {DVFS} with tight performance
guarantee},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {231--236},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379035},
doi = {10.1109/VLSI-SOC.2012.6379035},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WuL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/XiaoB12,
author = {Zhibin Xiao and
Bevan M. Baas},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {A hexagonal shaped processor and interconnect topology for tightly-tiled
many-core architecture},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {153--158},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379022},
doi = {10.1109/VLSI-SOC.2012.6379022},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/XiaoB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/XiaoB12a,
author = {Zhibin Xiao and
Bevan M. Baas},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {A Hexagonal Processor and Interconnect Topology for Many-Core Architecture
with Dense On-Chip Networks},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {125--143},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_7},
doi = {10.1007/978-3-642-45073-0\_7},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/XiaoB12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhengSK12,
author = {Le Zheng and
Sangho Shin and
Sung{-}Mo Steve Kang},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Design of a neural stimulator system with closed-loop charge cancellation},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {1--6},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6378996},
doi = {10.1109/VLSI-SOC.2012.6378996},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhengSK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhuLC12,
author = {Mingyang Zhu and
Jinho Lee and
Kiyoung Choi},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {An adaptive routing algorithm for 3D mesh NoC with limited vertical
bandwidth},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {18--23},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6378999},
doi = {10.1109/VLSI-SOC.2012.6378999},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhuLC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhuPF12,
author = {Qiuling Zhu and
Larry T. Pileggi and
Franz Franchetti},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Cost-effective smart memory implementation for parallel backprojection
in computed tomography},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {111--116},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379015},
doi = {10.1109/VLSI-SOC.2012.6379015},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhuPF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhuPF12a,
author = {Qiuling Zhu and
Larry T. Pileggi and
Franz Franchetti},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {A Smart Memory Accelerated Computed Tomography Parallel Backprojection},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {21--44},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_2},
doi = {10.1007/978-3-642-45073-0\_2},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhuPF12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2010socs,
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-28566-0},
doi = {10.1007/978-3-642-28566-0},
isbn = {978-3-642-28565-3},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2010socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2011socs,
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-32770-4},
doi = {10.1007/978-3-642-32770-4},
isbn = {978-3-642-32769-8},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2011socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2012soc,
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
publisher = {{IEEE}},
year = {2012},
url = {https://ieeexplore.ieee.org/xpl/conhome/6366003/proceeding},
isbn = {978-1-4673-2657-5},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2012soc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/0001M11,
author = {Huan Chen and
Jo{\~{a}}o Marques{-}Silva},
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {Improvements to Satisfiability-Based Boolean Function Bi-Decomposition},
booktitle = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
pages = {52--72},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-32770-4\_4},
doi = {10.1007/978-3-642-32770-4\_4},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/0001M11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AksoyCFM11,
author = {Levent Aksoy and
Eduardo Costa and
Paulo F. Flores and
Jos{\'{e}} Monteiro},
title = {A hybrid algorithm for the optimization of area and delay in linear
{DSP} transforms},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {148--153},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081637},
doi = {10.1109/VLSISOC.2011.6081637},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AksoyCFM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AksoyCFM11a,
author = {Levent Aksoy and
Eduardo A. C. da Costa and
Paulo F. Flores and
Jos{\'{e}} Monteiro},
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {Multiplierless Design of Linear {DSP} Transforms},
booktitle = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
pages = {73--93},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-32770-4\_5},
doi = {10.1007/978-3-642-32770-4\_5},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AksoyCFM11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ArtesASHC11,
author = {Antonio Art{\'{e}}s and
Jos{\'{e}} Luis Ayala and
Ashoka Visweswara Sathanur and
Jos Huisken and
Francky Catthoor},
title = {Run-time self-tuning banked loop buffer architecture for power optimization
of dynamic workload applications},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {136--141},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081635},
doi = {10.1109/VLSISOC.2011.6081635},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ArtesASHC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BeuxTON11,
author = {S{\'{e}}bastien Le Beux and
Jelena Trajkovic and
Ian O'Connor and
Gabriela Nicolescu},
title = {Layout guidelines for 3D architectures including Optical Ring Network-on-Chip
(ORNoC)},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {242--247},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081645},
doi = {10.1109/VLSISOC.2011.6081645},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BeuxTON11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BontziosDH11,
author = {Yiorgos I. Bontzios and
Michael G. Dimopoulos and
Alkis A. Hatzopoulos},
title = {Prospects of 3D inductors on through silicon vias processes for 3D
ICs},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {90--93},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081657},
doi = {10.1109/VLSISOC.2011.6081657},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BontziosDH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CamposFF11,
author = {Marcel Veloso Campos and
Andr{\'{e}} Lu{\'{\i}}s Fortunato and
Carlos Alberto dos Reis Filho},
title = {New 12-bit source-follower track-and-hold circuit suitable for high-speed
applications},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {82--85},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081655},
doi = {10.1109/VLSISOC.2011.6081655},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CamposFF11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CenniSS11,
author = {Fabio Cenni and
Serge Scotti and
Emmanuel Simeu},
title = {SystemC {AMS} behavioral modeling of a {CMOS} video sensor},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {380--385},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081614},
doi = {10.1109/VLSISOC.2011.6081614},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CenniSS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChaiSXLZC11,
author = {Yang Chai and
Minghui Sun and
Zhiyong Xiao and
Yuan Li and
Min Zhang and
Philip C. H. Chan},
title = {Towards future {VLSI} interconnects using aligned carbon nanotubes},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {248--253},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081646},
doi = {10.1109/VLSISOC.2011.6081646},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChaiSXLZC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChattopadhyayR11,
author = {Anupam Chattopadhyay and
Zoltan Endre Rakosi},
title = {Combinational logic synthesis for material implication},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {200--203},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081665},
doi = {10.1109/VLSISOC.2011.6081665},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChattopadhyayR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChenM11,
author = {Huan Chen and
Jo{\~{a}}o Marques{-}Silva},
title = {Improvements to satisfiability-based boolean function bi-decomposition},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {142--147},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081636},
doi = {10.1109/VLSISOC.2011.6081636},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChenM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ConcattoKCKPS11,
author = {Caroline Concatto and
Anelise Kologeski and
Luigi Carro and
Fernanda Lima Kastensmidt and
Gianluca Palermo and
Cristina Silvano},
title = {Two-levels of adaptive buffer for virtual channel router in NoCs},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {302--307},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081596},
doi = {10.1109/VLSISOC.2011.6081596},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ConcattoKCKPS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DahirMY11,
author = {Nizar Dahir and
Terrence S. T. Mak and
Alex Yakovlev},
title = {Communication centric on-chip power grid models for networks-on-chip},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {180--183},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081671},
doi = {10.1109/VLSISOC.2011.6081671},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/DahirMY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DhootMCC11,
author = {Charvi Dhoot and
Vincent John Mooney and
Shubhajit Roy Chowdhury and
Lap{-}Pui Chau},
title = {Fault tolerant design for low power hierarchical search motion estimation
algorithms},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {266--271},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081649},
doi = {10.1109/VLSISOC.2011.6081649},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/DhootMCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DobesCY11,
author = {Josef Dobes and
David Cern{\'{y}} and
Abhimanyu Yadav},
title = {A more efficient arrangement of the sparse {LU} factorization for
the large-scale circuit analysis},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {416--421},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081619},
doi = {10.1109/VLSISOC.2011.6081619},
timestamp = {Fri, 28 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DobesCY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EbrahimiDLPT11,
author = {Masoumeh Ebrahimi and
Masoud Daneshtalab and
Pasi Liljeberg and
Juha Plosila and
Hannu Tenhunen},
title = {Agent-based on-chip network using efficient selection method},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {284--289},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081593},
doi = {10.1109/VLSISOC.2011.6081593},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/EbrahimiDLPT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FrantzLO11,
author = {Felipe Frantz and
Lioua Labrak and
Ian O'Connor},
title = {3D-IC floorplanning: Applying meta-optimization to improve performance},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {404--409},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081618},
doi = {10.1109/VLSISOC.2011.6081618},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FrantzLO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FummiQS11,
author = {Franco Fummi and
Davide Quaglia and
Francesco Stefanni},
title = {Communication-aware middleware-based design-space exploration for
Networked Embedded Systems},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {168--171},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081668},
doi = {10.1109/VLSISOC.2011.6081668},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FummiQS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Garcia-SanchezR11,
author = {J. Gerardo Garc{\'{\i}}a{-}S{\'{a}}nchez and
Jos{\'{e}} M. de la Rosa},
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade
2-2 Sigma-Delta Modulators for Wideband Telecom},
booktitle = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
pages = {124--143},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-32770-4\_8},
doi = {10.1007/978-3-642-32770-4\_8},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Garcia-SanchezR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Garcia-SanchezU11,
author = {J. Gerardo Garc{\'{\i}}a{-}S{\'{a}}nchez and
Jos{\'{e}} M. de la Rosa},
title = {Multirate hybrid continuous-time/discrete-time cascade 2-2 {\(\Sigma\)}{\(\Delta\)}
modulator for wideband telecom},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {314--318},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081599},
doi = {10.1109/VLSISOC.2011.6081599},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Garcia-SanchezU11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GhiribaldiLFB11,
author = {Alberto Ghiribaldi and
Daniele Ludovici and
Michele Favalli and
Davide Bertozzi},
title = {System-level infrastructure for boot-time testing and configuration
of networks-on-chip with programmable routing logic},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {308--313},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081597},
doi = {10.1109/VLSISOC.2011.6081597},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GhiribaldiLFB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HuLJLZL11,
author = {Wenmin Hu and
Zhonghai Lu and
Axel Jantsch and
Hengzhu Liu and
Botao Zhang and
Dongpei Liu},
title = {Network-on-Chip multicasting with low latency path setup},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {290--295},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081594},
doi = {10.1109/VLSISOC.2011.6081594},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HuLJLZL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HuangYLDCC11,
author = {Tzu{-}Chi Huang and
Yao{-}Yi Yang and
Yu{-}Huei Lee and
Ming{-}Jhe Du and
Shih{-}Hsien Cheng and
Ke{-}Horng Chen},
title = {A battery-free energy harvesting system with the switch capacitor
sampler {(SCS)} technique for high power factor in smart meter applications},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {359--362},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081609},
doi = {10.1109/VLSISOC.2011.6081609},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HuangYLDCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/IidaIAS11,
author = {Masahiro Iida and
Kazuki Inoue and
Motoki Amagasaki and
Toshinori Sueyoshi},
title = {An easily testable routing architecture of {FPGA}},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {106--109},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081661},
doi = {10.1109/VLSISOC.2011.6081661},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/IidaIAS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/InoueK11,
author = {Keisuke Inoue and
Mineo Kaneko},
title = {Early planning for RT-level delay insertion during clock skew-aware
register binding},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {154--159},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081638},
doi = {10.1109/VLSISOC.2011.6081638},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/InoueK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JhengCRQ11,
author = {Hong{-}Yuan Jheng and
Yen{-}Hsiang Chen and
Shanq{-}Jang Ruan and
Ziming Qi},
title = {{FPGA} implementation of high sampling rate in-car non-stationary
noise cancellation based on adaptive Wiener filter},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {114--117},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081652},
doi = {10.1109/VLSISOC.2011.6081652},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JhengCRQ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JiangWSHM11,
author = {Jianfei Jiang and
Xu Wang and
Wei{-}Guang Sheng and
Wei{-}Feng He and
Zhi{-}Gang Mao},
title = {A clock-less transceiver for global interconnect},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {184--187},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081672},
doi = {10.1109/VLSISOC.2011.6081672},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JiangWSHM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JinLHM11,
author = {Wei Jin and
Sheng Lu and
Weifeng He and
Zhigang Mao},
title = {A 230mV 8-bit sub-threshold microprocessor for wireless sensor network},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {126--129},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081633},
doi = {10.1109/VLSISOC.2011.6081633},
timestamp = {Thu, 15 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JinLHM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JinLHM11a,
author = {Wei Jin and
Sheng Lu and
Weifeng He and
Zhigang Mao},
title = {Robust design of sub-threshold flip-flop cells for wireless sensor
network},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {440--443},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081623},
doi = {10.1109/VLSISOC.2011.6081623},
timestamp = {Thu, 15 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JinLHM11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JingHM11,
author = {Naifeng Jing and
Weifeng He and
Zhigang Mao},
title = {A general statistical estimation for application mapping in Network-on-Chip},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {172--175},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081669},
doi = {10.1109/VLSISOC.2011.6081669},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JingHM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JuangPK11,
author = {Tso{-}Bing Juang and
Hsin{-}Hao Peng and
Chao{-}Tsung Kuo},
title = {Area-efficient 3-input decimal adders using simplified carry and sum
vectors},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {25--30},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081625},
doi = {10.1109/VLSISOC.2011.6081625},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JuangPK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KhanKK11,
author = {Asim Khan and
Kyungsu Kang and
Chong{-}Min Kyung},
title = {Exploiting maximum throughput in 3D multicore architectures with stacked
{NUCA} cache},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {130--135},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081634},
doi = {10.1109/VLSISOC.2011.6081634},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KhanKK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KiLST11,
author = {Wing{-}Hung Ki and
Yan Lu and
Feng Su and
Chi{-}Ying Tsui},
title = {Design and analysis of on-chip charge pumps for micro-power energy
harvesting applications},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {374--379},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081612},
doi = {10.1109/VLSISOC.2011.6081612},
timestamp = {Thu, 14 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/KiLST11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KiLST11a,
author = {Wing{-}Hung Ki and
Yan Lu and
Feng Su and
Chi{-}Ying Tsui},
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power
Energy Harvesting Applications},
booktitle = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
pages = {158--186},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-32770-4\_10},
doi = {10.1007/978-3-642-32770-4\_10},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KiLST11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimG11,
author = {Seokjoong Kim and
Matthew R. Guthaus},
title = {SNM-aware power reduction and reliability improvement in 45nm SRAMs},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {204--207},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081666},
doi = {10.1109/VLSISOC.2011.6081666},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimLLC11,
author = {Jeong Hoon Kim and
In Jung Lyu and
Hyun June Lyu and
Jun Rim Choi},
title = {Minimizing redundancy-based motion estimation design for high-definition},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {110--113},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081662},
doi = {10.1109/VLSISOC.2011.6081662},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimLLC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Kuroda11,
author = {Tadahiro Kuroda},
title = {ThruChip interface {(TCI)} for 3D networks on chip},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {238--241},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081644},
doi = {10.1109/VLSISOC.2011.6081644},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Kuroda11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KwanSLLTTCGHZWHTMNTT11,
author = {Alex Man Ho Kwan and
Sichao Song and
Xing Lu and
Lei Lu and
Ying{-}Khai Teh and
Ying Fei Teh and
Eddie Wing Cheung Chong and
Yan Gao and
William Hau and
Fan Zeng and
Man Wong and
Chunmei Huang and
Akira Taniyama and
Yoshihide Makino and
So Nishino and
Toshiyuki Tsuchiya and
Osamu Tabata},
title = {Designs for improving the performance of an electro-thermal in-plane
actuator},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {220--225},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081641},
doi = {10.1109/VLSISOC.2011.6081641},
timestamp = {Tue, 24 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KwanSLLTTCGHZWHTMNTT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LamMP11,
author = {Kai{-}Pui Lam and
Terrence S. T. Mak and
Chi{-}Sang Poon},
title = {Comparative {ODE} benchmarking of unidirectional and bidirectional
{DP} networks for 3D-IC},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {98--101},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081659},
doi = {10.1109/VLSISOC.2011.6081659},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LamMP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LamMP11a,
author = {Kai{-}Pui Lam and
Terrence S. T. Mak and
Chi{-}Sang Poon},
title = {Cycle avoidance in 2D/3D bidirectional graphs using shortest-path
dynamic programming network},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {354--358},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081607},
doi = {10.1109/VLSISOC.2011.6081607},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LamMP11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiXX11,
author = {Jianhua Li and
Chun Jason Xue and
Yinlong Xu},
title = {{STT-RAM} based energy-efficiency hybrid cache for CMPs},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {31--36},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081626},
doi = {10.1109/VLSISOC.2011.6081626},
timestamp = {Mon, 07 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LiXX11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LinnDCY11,
author = {Myat Thu Linn Aung and
Anh{-}Tuan Do and
Shoushun Chen and
Kiat Seng Yeo},
title = {Adaptive priority toggle asynchronous tree arbiter for AER-based image
sensor},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {66--71},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081631},
doi = {10.1109/VLSISOC.2011.6081631},
timestamp = {Tue, 07 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LinnDCY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiuCFZ11,
author = {Jialiang Liu and
Xinhua Chen and
Yibo Fan and
Xiaoyang Zeng},
title = {A full-mode {FME} {VLSI} architecture based on 8{\texttimes}8/4{\texttimes}4
adaptive Hadamard Transform for {QFHD} {H.264/AVC} encoder},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {434--439},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081622},
doi = {10.1109/VLSISOC.2011.6081622},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LiuCFZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LiuSWW11,
author = {Haotian Liu and
Fengrui Shi and
Yuanzhe Wang and
Ngai Wong},
title = {Frequency-domain transient analysis of multitime partial differential
equation systems},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {160--163},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081663},
doi = {10.1109/VLSISOC.2011.6081663},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LiuSWW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LopichD11,
author = {Alexey Lopich and
Piotr Dudek},
title = {Architecture and design of a programmable 3D-integrated cellular processor
array for image processing},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {349--353},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081606},
doi = {10.1109/VLSISOC.2011.6081606},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LopichD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MaHM11,
author = {Qingyun Ma and
Mohammad Rafiqul Haider and
Yehia Massoud},
title = {A low-loss rectifier unit for inductive-powering of biomedical implants},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {86--89},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081656},
doi = {10.1109/VLSISOC.2011.6081656},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MaHM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MalikMHG11,
author = {Jamshaid Sarwar Malik and
Jameel Nawaz Malik and
Ahmed Hemani and
Nasirud Din Gohar},
title = {Generating high tail accuracy Gaussian Random Numbers in hardware
using central limit theorem},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {60--65},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081630},
doi = {10.1109/VLSISOC.2011.6081630},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MalikMHG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ManyamCW11,
author = {Venkata Narasimha Manyam and
Dhurv Chhetri and
J. Jacob Wikner},
title = {Clockless asynchronous delta modulator based {ADC} for smart dust
applications},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {331--336},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081602},
doi = {10.1109/VLSISOC.2011.6081602},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ManyamCW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MeherP11,
author = {Pramod Kumar Meher and
Yu Pan},
title = {MCM-based implementation of block {FIR} filters for high-speed and
low-power applications},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {118--121},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081653},
doi = {10.1109/VLSISOC.2011.6081653},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MeherP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MeherP11a,
author = {Pramod Kumar Meher and
Sang Yoon Park},
title = {High-throughput pipelined realization of adaptive {FIR} filter based
on distributed arithmetic},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {428--433},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081621},
doi = {10.1109/VLSISOC.2011.6081621},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MeherP11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MingZZ11,
author = {Xin Ming and
Ze{-}kun Zhou and
Bo Zhang},
title = {A low-power ultra-fast capacitor-less {LDO} with advanced dynamic
push-pull techniques},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {54--59},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081629},
doi = {10.1109/VLSISOC.2011.6081629},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MingZZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MingZZ11a,
author = {Xin Ming and
Ze{-}kun Zhou and
Bo Zhang},
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {A Low-Power Ultra-Fast Capacitor-Less {LDO} with Advanced Dynamic
Push-Pull Techniques},
booktitle = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
pages = {34--51},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-32770-4\_3},
doi = {10.1007/978-3-642-32770-4\_3},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MingZZ11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MiteaMH11,
author = {Oliver Mitea and
Markus Meissner and
Lars Hedrich},
title = {Topology synthesis of analog circuits with yield optimization and
evaluation using pareto fronts},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {78--81},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081651},
doi = {10.1109/VLSISOC.2011.6081651},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MiteaMH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MolterSH11,
author = {H. Gregor Molter and
Andr{\'{e}} Seffrin and
Sorin A. Huss},
title = {State space optimization within the {DEVS} model of computation for
timing efficiency},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {422--427},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081620},
doi = {10.1109/VLSISOC.2011.6081620},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MolterSH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MullaneO11,
author = {Brendan Mullane and
Vincent O'Brien},
title = {A high performance band-pass {DAC} architecture and design targeting
a low voltage silicon process},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {325--330},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081601},
doi = {10.1109/VLSISOC.2011.6081601},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MullaneO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MullaneO11a,
author = {Brendan Mullane and
Vincent O'Brien},
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {A 100dB {SFDR} 0.5V pk-pk Band-Pass {DAC} Implemented on a Low Voltage
{CMOS} Process},
booktitle = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
pages = {144--157},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-32770-4\_9},
doi = {10.1007/978-3-642-32770-4\_9},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MullaneO11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NakazawaIS11,
author = {Hirokazu Nakazawa and
Makoto Ishida and
Kazuaki Sawada},
title = {Multimodal proton and fluorescence image sensor for bio applications},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {5--9},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081603},
doi = {10.1109/VLSISOC.2011.6081603},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NakazawaIS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NarayananDCPS11,
author = {Surya Narayanan and
Ludovic Devaux and
Daniel Chillet and
S{\'{e}}bastien Pillement and
Ioannis Sourdis},
title = {Communication service for hardware tasks executed on dynamic and partial
reconfigurable resources},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {196--199},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081664},
doi = {10.1109/VLSISOC.2011.6081664},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NarayananDCPS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NodaKISTTTKFO11,
author = {Toshihiko Noda and
Takuya Kitao and
Takasuke Ito and
Kiyotaka Sasagawa and
Takashi Tokuda and
Yasuo Terasawa and
Hiroyuki Tashiro and
Hiroyuki Kanda and
Takashi Fujikado and
Jun Ohta},
title = {Fabrication of a flexible neural interface device with CMOS-based
smart electrodes},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {10--14},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081608},
doi = {10.1109/VLSISOC.2011.6081608},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NodaKISTTTKFO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PamunuwaGWJ11,
author = {Dinesh Pamunuwa and
Matthew Grange and
Roshan Weerasekera and
Axel Jantsch},
title = {3-D integration and the limits of silicon computation},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {343--348},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081605},
doi = {10.1109/VLSISOC.2011.6081605},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PamunuwaGWJ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PlyaskinH11,
author = {Roman Plyaskin and
Andreas Herkersdorf},
title = {Context-aware compiled simulation of out-of-order processor behavior
based on atomic traces},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {386--391},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081615},
doi = {10.1109/VLSISOC.2011.6081615},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PlyaskinH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PuthalSGL11,
author = {Manas Kumar Puthal and
Virendra Singh and
Manoj Singh Gaur and
Vijay Laxmi},
title = {C-Routing: An adaptive hierarchical NoC routing methodology},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {392--397},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081616},
doi = {10.1109/VLSISOC.2011.6081616},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PuthalSGL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/QianTT11,
author = {Zhiliang Qian and
Ying Fei Teh and
Chi{-}Ying Tsui},
title = {A fault-tolerant network-on-chip design using dynamic reconfiguration
of partial-faulty routing resources},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {192--195},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081674},
doi = {10.1109/VLSISOC.2011.6081674},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/QianTT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RovedaLSCAQ11,
author = {Janet Meiling Wang Roveda and
Susan Lysecky and
Young{-}Jun Son and
Hyungtaek Chang and
Anita Annamalai and
Xiao Qin},
title = {Interface model based cyber-physical energy system design for smart
grid},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {368--373},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081611},
doi = {10.1109/VLSISOC.2011.6081611},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RovedaLSCAQ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SaibuaQZ11,
author = {Siwat Saibua and
Liuxi Qian and
Dian Zhou},
title = {Worst case analysis for evaluating {VLSI} circuit performance bounds
using an optimization method},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {102--105},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081660},
doi = {10.1109/VLSISOC.2011.6081660},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SaibuaQZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SanchezRT11,
author = {Ernesto S{\'{a}}nchez and
Matteo Sonza Reorda and
Alberto Paolo Tonda},
title = {On the functional test of Branch Prediction Units based on Branch
History Table},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {278--283},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081650},
doi = {10.1109/VLSISOC.2011.6081650},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SanchezRT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SanchezRT11a,
author = {Ernesto S{\'{a}}nchez and
Matteo Sonza Reorda and
Alberto Paolo Tonda},
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {On the Functional Test of Branch Prediction Units Based on the Branch
History Table Architecture},
booktitle = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
pages = {110--123},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-32770-4\_7},
doi = {10.1007/978-3-642-32770-4\_7},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SanchezRT11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SanchezST11,
author = {Ernesto S{\'{a}}nchez and
Giovanni Squillero and
Alberto Paolo Tonda},
title = {Post-silicon failing-test generation through evolutionary computation},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {164--167},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081667},
doi = {10.1109/VLSISOC.2011.6081667},
timestamp = {Wed, 13 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SanchezST11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SankmanM11,
author = {Joseph Sankman and
Dongsheng Ma},
title = {A subthreshold digital maximum power point tracker for micropower
piezoelectric energy harvesting applications},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {363--367},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081610},
doi = {10.1109/VLSISOC.2011.6081610},
timestamp = {Fri, 21 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SankmanM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Sarfraz11,
author = {Khawar Sarfraz},
title = {A novel low-leakage 8T differential {SRAM} cell},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {19--24},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081624},
doi = {10.1109/VLSISOC.2011.6081624},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Sarfraz11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SasagawaMTKNTO11,
author = {Kiyotaka Sasagawa and
Hiroyuki Masuda and
Ayato Tagawa and
Takuma Kobayashi and
Toshihiko Noda and
Takashi Tokuda and
Jun Ohta},
title = {Micro {CMOS} image sensor for multi-area imaging},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {15--18},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081613},
doi = {10.1109/VLSISOC.2011.6081613},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SasagawaMTKNTO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SunK11,
author = {Yanan Sun and
Volkan Kursun},
title = {Uniform carbon nanotube diameter and nanoarray pitch for {VLSI} of
16nm P-channel MOSFETs},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {226--231},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081642},
doi = {10.1109/VLSISOC.2011.6081642},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SunK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TehQT11,
author = {Ying Fei Teh and
Zhiliang Qian and
Chi{-}Ying Tsui},
title = {A fault-tolerant NoC using combined link sharing and partial fault
link utilization scheme},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {296--301},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081595},
doi = {10.1109/VLSISOC.2011.6081595},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TehQT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsuchiyaTHST11,
author = {Toshiyuki Tsuchiya and
Hiroyuki Tokusaki and
Yoshikazu Hirai and
Koji Sugano and
Osamu Tabata},
title = {Self-dependent equivalent circuit modeling of electrostatic comb transducers
for integrated {MEMS}},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {208--213},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081639},
doi = {10.1109/VLSISOC.2011.6081639},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TsuchiyaTHST11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsuchiyaTHST11a,
author = {Toshiyuki Tsuchiya and
Hiroyuki Tokusaki and
Yoshikazu Hirai and
Koji Sugano and
Osamu Tabata},
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {Self-dependent Equivalent Circuit Modeling of Electrostatic Comb Transducers
for Integrated {MEMS}},
booktitle = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
pages = {94--109},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-32770-4\_6},
doi = {10.1007/978-3-642-32770-4\_6},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TsuchiyaTHST11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VillenaS11,
author = {Jorge Fernandez Villena and
L. Miguel Silveira},
title = {Positive realization of reduced {RLCM} nets},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {398--403},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081617},
doi = {10.1109/VLSISOC.2011.6081617},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/VillenaS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VivetDTC11,
author = {Pascal Vivet and
Denis Dutoit and
Yvain Thonnart and
Fabien Clermidy},
title = {3D NoC using through silicon Via: An asynchronous implementation},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {232--237},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081643},
doi = {10.1109/VLSISOC.2011.6081643},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/VivetDTC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WangPYJHL11,
author = {Xiaohang Wang and
Maurizio Palesi and
Mei Yang and
Yingtao Jiang and
Michael C. Huang and
Peng Liu},
title = {Low latency and energy efficient multicasting schemes for 3D NoC-based
SoCs},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {337--342},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081604},
doi = {10.1109/VLSISOC.2011.6081604},
timestamp = {Mon, 24 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WangPYJHL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WeiCGS11,
author = {Jizeng Wei and
Yisong Chang and
Wei Guo and
Jizhou Sun},
title = {An optimized TTA-like vertex shader datapath for embedded 3D graphics
processing unit},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {188--191},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081673},
doi = {10.1109/VLSISOC.2011.6081673},
timestamp = {Sun, 27 May 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WeiCGS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/XieXM11,
author = {Jing Xie and
Huimin Xing and
Zhigang Mao},
title = {On-chip structure and addressing scheme design for 2-D block data
processing in a 64-core array system},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {176--179},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081670},
doi = {10.1109/VLSISOC.2011.6081670},
timestamp = {Sat, 08 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/XieXM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YingCFZ11,
author = {Jiang Ying and
Xinhua Chen and
Yibo Fan and
Xiaoyang Zeng},
title = {{MUX-MCM} based quantization {VLSI} architecture for {H.264/AVC} high
profile encoder},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {72--77},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081632},
doi = {10.1109/VLSISOC.2011.6081632},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/YingCFZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YuYZW11,
author = {Le Yu and
Haigang Yang and
Jia Zhang and
Wei Wang},
title = {Performance evaluation of air-gap-based coaxial {RF} {TSV} for 3D
NoC},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {94--97},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081658},
doi = {10.1109/VLSISOC.2011.6081658},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/YuYZW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhangYYXZW11,
author = {Jia Zhang and
Le Yu and
Haigang Yang and
Y. L. Xie and
F. B. Zhou and
Wei Wang},
title = {Self-test method and recovery mechanism for high frequency {TSV} array},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {260--265},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081648},
doi = {10.1109/VLSISOC.2011.6081648},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhangYYXZW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhaoBB11,
author = {Xiaojin Zhao and
Amine Bermak and
Farid Boussa{\"{\i}}d},
title = {A low cost {CMOS} polarimetric ophthalmoscope scheme for cerebral
malaria diagnostics},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081598},
doi = {10.1109/VLSISOC.2011.6081598},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhaoBB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhaoBB11a,
author = {Xiaojin Zhao and
Amine Bermak and
Farid Boussa{\"{\i}}d},
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {A Low Cost {CMOS} Polarimetric Ophthalmoscope Scheme for Cerebral
Malaria Diagnostics},
booktitle = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
pages = {1--9},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-32770-4\_1},
doi = {10.1007/978-3-642-32770-4\_1},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhaoBB11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhaoTCBZGSLKERC11,
author = {Weisheng Zhao and
Lionel Torres and
Luis Vit{\'{o}}rio Cargnini and
Raphael Martins Brum and
Yue Zhang and
Yoann Guillemenet and
Gilles Sassatelli and
Yahya Lakys and
Jacques{-}Olivier Klein and
Daniel Etiemble and
Dafine Ravelosona and
Claude Chappert},
editor = {Salvador Mir and
Chi{-}Ying Tsui and
Ricardo Reis and
Oliver C. S. Choy},
title = {High Performance SoC Design Using Magnetic Logic and Memory},
booktitle = {VLSI-SoC: Advanced Research for Systems on Chip - 19th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {379},
pages = {10--33},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-32770-4\_2},
doi = {10.1007/978-3-642-32770-4\_2},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhaoTCBZGSLKERC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhaoZLKERCTCBGS11,
author = {Weisheng Zhao and
Yue Zhang and
Yahya Lakys and
Jacques{-}Olivier Klein and
Daniel Etiemble and
D. Revelosona and
Claude Chappert and
Lionel Torres and
Luis Vit{\'{o}}rio Cargnini and
Raphael Martins Brum and
Yoann Guillemenet and
Gilles Sassatelli},
title = {Embedded {MRAM} for high-speed computing},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {37--42},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081627},
doi = {10.1109/VLSISOC.2011.6081627},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhaoZLKERCTCBGS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhenZLYZL11,
author = {Shaowei Zhen and
Bo Zhang and
Ping Luo and
Kang Yang and
Xiaohui Zhu and
Jiangkun Li},
title = {A high efficiency synchronous buck converter with adaptive dead time
control for dynamic voltage scaling applications},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {43--48},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081628},
doi = {10.1109/VLSISOC.2011.6081628},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhenZLYZL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhongZJCP11,
author = {Guanwen Zhong and
Hongbin Zheng and
ZhenHua Jin and
Dihu Chen and
Zhiyong Pang},
title = {1024-point pipeline {FFT} processor with pointer FIFOs based on {FPGA}},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {122--125},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081654},
doi = {10.1109/VLSISOC.2011.6081654},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhongZJCP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhouWR11,
author = {Zhijian Zhou and
Man Wong and
Libor Rufer},
title = {Wide-band piezoresistive aero-acoustic microphone},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {214--219},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081640},
doi = {10.1109/VLSISOC.2011.6081640},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhouWR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhuLZYLZ11,
author = {Xiaohui Zhu and
Ping Luo and
Shaowei Zhen and
Kang Yang and
Jiangkun Li and
Zekun Zhou},
title = {A voltage mode power converter with the function of digitally duty
cycle tuning},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {319--324},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081600},
doi = {10.1109/VLSISOC.2011.6081600},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhuLZYLZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhuXL11,
author = {Ming Zhu and
Liyi Xiao and
Hong Wei Luo},
title = {New {SEC-DED-DAEC} codes for multiple bit upsets mitigation in memory},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {254--259},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081647},
doi = {10.1109/VLSISOC.2011.6081647},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhuXL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2009soc,
editor = {J{\"{u}}rgen Becker and
Marcelo O. Johann and
Ricardo Reis},
title = {VLSI-SoC: Technologies for Systems Integration - 17th {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2009, Florian{\'{o}}polis, Brazil, October 12-14, 2009,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {360},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-23120-9},
doi = {10.1007/978-3-642-23120-9},
isbn = {978-3-642-23119-3},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2009soc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2011soc,
title = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
publisher = {{IEEE}},
year = {2011},
url = {https://ieeexplore.ieee.org/xpl/conhome/6069623/proceeding},
isbn = {978-1-4577-0171-9},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2011soc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Abdel-KhalekB10,
author = {Rawan Abdel{-}Khalek and
Valeria Bertacco},
title = {SoCGuard: {A} runtime verification solution for the functional correctness
of SoCs},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {49--54},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642622},
doi = {10.1109/VLSISOC.2010.5642622},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Abdel-KhalekB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AbdelsalamWADI10,
author = {Mohamed Abdelsalam and
M. Wahba and
M. Abdelmoneum and
David Duarte and
Yehia Ismail},
title = {Supporting circuitry for a fully integrated micro electro mechanical
{(MEMS)} oscillator in 45 nm {CMOS} technology},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {259--263},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642670},
doi = {10.1109/VLSISOC.2010.5642670},
timestamp = {Fri, 11 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AbdelsalamWADI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AghamirzaieRZN10,
author = {Delasa Aghamirzaie and
Seyyed Ahmad Razavi and
Morteza Saheb Zamani and
Mahdi Nabiyouni},
title = {Reduction of process variation effect on FPGAs using multiple configurations},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {85--90},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642616},
doi = {10.1109/VLSISOC.2010.5642616},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AghamirzaieRZN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AkinCEKH10,
author = {Abdulkadir Akin and
Mert Cetin and
Burak Erbagci and
Ozgur Karakaya and
Ilker Hamzaoglu},
title = {An adaptive bilateral motion estimation algorithm and its hardware
architecture},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {207--212},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642661},
doi = {10.1109/VLSISOC.2010.5642661},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AkinCEKH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AlonsoD10,
author = {Oscar Alonso and
{\'{A}}ngel Di{\'{e}}guez},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Control Electronics Integration toward Endoscopic Capsule Robot Performing
Legged Locomotion and Illumination},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {312--338},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_13},
doi = {10.1007/978-3-642-28566-0\_13},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AlonsoD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AlonsoFCSD10,
author = {Oscar Alonso and
Lluis Freixas and
Joan Canals and
Ekawahyu Susilo and
{\'{A}}ngel Dieguez},
title = {Control electronics integration toward endoscopic capsule robot performing
legged locomotion and illumination},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {241--246},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642667},
doi = {10.1109/VLSISOC.2010.5642667},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AlonsoFCSD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AltermannCB10,
author = {Jo{\~{a}}o S. Altermann and
Eduardo A. C. da Costa and
Sergio Bampi},
title = {Fast forward and inverse transforms for the {H.264/AVC} standard using
hierarchical adder compressors},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {310--315},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642679},
doi = {10.1109/VLSISOC.2010.5642679},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AltermannCB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AnuarTS10,
author = {Nazrul Anuar and
Yasuhiro Takahashi and
Toshikazu Sekine},
title = {4{\texttimes}4-bit array two phase clocked adiabatic static {CMOS}
logic multiplier with new {XOR}},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {364--368},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642688},
doi = {10.1109/VLSISOC.2010.5642688},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AnuarTS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BaloukasPPSM10,
author = {Christos Baloukas and
Lazaros Papadopoulos and
Robert Pyka and
Dimitrios Soudris and
Peter Marwedel},
title = {An automatic framework for dynamic data structures optimization in
{C}},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {155--160},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642605},
doi = {10.1109/VLSISOC.2010.5642605},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BaloukasPPSM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BattezzatiSVD10,
author = {Niccol{\`{o}} Battezzati and
Luca Sterpone and
Massimo Violante and
Filomena Decuzzi},
title = {A new software tool for static analysis of {SET} sensitiveness in
Flash-based FPGAs},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {79--84},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642619},
doi = {10.1109/VLSISOC.2010.5642619},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BattezzatiSVD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BenkeserBH10,
author = {Christian Benkeser and
Andreas Bubenhofer and
Qiuting Huang},
title = {A 1mm\({}^{\mbox{2}}\) 1.3mW {GSM/EDGE} digital baseband receiver
{ASIC} in 0.13 {\(\mathrm{\mu}\)}m {CMOS}},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {183--188},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642592},
doi = {10.1109/VLSISOC.2010.5642592},
timestamp = {Thu, 09 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BenkeserBH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BenkeserH10,
author = {Christian Benkeser and
Qiuting Huang},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Design and Optimization of a Digital Baseband Receiver {ASIC} for
{GSM/EDGE}},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {100--127},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_5},
doi = {10.1007/978-3-642-28566-0\_5},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BenkeserH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Berg10,
author = {Yngvar Berg},
title = {Ultra low voltage and high speed {CMOS} flip-flop using floating-gates},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {111--114},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642613},
doi = {10.1109/VLSISOC.2010.5642613},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Berg10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Berg10a,
author = {Yngvar Berg},
title = {Static ultra-low-voltage high-speed {CMOS} logic and latches},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {115--118},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642610},
doi = {10.1109/VLSISOC.2010.5642610},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Berg10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Berg10b,
author = {Yngvar Berg},
title = {Novel ultra low-voltage and high speed domino {CMOS} logic},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {225--228},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642664},
doi = {10.1109/VLSISOC.2010.5642664},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Berg10b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BermanGK10,
author = {Amit Berman and
Ran Ginosar and
Idit Keidar},
title = {Order is power: Selective Packet Interleaving for energy efficient
Networks-on-Chip},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {37--42},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642624},
doi = {10.1109/VLSISOC.2010.5642624},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BermanGK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernasconiC10,
author = {Anna Bernasconi and
Valentina Ciriani},
title = {Logic synthesis and testability of D-reducible functions},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {280--285},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642674},
doi = {10.1109/VLSISOC.2010.5642674},
timestamp = {Sat, 23 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BernasconiC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BombieriFG10,
author = {Nicola Bombieri and
Franco Fummi and
Valerio Guarnieri},
title = {Model checking on {TLM-2.0} IPs through automatic TLM-to-RTL synthesis},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {61--66},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642620},
doi = {10.1109/VLSISOC.2010.5642620},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BombieriFG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BonannoBMM10,
author = {Alberto Bonanno and
Alberto Bocca and
Alberto Macii and
Enrico Macii},
title = {Power-aware partitioning of data converters},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {358--363},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642687},
doi = {10.1109/VLSISOC.2010.5642687},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BonannoBMM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BotelhoKLCC10,
author = {Mariza Botelho and
Fernanda Lima Kastensmidt and
Marcelo Lubaszewski and
{\'{E}}rika F. Cota and
Luigi Carro},
title = {A broad strategy to detect crosstalk faults in network-on-chip interconnects},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {298--303},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642677},
doi = {10.1109/VLSISOC.2010.5642677},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BotelhoKLCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BusseuilAOVSR10,
author = {R{\'{e}}mi Busseuil and
Gabriel Marchesan Almeida and
Luciano Ost and
Sameer Varyani and
Gilles Sassatelli and
Michel Robert},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Adaptation Strategies in Multiprocessors System on Chip},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {233--257},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_10},
doi = {10.1007/978-3-642-28566-0\_10},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BusseuilAOVSR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CaffarenaC10,
author = {Gabriel Caffarena and
Carlos Carreras},
title = {Architectural synthesis of {DSP} circuits under simultaneous error
and time constraints},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {322--327},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642681},
doi = {10.1109/VLSISOC.2010.5642681},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CaffarenaC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CaffarenaCLH10,
author = {Gabriel Caffarena and
Carlos Carreras and
Juan A. L{\'{o}}pez and
Angel Fernandez Herrero},
title = {Fast fixed-point optimization of {DSP} algorithms},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {195--200},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642659},
doi = {10.1109/VLSISOC.2010.5642659},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CaffarenaCLH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CaffarenaHLC10,
author = {Gabriel Caffarena and
Angel Fernandez Herrero and
Juan A. L{\'{o}}pez and
Carlos Carreras},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Fast Fixed-Point Optimization of {DSP} Algorithms},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {182--205},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_8},
doi = {10.1007/978-3-642-28566-0\_8},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CaffarenaHLC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CarduFGSCPSC10,
author = {Roberto Cardu and
Eleonora Franchi and
Roberto Guerrieri and
Mauro Scandiuzzo and
Salvatore Cani and
Luca Perugini and
Simone Spolzino and
Roberto Canegallo},
title = {Characterization of chip-to-chip wireless interconnections based on
capacitive coupling},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {375--380},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642690},
doi = {10.1109/VLSISOC.2010.5642690},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CarduFGSCPSC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ClaesenVLMFRLY10,
author = {Luc Claesen and
Peter Vandoren and
Tom Van Laerhoven and
Andy Motten and
Fabian Di Fiore and
Frank Van Reeth and
Jing Liao and
Jinhui Yu},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Smart Camera System-on-Chip Architecture for Real-Time Brush Based
Interactive Painting Systems},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {339--353},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_14},
doi = {10.1007/978-3-642-28566-0\_14},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ClaesenVLMFRLY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ClaesenVLMNWRF10,
author = {Luc Claesen and
Peter Vandoren and
Tom Van Laerhoven and
Andy Motten and
Domien Nowicki and
Tom De Weyer and
Frank Van Reeth and
Eddy Flerackers},
title = {Smart camera SoC system for interactive real-time real-brush based
digital painting systems},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {247--252},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642668},
doi = {10.1109/VLSISOC.2010.5642668},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ClaesenVLMNWRF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DoBDYC10,
author = {Aaron V. T. Do and
Chirn Chye Boon and
Manh Anh Do and
Kiat Seng Yeo and
Alper Cabuk},
title = {A 1-V {CMOS} ultralow-power receiver front end for the {IEEE} 802.15.4
standard using tuned passive mixer output pole},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {381--386},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642691},
doi = {10.1109/VLSISOC.2010.5642691},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DoBDYC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DoBKDY10,
author = {Aaron V. T. Do and
Chirn Chye Boon and
Manthena Vamshi Krishna and
Manh Anh Do and
Kiat Seng Yeo},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {A 1-V {CMOS} Ultralow-Power Receiver Front End for the {IEEE} 802.15.4
Standard Using Tuned Passive Mixer Output Pole},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {1--21},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_1},
doi = {10.1007/978-3-642-28566-0\_1},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DoBKDY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ElissatiRYF10,
author = {Oussama Elissati and
S{\'{e}}bastien Rieubon and
Eslam Yahya and
Laurent Fesquet},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Self-Timed Rings: {A} Promising Solution for Generating High-Speed
High-Resolution Low-Phase Noise Clocks},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {22--42},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_2},
doi = {10.1007/978-3-642-28566-0\_2},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ElissatiRYF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ElissatiYRF10,
author = {Oussama Elissati and
Eslam Yahya and
S{\'{e}}bastien Rieubon and
Laurent Fesquet},
title = {A high-speed high-resolution low-phase noise oscillator using self-timed
rings},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {173--178},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642600},
doi = {10.1109/VLSISOC.2010.5642600},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ElissatiYRF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FranciscoPS10,
author = {Bruno Francisco and
Frederico Pratas and
Leonel Sousa},
title = {Unifying stream based and reconfigurable computing to design application
accelerators},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {408--413},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642696},
doi = {10.1109/VLSISOC.2010.5642696},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FranciscoPS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Gioiosa10,
author = {Roberto Gioiosa},
title = {Towards sustainable exascale computing},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {270--275},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642672},
doi = {10.1109/VLSISOC.2010.5642672},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Gioiosa10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GuoLY10,
author = {Jing Guo and
Bing Liu and
George Jie Yuan},
title = {A highly linear wide dynamic range detector for cell recording with
microelectrode arrays},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {179--182},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642601},
doi = {10.1109/VLSISOC.2010.5642601},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GuoLY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HamwiH10,
author = {Khawla Hamwi and
Omar Hammami},
title = {Design and implementation of MPSoC single chip with butterfly network},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {143--148},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642607},
doi = {10.1109/VLSISOC.2010.5642607},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HamwiH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HoL10,
author = {Tsung{-}Yi Ho and
Sheng{-}Hung Liu},
title = {Fast legalization for standard cell placement with simultaneous wirelength
and displacement minimization},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {369--374},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642689},
doi = {10.1109/VLSISOC.2010.5642689},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HoL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HoL10a,
author = {Tsung{-}Yi Ho and
Sheng{-}Hung Liu},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Fast Legalization for Standard Cell Placement with Simultaneous Wirelength
and Displacement Minimization},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {291--311},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_12},
doi = {10.1007/978-3-642-28566-0\_12},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HoL10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HongC10,
author = {Kuo{-}Che Hong and
Herming Chiueh},
title = {A 36-mW continuous-time sigma-delta modulator with 74db dynamic range
and 10-MHz bandwidth},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {392--395},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642693},
doi = {10.1109/VLSISOC.2010.5642693},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HongC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HusemannMGSRL10,
author = {Ronaldo Husemann and
Mariano Majolo and
Victor Guimar{\~{a}}es and
Altamiro Amadeu Susin and
Valter Roesler and
Jos{\'{e}} Valdeni de Lima},
title = {Hardware integrated quantization solution for improvement of computational
{H.264} encoder module},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {316--321},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642680},
doi = {10.1109/VLSISOC.2010.5642680},
timestamp = {Sun, 19 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HusemannMGSRL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JaccottetCAFM10,
author = {Diego Jaccottet and
Eduardo Costa and
Levent Aksoy and
Paulo F. Flores and
Jos{\'{e}} Monteiro},
title = {Design of low-complexity and high-speed digital Finite Impulse Response
filters},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {292--297},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642676},
doi = {10.1109/VLSISOC.2010.5642676},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JaccottetCAFM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JiaoK10,
author = {Hailong Jiao and
Volkan Kursun},
title = {Reactivation noise suppression with threshold voltage tuning in sequential
{MTCMOS} circuits},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {347--351},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642685},
doi = {10.1109/VLSISOC.2010.5642685},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JiaoK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JiaoK10a,
author = {Hailong Jiao and
Volkan Kursun},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage
Multi-Threshold {CMOS} Circuits},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {258--290},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_11},
doi = {10.1007/978-3-642-28566-0\_11},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JiaoK10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JimenezGKCCBBV10,
author = {V{\'{\i}}ctor Jim{\'{e}}nez and
Roberto Gioiosa and
Eren Kursun and
Francisco J. Cazorla and
Chen{-}Yong Cher and
Alper Buyuktosunoglu and
Pradip Bose and
Mateo Valero},
title = {Trends and techniques for energy efficient architectures},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {276--279},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642673},
doi = {10.1109/VLSISOC.2010.5642673},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JimenezGKCCBBV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JridiA10,
author = {Maher Jridi and
Ayman Alfalou},
title = {A low-power, high-speed {DCT} architecture for image compression:
Principle and implementation},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {304--309},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642678},
doi = {10.1109/VLSISOC.2010.5642678},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JridiA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JridiA10a,
author = {Maher Jridi and
Ayman Alfalou},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Joint Optimization of Low-Power {DCT} Architecture and Efficient Quantization
Technique for Embedded Image Compression},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {155--181},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_7},
doi = {10.1007/978-3-642-28566-0\_7},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JridiA10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JungKK10,
author = {Jongpil Jung and
Seonpil Kim and
Chong{-}Min Kyung},
title = {Latency-aware Utility-based {NUCA} Cache Partitioning in 3D-stacked
multi-processor systems},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {125--130},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642608},
doi = {10.1109/VLSISOC.2010.5642608},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JungKK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KarimiS10,
author = {Zohreh Karimi and
Majid Sarrafzadeh},
title = {Fine-grained post placement voltage assignment considering level shifter
overhead},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {73--78},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642618},
doi = {10.1109/VLSISOC.2010.5642618},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KarimiS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KhereddineASMC10,
author = {Rafik Khereddine and
Louay Abdallah and
Emmanuel Simeu and
Salvador Mir and
Fabio Cenni},
title = {Adaptive logical control of {RF} {LNA} performances for efficient
energy consumption},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {161--166},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642602},
doi = {10.1109/VLSISOC.2010.5642602},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KhereddineASMC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KhereddineASMC10a,
author = {Rafik Khereddine and
Louay Abdallah and
Emmanuel Simeu and
Salvador Mir and
Fabio Cenni},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Adaptive Logical Control of {RF} {LNA} Performances for Efficient
Energy Consumption},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {43--68},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_3},
doi = {10.1007/978-3-642-28566-0\_3},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KhereddineASMC10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KiladaDS10,
author = {Eliyah Kilada and
Shomit Das and
Kenneth S. Stevens},
title = {Synchronous elasticization: Considerations for correct implementation
and MiniMIPS case study},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {7--12},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642631},
doi = {10.1109/VLSISOC.2010.5642631},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KiladaDS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KiladaS10,
author = {Eliyah Kilada and
Kenneth S. Stevens},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {Design and Verification of Lazy and Hybrid Implementations of the
{SELF} Protocol},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {206--232},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_9},
doi = {10.1007/978-3-642-28566-0\_9},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KiladaS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KongL10,
author = {Ji Kong and
Peilin Liu},
title = {A novel reconfigurable scratchpad memory for audio applications on
cost-effective SoC},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {402--407},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642695},
doi = {10.1109/VLSISOC.2010.5642695},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KongL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KrishnaJDBYD10,
author = {Manthena Vamshi Krishna and
Xuan Jie and
Manh Anh Do and
Chirn Chye Boon and
Kiat Seng Yeo and
Aaron V. T. Do},
editor = {Jos{\'{e}} L. Ayala and
David Atienza Alonso and
Ricardo Reis},
title = {A 1.8-V 3.6-mW 2.4-GHz Fully Integrated {CMOS} Frequency Synthesizer
for the {IEEE} 802.15.4},
booktitle = {VLSI-SoC: Forward-Looking Trends in {IC} and Systems Design - 18th
{IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale
Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010,
Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {373},
pages = {69--99},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-28566-0\_4},
doi = {10.1007/978-3-642-28566-0\_4},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KrishnaJDBYD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KrishnaXDBYD10,
author = {Manthena Vamshi Krishna and
Juan Xie and
Manh Anh Do and
Chirn Chye Boon and
Kiat Seng Yeo and
Aaron V. T. Do},
title = {A 1.8-V 3.6-mW 2.4-GHz fully integrated {CMOS} frequency synthesizer
for {IEEE} 802.15.4},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {387--391},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642692},
doi = {10.1109/VLSISOC.2010.5642692},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KrishnaXDBYD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeKK10,
author = {Seunghan Lee and
Kyungsu Kang and
Chong{-}Min Kyung},
title = {Temperature- and bus traffic- aware data placement in 3D-stacked cache},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {352--357},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642686},
doi = {10.1109/VLSISOC.2010.5642686},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeKK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LinCL10,
author = {Kuan Jen Lin and
Yu Chan Chiu and
Tzu{-}Hao Lin},
title = {A decimal squarer with efficient partial product generation},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {213--218},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642662},
doi = {10.1109/VLSISOC.2010.5642662},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LinCL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LinLC10,
author = {Ding{-}Guo Lin and
Bing{-}Hsun Lu and
Herming Chiueh},
title = {An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching
detector},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {101--104},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642615},
doi = {10.1109/VLSISOC.2010.5642615},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LinLC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MagnoLBSB10,
author = {Michele Magno and
Alessandro Lanza and
Davide Brunelli and
Luigi Di Stefano and
Luca Benini},
title = {Energy aware multimodal embedded video surveillance},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {264--269},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642671},
doi = {10.1109/VLSISOC.2010.5642671},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MagnoLBSB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MathewBRPMJ10,
author = {Jimson Mathew and
Savita Banerjee and
Hafizur Rahaman and
Dhiraj K. Pradhan and
Saraju P. Mohanty and
Abusaleh M. Jabir},
title = {On the synthesis of attack tolerant cryptographic hardware},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {286--291},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642675},
doi = {10.1109/VLSISOC.2010.5642675},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MathewBRPMJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MatosCCS10,
author = {Debora Matos and
Miklecio Costa and
Luigi Carro and
Altamiro Amadeu Susin},
title = {Network interface to synchronize multiple packets on NoC-based Systems-on-Chip},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {31--36},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642627},
doi = {10.1109/VLSISOC.2010.5642627},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MatosCCS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Meher10,
author = {Pramod Kumar Meher},
title = {An optimized lookup-table for the evaluation of sigmoid function for
artificial neural networks},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {91--95},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642617},
doi = {10.1109/VLSISOC.2010.5642617},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Meher10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Meher10a,
author = {Pramod Kumar Meher},
title = {Novel input coding technique for high-precision LUT-based multiplication
for {DSP} applications},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {201--206},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642660},
doi = {10.1109/VLSISOC.2010.5642660},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Meher10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MeloniSR10,
author = {Paolo Meloni and
Simone Secchi and
Luigi Raffo},
title = {Enabling fast Network-on-Chip topology selection: an FPGA-based runtime
reconfigurable prototyper},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {43--48},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642625},
doi = {10.1109/VLSISOC.2010.5642625},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MeloniSR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MottenC10,
author = {Andy Motten and
Luc Claesen},
title = {A binary adaptable window SoC architecture for a stereo vision based
depth field processor},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {25--30},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642626},
doi = {10.1109/VLSISOC.2010.5642626},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MottenC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NageswaranRDK10,
author = {Jayram Moorkanikara Nageswaran and
Micah Richert and
Nikil D. Dutt and
Jeffrey L. Krichmar},
title = {Towards reverse engineering the brain: Modeling abstractions and simulation
frameworks},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {1--6},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642630},
doi = {10.1109/VLSISOC.2010.5642630},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NageswaranRDK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NishidaEAIKS10,
author = {Shoichi Nishida and
Jyunya Eto and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Power-aware {FPGA} routing fabrics and design tools},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {67--72},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642621},
doi = {10.1109/VLSISOC.2010.5642621},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NishidaEAIKS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PandaVB10,
author = {Preeti Ranjan Panda and
Anant Vishnoi and
M. Balakrishnan},
title = {Enhancing post-silicon processor debug with Incremental Cache state
Dumping},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {55--60},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642623},
doi = {10.1109/VLSISOC.2010.5642623},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PandaVB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PanellaSRCS10,
author = {Alessandro Panella and
Marco D. Santambrogio and
Francesco Redaelli and
Fabio Cancare and
Donatella Sciuto},
title = {A design workflow for dynamically reconfigurable multi-FPGA systems},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {414--419},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642697},
doi = {10.1109/VLSISOC.2010.5642697},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PanellaSRCS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PettenghiCSA10,
author = {H{\'{e}}ctor Pettenghi and
Ricardo Chaves and
Leonel Sousa and
Maria J. Avedillo},
title = {An improved {RNS} generator 2\({}^{\mbox{n}}\) +/- k based on threshold
logic},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {119--124},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642611},
doi = {10.1109/VLSISOC.2010.5642611},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PettenghiCSA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PlyaskinMGCH10,
author = {Roman Plyaskin and
Alejandro Masrur and
Martin Geier and
Samarjit Chakraborty and
Andreas Herkersdorf},
title = {High-level timing analysis of concurrent applications on MPSoC platforms
using memory-aware trace-driven simulations},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {229--234},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642665},
doi = {10.1109/VLSISOC.2010.5642665},
timestamp = {Tue, 02 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PlyaskinMGCH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PonsMRAVG10,
author = {Marc Pons and
Francesc Moll and
Antonio Rubio and
Jaume Abella and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {{VCTA:} {A} Via-Configurable Transistor Array regular fabric},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {335--340},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642683},
doi = {10.1109/VLSISOC.2010.5642683},
timestamp = {Tue, 11 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PonsMRAVG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PoucheretBBTMR10,
author = {Fran{\c{c}}ois Poucheret and
Lyonel Barthe and
Pascal Benoit and
Lionel Torres and
Philippe Maurine and
Michel Robert},
title = {Spatial {EM} jamming: {A} countermeasure against {EM} Analysis?},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {105--110},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642612},
doi = {10.1109/VLSISOC.2010.5642612},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PoucheretBBTMR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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