Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSearch dblp for Publications
export results for "stream:streams/journals/integration:"
more than 1000 matches, exporting first 1000 hits only!
download as .bib file
@article{DBLP:journals/integration/ArnaizMAV24,
author = {David Arnaiz and
Francesc Moll and
Eduard Alarc{\'{o}}n and
Xavier Vilajosana},
title = {Energy and relevance-aware adaptive monitoring method for wireless
sensor nodes with hard energy constraints},
journal = {Integr.},
volume = {94},
pages = {102097},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102097},
doi = {10.1016/J.VLSI.2023.102097},
timestamp = {Sat, 08 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ArnaizMAV24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ArtugerO24,
author = {Firat Artuger and
Fatih {\"{O}}zkaynak},
title = {A new post-processing approach for improvement of nonlinearity property
in substitution boxes},
journal = {Integr.},
volume = {94},
pages = {102105},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102105},
doi = {10.1016/J.VLSI.2023.102105},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ArtugerO24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BandilN24,
author = {Lalit Bandil and
Bal Chand Nagar},
title = {Modified restoring array-based power efficient approximate square
root circuit and its application},
journal = {Integr.},
volume = {94},
pages = {102106},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102106},
doi = {10.1016/J.VLSI.2023.102106},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BandilN24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BeuraMDS24,
author = {Srikant Kumar Beura and
Sudeshna Manjari Mahanta and
Bishnulatpam Pushpa Devi and
Prabir Saha},
title = {Inexact radix-4 Booth multipliers based on new partial product generation
scheme for image multiplication},
journal = {Integr.},
volume = {94},
pages = {102096},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102096},
doi = {10.1016/J.VLSI.2023.102096},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BeuraMDS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CharalampidisIV24,
author = {Nikolaos Charalampidis and
Apostolos Iatropoulos and
Christos K. Volos},
title = {Chaos based speech encryption using microcontroller},
journal = {Integr.},
volume = {95},
pages = {102128},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102128},
doi = {10.1016/J.VLSI.2023.102128},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CharalampidisIV24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChaurasiaS24,
author = {Rahul Chaurasia and
Anirban Sengupta},
title = {Multi-cut based architectural obfuscation and handprint biometric
signature for securing transient fault detectable {IP} cores during
{HLS}},
journal = {Integr.},
volume = {95},
pages = {102114},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102114},
doi = {10.1016/J.VLSI.2023.102114},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChaurasiaS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenXX24,
author = {Yu Chen and
Yongjian Xu and
Ning Xu},
title = {Scalable layout decomposition implemented by a distribution evolutionary
algorithm},
journal = {Integr.},
volume = {95},
pages = {102125},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102125},
doi = {10.1016/J.VLSI.2023.102125},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChenXX24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChhabraAS24,
author = {Aakriti Chhabra and
Bhawna Aggarwal and
Raj Senani},
title = {A low-voltage {MOS} translinear loop, biased using {FVF} and its applications
in realizing square-rooter and squarer circuits},
journal = {Integr.},
volume = {94},
pages = {102092},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102092},
doi = {10.1016/J.VLSI.2023.102092},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChhabraAS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChughS24,
author = {Hemanshi Chugh and
Sonal Singh},
title = {Efficient co-planar adder designs in quantum dot cellular automata:
Energy and cost optimization with crossover elimination},
journal = {Integr.},
volume = {94},
pages = {102103},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102103},
doi = {10.1016/J.VLSI.2023.102103},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChughS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CuiSC24,
author = {Yuqiang Cui and
Weiwei Shan and
Peng Cao},
title = {Ultra-low-power one-hot transmission-gate multiplexer {(OTG-MUX)}
scalable into large fan-in circuits in 28 nm {CMOS}},
journal = {Integr.},
volume = {94},
pages = {102094},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102094},
doi = {10.1016/J.VLSI.2023.102094},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CuiSC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FrancaOGN24,
author = {Alexandre B. Z. de Fran{\c{c}}a and
Fernanda D. V. R. Oliveira and
Jos{\'{e}} Gabriel R. C. Gomes and
Nadia Nedjah},
title = {Hardware designs for convolutional neural networks: Memoryful, memoryless
and cached},
journal = {Integr.},
volume = {94},
pages = {102074},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102074},
doi = {10.1016/J.VLSI.2023.102074},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FrancaOGN24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GogolouKNS24,
author = {Vasiliki Gogolou and
Savvas Karipidis and
Thomas Noulis and
Stylianos Siskos},
title = {A frequency boosting technique for cold-start charge pump units},
journal = {Integr.},
volume = {94},
pages = {102076},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102076},
doi = {10.1016/J.VLSI.2023.102076},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GogolouKNS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GongCTWXSLL24,
author = {Yihong Gong and
Qibin Chen and
Ruiyong Tu and
Sini Wu and
Jin Xie and
Qiyan Sun and
Jing{-}Hu Li and
Zhicong Luo},
title = {A 10-Gb/s low-power inverter-based optical receiver front-end in 0.13-{\(\mu\)}m
{CMOS} process},
journal = {Integr.},
volume = {94},
pages = {102104},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102104},
doi = {10.1016/J.VLSI.2023.102104},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GongCTWXSLL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HaqueM24,
author = {Rezaul Haque and
Siraj Fulum Mossa},
title = {On-chip charge pump design for 3D non-volatile flash memory: from
industry perspective},
journal = {Integr.},
volume = {94},
pages = {102093},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102093},
doi = {10.1016/J.VLSI.2023.102093},
timestamp = {Tue, 02 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HaqueM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarCU24,
author = {Chaudhry Indra Kumar and
Abhishek Chaudhary and
Shreyansh Upadhyaya},
title = {Design of high performance energy efficient {CMOS} voltage level shifter
for mixed signal circuits applications},
journal = {Integr.},
volume = {95},
pages = {102133},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102133},
doi = {10.1016/J.VLSI.2023.102133},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KumarCU24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarS24,
author = {Saurabh Kumar and
Yatendra Kumar Singh},
title = {A low-jitter and low-phase noise switched-loop filter {PLL} using
fast phase-error correction and dual-edge phase comparison technique},
journal = {Integr.},
volume = {94},
pages = {102108},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102108},
doi = {10.1016/J.VLSI.2023.102108},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KumarS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LaskaridisVNM24,
author = {Lazaros Laskaridis and
Christos K. Volos and
Hector E. Nistazakis and
Efthymia Meletlidou},
title = {Exploring the dynamics of a multistable general model of discrete
memristor-based map featuring an exponentially varying memristance},
journal = {Integr.},
volume = {95},
pages = {102131},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102131},
doi = {10.1016/J.VLSI.2023.102131},
timestamp = {Sun, 25 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LaskaridisVNM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LemaUG24,
author = {Dar{\'{\i}}o G. Lema and
Rub{\'{e}}n Usamentiaga and
Daniel F. Garc{\'{\i}}a},
title = {Quantitative comparison and performance evaluation of deep learning-based
object detection models on edge computing devices},
journal = {Integr.},
volume = {95},
pages = {102127},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102127},
doi = {10.1016/J.VLSI.2023.102127},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LemaUG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiFZW24,
author = {Yongchao Li and
Jingya Feng and
Qi Zhao and
Yongzhuang Wei},
title = {{HDLBC:} {A} lightweight block cipher with high diffusion},
journal = {Integr.},
volume = {94},
pages = {102090},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102090},
doi = {10.1016/J.VLSI.2023.102090},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiFZW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiZHC24,
author = {Zijun Li and
Ziran Zhu and
Huan He and
Jianli Chen},
title = {An effective routability-driven packing algorithm for large-scale
heterogeneous FPGAs},
journal = {Integr.},
volume = {94},
pages = {102098},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102098},
doi = {10.1016/J.VLSI.2023.102098},
timestamp = {Thu, 25 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiZHC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MahalatSMSCS24,
author = {Mahabub Hasan Mahalat and
Shyam Subba and
Anindan Mondal and
Biplab K. Sikdar and
Rajat Subhra Chakraborty and
Bibhash Sen},
title = {{CAPUF:} Design of a configurable circular arbiter {PUF} with enhanced
security and hardware efficiency},
journal = {Integr.},
volume = {95},
pages = {102113},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102113},
doi = {10.1016/J.VLSI.2023.102113},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MahalatSMSCS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaityRG24,
author = {Dilip Kumar Maity and
Surajit Kumar Roy and
Chandan Giri},
title = {Built-in Self-prevention {(BISP)} for runtime ageing effects of TSVs
in 3D ICs},
journal = {Integr.},
volume = {94},
pages = {102088},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102088},
doi = {10.1016/J.VLSI.2023.102088},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MaityRG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NM24,
author = {Radha N and
Maheswari M},
title = {An optimal channel coding scheme for high-speed data communication},
journal = {Integr.},
volume = {94},
pages = {102107},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102107},
doi = {10.1016/J.VLSI.2023.102107},
timestamp = {Tue, 02 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PhamVHRGBM24,
author = {Viet{-}Thanh Pham and
Andrei Velichko and
Van Van Huynh and
Antonio Vincenzo Radogna and
Giuseppe Grassi and
Salah Mahmoud Boulaaras and
Shaher Momani},
title = {Analysis of memristive maps with asymmetry},
journal = {Integr.},
volume = {94},
pages = {102110},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102110},
doi = {10.1016/J.VLSI.2023.102110},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PhamVHRGBM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/QinZMH24,
author = {Maoyuan Qin and
Jiacheng Zhu and
Baolei Mao and
Wei Hu},
title = {Hardware/software security co-verification and vulnerability detection:
An information flow perspective},
journal = {Integr.},
volume = {94},
pages = {102089},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102089},
doi = {10.1016/J.VLSI.2023.102089},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/QinZMH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Rashidi24,
author = {Bahram Rashidi},
title = {Efficient and low-cost approximate multipliers for image processing
applications},
journal = {Integr.},
volume = {94},
pages = {102084},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102084},
doi = {10.1016/J.VLSI.2023.102084},
timestamp = {Tue, 02 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Rashidi24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RoutANN24,
author = {Prakash Kumar Rout and
Debiprasad Priyabrata Acharya and
Debasish Nayak and
Umakanta Nanda},
title = {Design of robust analog integrated circuit based on process corner
performance variability minimization},
journal = {Integr.},
volume = {94},
pages = {102100},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102100},
doi = {10.1016/J.VLSI.2023.102100},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RoutANN24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SG24,
author = {Sriram Sundar S and
Mahendran G},
title = {{CMOS} full adder cells based on modified full swing restored complementary
pass transistor logic for energy efficient high speed arithmetic applications},
journal = {Integr.},
volume = {95},
pages = {102132},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102132},
doi = {10.1016/J.VLSI.2023.102132},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SafdarSAH24,
author = {Muhammad Umair Safdar and
Tariq Shah and
Asif Ali and
Tanveer ul Haq},
title = {Construction of algebraic complex 9-bit lookup tables using non-chain-ring
and its applications in data security},
journal = {Integr.},
volume = {94},
pages = {102095},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102095},
doi = {10.1016/J.VLSI.2023.102095},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SafdarSAH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShahSSR24,
author = {Payal Shah and
Satvik Sawant and
Reena Sonkusare and
Surendra S. Rathod},
title = {Modelling and design of asynchronous receptive circuit for cone pathways},
journal = {Integr.},
volume = {94},
pages = {102112},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102112},
doi = {10.1016/J.VLSI.2023.102112},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShahSSR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShaikPSG24,
author = {Jani Babu Shaik and
Siona Menezes Picardo and
Sonal Singhal and
Nilesh Goel},
title = {Reliability-aware design of Integrate-and-Fire silicon neurons},
journal = {Integr.},
volume = {94},
pages = {102101},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102101},
doi = {10.1016/J.VLSI.2023.102101},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShaikPSG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/UllahLWZ24,
author = {Saeed Ullah and
Xinge Liu and
Adil Waheed and
Shuailei Zhang},
title = {An efficient construction of S-box based on the fractional-order Rabinovich-Fabrikant
chaotic system},
journal = {Integr.},
volume = {94},
pages = {102099},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102099},
doi = {10.1016/J.VLSI.2023.102099},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/UllahLWZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VohraTSD24,
author = {Sahibia Kaur Vohra and
Sherin A. Thomas and
Mahendra Sakare and
Devarshi Mrinal Das},
title = {Circuit implementation of on-chip trainable spiking neural network
using {CMOS} based memristive {STDP} synapses and {LIF} neurons},
journal = {Integr.},
volume = {95},
pages = {102122},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102122},
doi = {10.1016/J.VLSI.2023.102122},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/VohraTSD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangCCZCM24,
author = {Xuhui Wang and
Jun Cheng and
Fan Chang and
Lei Zhu and
Han Chang and
Kuizhi Mei},
title = {A bandwidth enhancement method of {VTA} based on paralleled memory
access design},
journal = {Integr.},
volume = {94},
pages = {102102},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102102},
doi = {10.1016/J.VLSI.2023.102102},
timestamp = {Sun, 24 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangCCZCM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XiaoZZML24,
author = {Wei Xiao and
Fazhan Zhao and
Kun Zhao and
Hongtu Ma and
Qing Li},
title = {TA-denseNet: Efficient hardware trust and assurance model based on
feature extraction and comparison of {SEM} images and {GDSII} images},
journal = {Integr.},
volume = {95},
pages = {102111},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102111},
doi = {10.1016/J.VLSI.2023.102111},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/XiaoZZML24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YanZWCLJ24,
author = {Shaohui Yan and
Bian Zheng and
Jianjian Wang and
Yu Cui and
Lin Li and
Jiawei Jiang},
title = {A new three-dimensional conservative system with non - Hamiltonian
energy and its synchronization application},
journal = {Integr.},
volume = {94},
pages = {102075},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102075},
doi = {10.1016/J.VLSI.2023.102075},
timestamp = {Tue, 02 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YanZWCLJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangL24,
author = {Liang Yang and
Qiang Lai},
title = {Construction and implementation of discrete memristive hyperchaotic
map with hidden attractors and self-excited attractors},
journal = {Integr.},
volume = {94},
pages = {102091},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102091},
doi = {10.1016/J.VLSI.2023.102091},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YangL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YuZDY24,
author = {Weiwei Yu and
Xiao Zhao and
Liyuan Dong and
Lanya Yu},
title = {A high current efficiency multipath nested feedforward compensation
technique for two-stage amplifier},
journal = {Integr.},
volume = {94},
pages = {102085},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102085},
doi = {10.1016/J.VLSI.2023.102085},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YuZDY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YuZMG24,
author = {Zhi{-}Guo Yu and
Xiao{-}Yu Zhong and
Xiao{-}Jie Ma and
Xiaofeng Gu},
title = {{W-IQ:} Wither-logic based issue queue for {RISC-V} superscalar out-of-order
processor},
journal = {Integr.},
volume = {94},
pages = {102109},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102109},
doi = {10.1016/J.VLSI.2023.102109},
timestamp = {Tue, 02 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YuZMG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangZGHX24,
author = {Jie Zhang and
Jiangang Zuo and
Yan Guo and
Jinyou Hou and
Qinggang Xie},
title = {Nonlinear analysis, circuit implementation, and application in image
encryption of a four-dimensional multi-scroll hyper-chaotic system},
journal = {Integr.},
volume = {95},
pages = {102126},
year = {2024},
url = {https://doi.org/10.1016/j.vlsi.2023.102126},
doi = {10.1016/J.VLSI.2023.102126},
timestamp = {Tue, 23 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhangZGHX24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/0001MBS23,
author = {Sudipta Paul and
Tridib Mukherjee and
Pritha Banerjee and
Susmita Sur{-}Kolay},
title = {Concurrent Steiner Tree Selection for Global routing with {EUVL} Flare
Reduction},
journal = {Integr.},
volume = {92},
pages = {66--76},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.04.007},
doi = {10.1016/J.VLSI.2023.04.007},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/0001MBS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/0019HQ23,
author = {Jie Xu and
Gensheng Hu and
Dingjun Qian},
title = {A quantum-based building block for designing a nanoscale full adder
circuit with power analysis},
journal = {Integr.},
volume = {92},
pages = {77--82},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.05.004},
doi = {10.1016/J.VLSI.2023.05.004},
timestamp = {Tue, 11 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/0019HQ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AggarwalRS23,
author = {Bhawna Aggarwal and
Shireesh Kumar Rai and
Anant Sinha},
title = {New memristor-less, resistor-less, two-OTA based grounded and floating
meminductor emulators and their applications in chaotic oscillators},
journal = {Integr.},
volume = {88},
pages = {173--184},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.005},
doi = {10.1016/J.VLSI.2022.10.005},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AggarwalRS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AhmadCGJB23,
author = {Riyaz Ahmad and
Narendra Choudhary and
Sujeet Kumar Gupta and
Amit Mahesh Joshi and
Dharmendar Boolchandani},
title = {Novel tunable current feedback instrumentation amplifier based on
{BBFC} {OP-AMP} for biomedical applications with low power and high
{CMRR}},
journal = {Integr.},
volume = {90},
pages = {214--223},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.003},
doi = {10.1016/J.VLSI.2023.02.003},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AhmadCGJB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AhmedKZA23,
author = {Mohammed Salman Ahmed and
Md. Kalesha and
Andleeb Zahra and
Zia Abbas},
title = {Approximate Toom-Cook {FFT} with sparsity aware error tuning in a
shared memory architecture},
journal = {Integr.},
volume = {89},
pages = {94--105},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.009},
doi = {10.1016/J.VLSI.2022.11.009},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AhmedKZA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AlizadehS23,
author = {Bijan Alizadeh and
Masoud Shiroei},
title = {Automatic correction of {RTL} designs using a lightweight partial
high level synthesis},
journal = {Integr.},
volume = {91},
pages = {173--181},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.04.001},
doi = {10.1016/J.VLSI.2023.04.001},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AlizadehS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AmiriV23,
author = {Zahra Yazdanian Amiri and
Mojtaba Valinataj},
title = {High-speed binary coded decimal digit multipliers with multiple error
detection},
journal = {Integr.},
volume = {93},
pages = {102073},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102073},
doi = {10.1016/J.VLSI.2023.102073},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AmiriV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AmuruZVCGAA23,
author = {Deepthi Amuru and
Andleeb Zahra and
Harsha V. Vudumula and
Pavan K. Cherupally and
Sushanth R. Gurram and
Amir Ahmad and
Zia Abbas},
title = {{AI/ML} algorithms and applications in {VLSI} design and technology},
journal = {Integr.},
volume = {93},
pages = {102048},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.06.002},
doi = {10.1016/J.VLSI.2023.06.002},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AmuruZVCGAA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Asyaei23,
author = {Mohammad Asyaei},
title = {New partitioned domino circuit for power-efficient wide gates},
journal = {Integr.},
volume = {88},
pages = {320--327},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.010},
doi = {10.1016/J.VLSI.2022.10.010},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Asyaei23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AttaouiCIM23,
author = {Yassine Attaoui and
Mohamed Chentouf and
Zine El Abidine Alaoui Ismaili and
Aimad El Mourabit},
title = {Machine learning application for cell delay accuracy improvement at
post-placement stage: {A} case study for combinational cells},
journal = {Integr.},
volume = {90},
pages = {261--270},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.011},
doi = {10.1016/J.VLSI.2023.02.011},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AttaouiCIM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AwanoH23,
author = {Hiromitsu Awano and
Masanori Hashimoto},
title = {{B2N2:} Resource efficient Bayesian neural network accelerator using
Bernoulli sampler on {FPGA}},
journal = {Integr.},
volume = {89},
pages = {1--8},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.005},
doi = {10.1016/J.VLSI.2022.11.005},
timestamp = {Sat, 13 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AwanoH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AxelouFES23,
author = {Olympia Axelou and
George Floros and
Nestor E. Evmorfopoulos and
George I. Stamoulis},
title = {Fast electromigration stress analysis using Low-Rank Balanced Truncation
for general interconnect and power grid structures},
journal = {Integr.},
volume = {89},
pages = {197--206},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.005},
doi = {10.1016/J.VLSI.2022.12.005},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AxelouFES23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AyesF23,
author = {Andres Ayes and
Eby G. Friedman},
title = {Linear Clock Tree Topology for Dynamic Source Synchronous and Fully
Synchronous 3-D Interfaces},
journal = {Integr.},
volume = {93},
pages = {102066},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102066},
doi = {10.1016/J.VLSI.2023.102066},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AyesF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BabaB23,
author = {Abdullatif Baba and
Talal Bonny},
title = {FPGA-based parallel implementation to classify Hyperspectral images
by using a Convolutional Neural Network},
journal = {Integr.},
volume = {92},
pages = {15--23},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.04.003},
doi = {10.1016/J.VLSI.2023.04.003},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BabaB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BaiZXWC23,
author = {Na Bai and
Yueliang Zhou and
Yaohua Xu and
Yi Wang and
Zihan Chen},
title = {Highly stable soft-error immune {SRAM} with multi-node upset recovery
for aerospace applications},
journal = {Integr.},
volume = {92},
pages = {58--65},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.05.001},
doi = {10.1016/J.VLSI.2023.05.001},
timestamp = {Tue, 11 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BaiZXWC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BalakrishnanVB23,
author = {Melvin T. Balakrishnan and
T. G. Venkatesh and
A. Vijaya Bhaskar},
title = {Design and implementation of congestion aware router for network-on-chip},
journal = {Integr.},
volume = {88},
pages = {43--57},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.08.012},
doi = {10.1016/J.VLSI.2022.08.012},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BalakrishnanVB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BalogluCH23,
author = {Onat Baloglu and
Oguzhan Cicekoglu and
Norbert Herencsar},
title = {{OTA-C} signal delay compensation circuit for transimpedance-mode
audio signal processing systems},
journal = {Integr.},
volume = {90},
pages = {205--213},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.005},
doi = {10.1016/J.VLSI.2023.02.005},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BalogluCH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BarbaFrancoRJLHP23,
author = {Jos{\'{e}} de Jes{\'{u}}s Barba{-}Franco and
Laura Romo{-}Mu{\~{n}}oz and
Rider Jaimes{-}Re{\'{a}}tegui and
Juan Hugo Garc{\'{\i}}a L{\'{o}}pez and
Guillermo Huerta{-}Cu{\'{e}}llar and
Alexander N. Pisarchik},
title = {Electronic equivalent of a pump-modulated erbium-doped fiber laser},
journal = {Integr.},
volume = {89},
pages = {106--113},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.012},
doi = {10.1016/J.VLSI.2022.11.012},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BarbaFrancoRJLHP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BenchanaKTBR23,
author = {Mohamed Amine Benchana and
Abderrezak Khalfallaoui and
Somia Taba and
Abdesselam Babouri and
Zouheir Riah},
title = {A hybrid equivalent source - particle swarm optimization model for
accurate near-field to far-field conversion},
journal = {Integr.},
volume = {89},
pages = {134--145},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.001},
doi = {10.1016/J.VLSI.2022.12.001},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BenchanaKTBR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BhardwajS23,
author = {Kapil Bhardwaj and
Mayank Srivastava},
title = {{VDTA} and {DO-CCII} based incremental/decremental floating memductance/meminductance
simulator: {A} novel realization},
journal = {Integr.},
volume = {88},
pages = {139--155},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.014},
doi = {10.1016/J.VLSI.2022.09.014},
timestamp = {Tue, 06 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BhardwajS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BokeNR23,
author = {Amol K. Boke and
Sangeeta Nakhate and
Arvind Rajawat},
title = {{FPGA} implementation of {PUF} based key generator for secure communication
in IoT},
journal = {Integr.},
volume = {89},
pages = {241--247},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.006},
doi = {10.1016/J.VLSI.2022.12.006},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BokeNR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BoniC23,
author = {Andrea Boni and
Michele Caselli},
title = {Model of a switched-capacitor programmable voltage reference for ultra
low-power applications},
journal = {Integr.},
volume = {90},
pages = {163--170},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.018},
doi = {10.1016/J.VLSI.2023.01.018},
timestamp = {Tue, 12 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BoniC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BrennerS23,
author = {Ulrich Brenner and
Anna Silvanus},
title = {BonnLogic: Delay optimization by And-Or Path restructuring},
journal = {Integr.},
volume = {89},
pages = {123--133},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.014},
doi = {10.1016/J.VLSI.2022.11.014},
timestamp = {Sun, 19 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BrennerS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CaiWXW023,
author = {Shuo Cai and
Yan Wen and
Caicai Xie and
Weizheng Wang and
Fei Yu},
title = {Low-power and high-speed {SRAM} cells for double-node-upset recovery},
journal = {Integr.},
volume = {91},
pages = {1--9},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.010},
doi = {10.1016/J.VLSI.2023.02.010},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CaiWXW023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CaiXWWYY23,
author = {Shuo Cai and
Caicai Xie and
Yan Wen and
Weizheng Wang and
Fei Yu and
Lairong Yin},
title = {Four-input-C-element-based multiple-node-upset-self-recoverable latch
designs},
journal = {Integr.},
volume = {90},
pages = {11--21},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.012},
doi = {10.1016/J.VLSI.2022.12.012},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CaiXWWYY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CamposCantonSM23,
author = {Isaac Campos{-}Cant{\'{o}}n and
Carlos Soubervielle{-}Montalvo and
Roberto C. Martinez{-}Montejano},
title = {Lorenz system as a filter},
journal = {Integr.},
volume = {90},
pages = {51--57},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.003},
doi = {10.1016/J.VLSI.2023.01.003},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CamposCantonSM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChangCCCY23,
author = {Cheng{-}Tsung Chang and
Pin{-}Wei Chen and
Wen{-}Long Chin and
Shih{-}Hsiang Chou and
Yu{-}Hua Yang},
title = {Hardware-efficient algorithm and architecture design with memory and
complexity reduction for semi-global matching},
journal = {Integr.},
volume = {92},
pages = {99--105},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.05.005},
doi = {10.1016/J.VLSI.2023.05.005},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChangCCCY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChatterjeeR23,
author = {Shatadal Chatterjee and
Sounak Roy},
title = {A low power offset voltage calibration method for flash ADCs},
journal = {Integr.},
volume = {88},
pages = {58--69},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.08.006},
doi = {10.1016/J.VLSI.2022.08.006},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChatterjeeR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenDCS23,
author = {Zhuo Chen and
Yuxuan Du and
Boyang Cheng and
Weiwei Shan},
title = {Design of high-efficiency complex multiplier for fault-tolerant computation},
journal = {Integr.},
volume = {90},
pages = {190--195},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.002},
doi = {10.1016/J.VLSI.2023.02.002},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChenDCS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenLGH23,
author = {Wen Chen and
Lang Li and
Ying Guo and
Ying Huang},
title = {{SAND-2:} An optimized implementation of lightweight block cipher},
journal = {Integr.},
volume = {91},
pages = {23--34},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.013},
doi = {10.1016/J.VLSI.2023.02.013},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChenLGH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenYLYS23,
author = {Qian Chen and
Yuyang Ye and
Meng Li and
Hao Yan and
Longxing Shi},
title = {Optimized matrix ordering of sparse linear solver using a few-shot
model for circuit simulation},
journal = {Integr.},
volume = {93},
pages = {102062},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102062},
doi = {10.1016/J.VLSI.2023.102062},
timestamp = {Thu, 11 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChenYLYS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChengXGX23,
author = {Tiedong Cheng and
Ziyu Xiao and
Jianping Guo and
Lijun Xu},
title = {A low power high area-efficiency {NMOS} {LDO} with fast adaptive bias},
journal = {Integr.},
volume = {88},
pages = {371--378},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.002},
doi = {10.1016/J.VLSI.2022.11.002},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChengXGX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChowdhuryMPS23,
author = {Sagarika Chowdhury and
Ritwika Majumdar and
Rajat Kumar Pal and
Goutam Saha},
title = {Automated path selection technique while incorporating multiple assay
operations and cross-contamination avoidance in cross-referencing
DMFBs},
journal = {Integr.},
volume = {88},
pages = {125--138},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.013},
doi = {10.1016/J.VLSI.2022.09.013},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChowdhuryMPS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CostamagnaM23,
author = {Andrea Costamagna and
Giovanni De Micheli},
title = {Accuracy recovery: {A} decomposition procedure for the synthesis of
partially-specified Boolean functions},
journal = {Integr.},
volume = {89},
pages = {248--260},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.008},
doi = {10.1016/J.VLSI.2022.12.008},
timestamp = {Sat, 13 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CostamagnaM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DabasKGY23,
author = {Annu Dabas and
Shweta Kumari and
Maneesha Gupta and
Richa Yadav},
title = {Design and analysis of {DTMOS} based {RFC} with controlled positive
feedback {OTA} using {HSCCM} and adaptive biasing technique},
journal = {Integr.},
volume = {90},
pages = {90--103},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.012},
doi = {10.1016/J.VLSI.2023.01.012},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DabasKGY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DasP23,
author = {Kaushik Das and
Sambhu Nath Pradhan},
title = {Hardware architecture design for complementary ensemble empirical
mode decomposition algorithm},
journal = {Integr.},
volume = {91},
pages = {153--164},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.011},
doi = {10.1016/J.VLSI.2023.03.011},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DasP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DeepsitaKM23,
author = {S. Skandha Deepsita and
T. Karthikeyan and
Sk. Noor Mahammad},
title = {Energy efficient multiply-accumulate unit using novel recursive multiplication
for error-tolerant applications},
journal = {Integr.},
volume = {92},
pages = {24--34},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.04.006},
doi = {10.1016/J.VLSI.2023.04.006},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DeepsitaKM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DingCGXG23,
author = {Liqiang Ding and
Xiaowu Cai and
Mali Gao and
Ruirui Xia and
Yuexin Gao},
title = {A high reliability under-voltage lock out circuit for power driver
{IC}},
journal = {Integr.},
volume = {88},
pages = {166--172},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.011},
doi = {10.1016/J.VLSI.2022.09.011},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DingCGXG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DounaviT23,
author = {Helen{-}Maria Dounavi and
Yiorgos Tsiatouhas},
title = {An aging monitoring scheme for {SRAM} decoders},
journal = {Integr.},
volume = {88},
pages = {108--115},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.009},
doi = {10.1016/J.VLSI.2022.09.009},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DounaviT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ElHadedyGYCHBH23,
author = {Mohamed El{-}Hadedy and
Xinfei Guo and
Kazutomo Yoshii and
Yichen Cai and
Robert Herndon and
Bryan Banta and
Wen{-}Mei Hwu},
title = {{RECO-ASCON:} Reconfigurable {ASCON} hash functions for IoT applications},
journal = {Integr.},
volume = {93},
pages = {102061},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102061},
doi = {10.1016/J.VLSI.2023.102061},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ElHadedyGYCHBH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/EnwereCCR23,
author = {Promise I. Enwere and
Encarnaci{\'{o}}n Cervantes{-}Requena and
Luis A. Camu{\~{n}}as{-}Mesa and
Jos{\'{e}} M. de la Rosa},
title = {Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio
systems},
journal = {Integr.},
volume = {93},
pages = {102070},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102070},
doi = {10.1016/J.VLSI.2023.102070},
timestamp = {Thu, 19 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/EnwereCCR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ErolY23,
author = {Didem Erol and
Mustafa Berke Yelten},
title = {A highly-linear, sub-mW {LNA} at 2.4 GHz in 40 nm {CMOS} process},
journal = {Integr.},
volume = {88},
pages = {278--285},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.010},
doi = {10.1016/J.VLSI.2022.09.010},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ErolY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/EsirciB23,
author = {Fatma Nur Esirci and
Alp Arslan Bayrakci},
title = {Delay based hardware Trojan detection exploiting spatial correlations
to suppress variations},
journal = {Integr.},
volume = {91},
pages = {107--118},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.006},
doi = {10.1016/J.VLSI.2023.03.006},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/EsirciB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FangHW23,
author = {Zehua Fang and
Jinglin Han and
Huaxinyu Wang},
title = {Deep reinforcement learning assisted reticle floorplanning with rectilinear
polygon modules for multiple-project wafer},
journal = {Integr.},
volume = {91},
pages = {144--152},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.012},
doi = {10.1016/J.VLSI.2023.03.012},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FangHW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FarahaniMF23,
author = {Mahdi Mazidabadi Farahani and
Jalil Mazloum and
Majid Fouladian},
title = {An ultra-wideband low noise amplifier with cascaded flipped-active
inductor for cognitive radio applications},
journal = {Integr.},
volume = {93},
pages = {102046},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.05.010},
doi = {10.1016/J.VLSI.2023.05.010},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FarahaniMF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FarsianiS23,
author = {Sirous Farsiani and
Amir M. Sodagar},
title = {Compact agile Tchebycheff transform variant for temporal compression
of neural signals on brain-implantable microsystems},
journal = {Integr.},
volume = {90},
pages = {171--182},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.016},
doi = {10.1016/J.VLSI.2023.01.016},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FarsianiS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FloranceP23,
author = {D. Rebecca Florance and
B. Prabhakar},
title = {Design of joint reconfigurable hybrid adder and subtractor using FinFET
and GnrFET technologies},
journal = {Integr.},
volume = {88},
pages = {32--42},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.002},
doi = {10.1016/J.VLSI.2022.09.002},
timestamp = {Tue, 06 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FloranceP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FragaO23,
author = {Luis Gerardo de la Fraga and
Brisbane Ovilla{-}Martinez},
title = {A chaotic {PRNG} tested with the heuristic Differential Evolution},
journal = {Integr.},
volume = {90},
pages = {22--26},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.001},
doi = {10.1016/J.VLSI.2023.01.001},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FragaO23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GengLZWLS23,
author = {Chao Geng and
Chunhua Luo and
Zhen Zhang and
Xiaoxiao Wang and
Yunlong Liu and
Bowen Sun},
title = {Design and optimization of on-chip thick-plated copper-transformers
for galvanic isolated {DC-DC} converter achieving up to 38.9{\%} peak
efficiency},
journal = {Integr.},
volume = {90},
pages = {146--156},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.015},
doi = {10.1016/J.VLSI.2023.01.015},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GengLZWLS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GhanimTUH23,
author = {Mustafa Ghanim and
Ozgur Tasdizen and
H. Fatih Ugurdag and
Ilker Hamzaoglu},
title = {An efficient algorithm for disparity map compression based on spatial
correlations and its low-cost hardware architecture},
journal = {Integr.},
volume = {93},
pages = {102069},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102069},
doi = {10.1016/J.VLSI.2023.102069},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GhanimTUH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GogoiGM23,
author = {Ankur Gogoi and
Bibhas Ghoshal and
Kanchan Manna},
title = {Fault-aware routing approach for mesh-based Network-on-Chip architecture},
journal = {Integr.},
volume = {93},
pages = {102043},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.05.007},
doi = {10.1016/J.VLSI.2023.05.007},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GogoiGM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GogolouKNS23,
author = {Vasiliki Gogolou and
Konstantinos Kozalakis and
Thomas Noulis and
Stylianos Siskos},
title = {Integrated {DC} - {DC} converter design methodology for design cycle
speed up},
journal = {Integr.},
volume = {88},
pages = {80--90},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.003},
doi = {10.1016/J.VLSI.2022.09.003},
timestamp = {Thu, 05 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GogolouKNS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Gonzalez-Zapata23,
author = {Astrid Maritza Gonz{\'{a}}lez{-}Zapata and
Luis Gerardo de la Fraga and
Brisbane Ovilla{-}Martinez and
Esteban Tlelo{-}Cuautle and
Israel Cruz{-}Vega},
title = {Enhanced {FPGA} implementation of Echo State Networks for chaotic
time series prediction},
journal = {Integr.},
volume = {92},
pages = {48--57},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.05.002},
doi = {10.1016/J.VLSI.2023.05.002},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Gonzalez-Zapata23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GoswamiSB23,
author = {Pingakshya Goswami and
Benjamin Carri{\'{o}}n Sch{\"{a}}fer and
Dinesh Bhatia},
title = {Machine learning based fast and accurate High Level Synthesis design
space exploration: From graph to synthesis},
journal = {Integr.},
volume = {88},
pages = {116--124},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.006},
doi = {10.1016/J.VLSI.2022.09.006},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GoswamiSB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuoCXSLWGW23,
author = {Zhongjie Guo and
Xinqi Cheng and
Ruiming Xu and
Changxu Su and
Chen Li and
Bin Wang and
Youmei Guo and
Yangle Wang},
title = {A 1Gpixel 10FPS {CMOS} image sensor using pixel array high-speed readout
technology},
journal = {Integr.},
volume = {89},
pages = {114--122},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.002},
doi = {10.1016/J.VLSI.2022.12.002},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GuoCXSLWGW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HoangCHPWSG23,
author = {Duy V{\~{o}} Ho{\`{a}}ng and
Dong Si Thien Chau and
Van Van Huynh and
Viet{-}Thanh Pham and
Rui Wang and
Hui Sun and
Giuseppe Grassi},
title = {Building discrete maps with memristor and multiple nonlinear terms},
journal = {Integr.},
volume = {90},
pages = {126--130},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.013},
doi = {10.1016/J.VLSI.2023.01.013},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HoangCHPWSG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HossainY23,
author = {Fakir Sharif Hossain and
Tomokazo Yuneda},
title = {An exquisitely sensitive variant-conscious post-silicon Hardware Trojan
detection},
journal = {Integr.},
volume = {93},
pages = {102064},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102064},
doi = {10.1016/J.VLSI.2023.102064},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HossainY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HussainMMD23,
author = {Sheikh Wasmir Hussain and
Telajala Venkata Mahendra and
Sandeep Mishra and
Anup Dandapat},
title = {{SMS-CAM:} Shared matchline scheme for content addressable memory},
journal = {Integr.},
volume = {88},
pages = {70--79},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.08.013},
doi = {10.1016/J.VLSI.2022.08.013},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HussainMMD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JangraK23,
author = {Vivek Jangra and
Manoj Kumar},
title = {A {PVT} tolerant low power wide tuning range differential voltage
controlled oscillator design in 90 nm {CMOS} technology},
journal = {Integr.},
volume = {93},
pages = {102054},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102054},
doi = {10.1016/J.VLSI.2023.102054},
timestamp = {Tue, 31 Oct 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JangraK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JingZSLCWJ23,
author = {Naifeng Jing and
Zihan Zhang and
Yongshuai Sun and
Pengyu Liu and
Liyan Chen and
Qin Wang and
Jianfei Jiang},
title = {Exploiting bit sparsity in both activation and weight in neural networks
accelerators},
journal = {Integr.},
volume = {88},
pages = {400--409},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.008},
doi = {10.1016/J.VLSI.2022.09.008},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/JingZSLCWJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JordanLKRB23,
author = {Michael Guilherme Jordan and
Bernardo Neuhaus Lignati and
Guilherme Korol and
Mateus Beck Rutzig and
Antonio Carlos Schneider Beck},
title = {MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning
for collaborative {CPU-FPGA} cloud systems},
journal = {Integr.},
volume = {93},
pages = {102052},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102052},
doi = {10.1016/J.VLSI.2023.102052},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/JordanLKRB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KandpalPSM23,
author = {Jyoti Kandpal and
Tika Ram Pokhrel and
Shalu Saini and
Alak Majumder},
title = {A variation resilient keeper design for high performance domino logic
applications},
journal = {Integr.},
volume = {88},
pages = {1--9},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.08.007},
doi = {10.1016/J.VLSI.2022.08.007},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KandpalPSM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KaushalR23,
author = {Shelja Kaushal and
Ashwani K. Rana},
title = {Reliable and low power Negative Capacitance Junctionless FinFET based
6T {SRAM} cell},
journal = {Integr.},
volume = {88},
pages = {313--319},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.014},
doi = {10.1016/J.VLSI.2022.10.014},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KaushalR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhaksariAE23,
author = {Afshin Khaksari and
Omid Akbari and
Behzad Ebrahimi},
title = {{BEAD:} Bounded error approximate adder with carry and sum speculations},
journal = {Integr.},
volume = {88},
pages = {353--361},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.015},
doi = {10.1016/J.VLSI.2022.10.015},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KhaksariAE23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhanAS23,
author = {Salma Khan and
Syed Azeemuddin and
Mohammed Arifuddin Sohel},
title = {ProHys {PUF:} {A} Proteresis - Hysteresis switch based Physical Unclonable
Function},
journal = {Integr.},
volume = {89},
pages = {207--216},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.009},
doi = {10.1016/J.VLSI.2022.12.009},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KhanAS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KiranAYD23,
author = {Harun Emre Kiran and
Akif Akgul and
Oktay Yildiz and
Emre Deniz},
title = {Lightweight encryption mechanism with discrete-time chaotic maps for
Internet of Robotic Things},
journal = {Integr.},
volume = {93},
pages = {102047},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.06.001},
doi = {10.1016/J.VLSI.2023.06.001},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KiranAYD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarKK23,
author = {Kunal Kumar and
Sandeep Kumar and
Binod Kumar Kanaujia},
title = {A highly robust {RF} 65 nm {CMOS} power amplifier design using Quasi-Newton
control algorithm for wireless system},
journal = {Integr.},
volume = {93},
pages = {102051},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.06.005},
doi = {10.1016/J.VLSI.2023.06.005},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KumarKK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarKP23,
author = {Navnit Kumar and
Manjeet Kumar and
Neeta Pandey},
title = {Electronically tunable positive and negative fractional order inductor
circuit using single topology},
journal = {Integr.},
volume = {88},
pages = {379--389},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.007},
doi = {10.1016/J.VLSI.2022.10.007},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KumarKP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarKP23a,
author = {Navnit Kumar and
Manjeet Kumar and
Neeta Pandey},
title = {{CCTA} based four different pairs of mutually coupled circuit using
single topology},
journal = {Integr.},
volume = {91},
pages = {43--53},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.009},
doi = {10.1016/J.VLSI.2023.02.009},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KumarKP23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarN23,
author = {Ankur Kumar and
Rajendra Kumar Nagaria},
title = {Reduction of variation and leakage in wide fan-in {OR} Logic domino
gate},
journal = {Integr.},
volume = {89},
pages = {229--240},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.010},
doi = {10.1016/J.VLSI.2022.12.010},
timestamp = {Sun, 19 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KumarN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarSPA23,
author = {Abhiram Kumar and
Pulkit Singh and
K. Abhimanyu Kumar Patro and
Bibhudendra Acharya},
title = {High-throughput and area-efficient architectures for image encryption
using {PRINCE} cipher},
journal = {Integr.},
volume = {90},
pages = {224--235},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.011},
doi = {10.1016/J.VLSI.2023.01.011},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KumarSPA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LaskaridisVMS23,
author = {Lazaros Laskaridis and
Christos K. Volos and
Jes{\'{u}}s Manuel Mu{\~{n}}oz{-}Pacheco and
Ioannis N. Stouboulos},
title = {Study of the dynamical behavior of an Ikeda-based map with a discrete
memristor},
journal = {Integr.},
volume = {89},
pages = {168--177},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.003},
doi = {10.1016/J.VLSI.2022.12.003},
timestamp = {Sun, 19 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LaskaridisVMS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LavanyaR23,
author = {T. Lavanya and
K. Rajalakshmi},
title = {Heterogenous ensemble learning driven multi-parametric assessment
model for hardware Trojan detection},
journal = {Integr.},
volume = {89},
pages = {217--228},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.011},
doi = {10.1016/J.VLSI.2022.12.011},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LavanyaR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LeonciniBMLG23,
author = {Mauro Leoncini and
Alessandro Bertolini and
Paolo Melillo and
Salvatore Levantino and
Massimo Ghioni},
title = {Integration of loop gain measurement circuit for stability evaluation
in {DC/DC} converters with time-based control},
journal = {Integr.},
volume = {90},
pages = {196--204},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.019},
doi = {10.1016/J.VLSI.2023.01.019},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LeonciniBMLG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LevyOBHR23,
author = {Akash Levy and
Michael Oduoza and
Akhilesh Balasingam and
Roger T. Howe and
Priyanka Raina},
title = {3-D coarse-grained reconfigurable array using multi-pole {NEM} relays
for programmable routing},
journal = {Integr.},
volume = {88},
pages = {249--261},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.001},
doi = {10.1016/J.VLSI.2022.10.001},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LevyOBHR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiWLH23,
author = {Jian{-}De Li and
Sying{-}Jyan Wang and
Katherine Shu{-}Min Li and
Tsung{-}Yi Ho},
title = {Design-for-reliability and on-the-fly fault tolerance procedure for
paper-based digital microfluidic biochips with multiple faults},
journal = {Integr.},
volume = {89},
pages = {185--196},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.013},
doi = {10.1016/J.VLSI.2022.11.013},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiWLH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuFWW23,
author = {Yuntao Liu and
Shuo Fang and
Lijing Wang and
Yun Wang},
title = {An ultra-low power dissipation {CMOS} temperature sensor with an inaccuracy
of {\(\pm\)}0.15 {\textdegree}C (3{\(\delta\)}) from -40 {\textdegree}C
to 125 {\textdegree}C},
journal = {Integr.},
volume = {91},
pages = {54--59},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.006},
doi = {10.1016/J.VLSI.2023.02.006},
timestamp = {Wed, 14 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiuFWW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuLZ23,
author = {Ruoran Liu and
Hongjun Liu and
Mengdi Zhao},
title = {Reveal the correlation between randomness and Lyapunov exponent of
\emph{n}-dimensional non-degenerate hyper chaotic map},
journal = {Integr.},
volume = {93},
pages = {102071},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102071},
doi = {10.1016/J.VLSI.2023.102071},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiuLZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Llamocca23,
author = {Daniel Llamocca},
title = {Fixed-point implementations for feed-forward artificial neural networks},
journal = {Integr.},
volume = {92},
pages = {1--14},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.04.002},
doi = {10.1016/J.VLSI.2023.04.002},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Llamocca23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LuoC23,
author = {Jing Luo and
Xue Chen},
title = {Transmission synchronization of multiple memristor chaotic circuits
via single input controller and its application in secure communication},
journal = {Integr.},
volume = {90},
pages = {40--50},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.005},
doi = {10.1016/J.VLSI.2023.01.005},
timestamp = {Wed, 22 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LuoC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaityMSD23,
author = {Sweta Bijali Maity and
Raj Kumar Maity and
Jagannath Samanta and
Chanchal Kumar De},
title = {Comments on "New low power and fast {SEC-DAEC} and {SEC-DAEC-TAEC}
codes for memories in space application"},
journal = {Integr.},
volume = {92},
pages = {35--37},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.04.004},
doi = {10.1016/J.VLSI.2023.04.004},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MaityMSD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Manikandan23,
author = {P. Manikandan},
title = {A feed-forward compensated {FVF} {LDO} regulator with no on-chip compensation
capacitors},
journal = {Integr.},
volume = {91},
pages = {89--97},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.005},
doi = {10.1016/J.VLSI.2023.03.005},
timestamp = {Wed, 14 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Manikandan23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MartinezFuentesMFT23,
author = {Oscar Martinez{-}Fuentes and
Aldo{-}Jonathan Mu{\~{n}}oz{-}V{\'{a}}zquez and
Guillermo Fern{\'{a}}ndez{-}Anaya and
Esteban Tlelo{-}Cuautle},
title = {Synchronization of fractional-order chaotic networks in Presnov form
via homogeneous controllers},
journal = {Integr.},
volume = {90},
pages = {71--80},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.007},
doi = {10.1016/J.VLSI.2023.01.007},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MartinezFuentesMFT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Mehri23,
author = {Milad Mehri},
title = {Analytic estimation of jitter and eye diagram based on transmission
line time domain response considering skin effect and stochastic crosstalk},
journal = {Integr.},
volume = {88},
pages = {222--232},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.008},
doi = {10.1016/J.VLSI.2022.10.008},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Mehri23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Mehri23a,
author = {Milad Mehri},
title = {A circuit level analysis of power distribution network on a {PCB}
layout exposed to intentional/unintentional electromagnetic threats},
journal = {Integr.},
volume = {89},
pages = {25--36},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.008},
doi = {10.1016/J.VLSI.2022.11.008},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Mehri23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MessadiKMV23,
author = {Manal Messadi and
Karim Kemih and
Lazaros Moysis and
Christos K. Volos},
title = {A new 4D Memristor chaotic system: Analysis and implementation},
journal = {Integr.},
volume = {88},
pages = {91--100},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.004},
doi = {10.1016/J.VLSI.2022.09.004},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MessadiKMV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MiddyaH23,
author = {Amitava Middya and
Terng{-}Yin Hsu},
title = {Design and implementation of virtual-single-length turbo decoder for
multi-user parallel decoding},
journal = {Integr.},
volume = {93},
pages = {102072},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102072},
doi = {10.1016/J.VLSI.2023.102072},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MiddyaH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MishraOM23,
author = {Ruby Mishra and
Manish Okade and
Kamalakanta Mahapatra},
title = {Efficient hardware mapping of Boolean substitution boxes based on
functional decomposition for {RFID} and {ISM} band IoT applications},
journal = {Integr.},
volume = {92},
pages = {38--47},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.04.005},
doi = {10.1016/J.VLSI.2023.04.005},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MishraOM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MorshedlouOR23,
author = {Farnaz Morshedlou and
Ali Asghar Orouji and
Nassim Ravanshad},
title = {An energy-efficient analog circuit for detecting {QRS} complexes from
{ECG} signal},
journal = {Integr.},
volume = {88},
pages = {390--399},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.001},
doi = {10.1016/J.VLSI.2022.11.001},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MorshedlouOR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MuhikanciOAYD23,
author = {{\"{O}}mer Yusuf Muhikanci and
Kemal Ozanoglu and
Engin Afacan and
Mustafa Berke Yelten and
G{\"{u}}nhan D{\"{u}}ndar},
title = {Radiation-aware analog circuit design via fully-automated simulation
environment},
journal = {Integr.},
volume = {90},
pages = {81--89},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.009},
doi = {10.1016/J.VLSI.2023.01.009},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MuhikanciOAYD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MumtazSH23,
author = {Summiya Mumtaz and
Nazli Sanam and
Tanveer ul Haq},
title = {An LA-group based design of the non-linear component of block cipher},
journal = {Integr.},
volume = {93},
pages = {102050},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.06.004},
doi = {10.1016/J.VLSI.2023.06.004},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MumtazSH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MurilloEscobarCLM23,
author = {Daniel Murillo{-}Escobar and
C{\'{e}}sar Cruz{-}Hern{\'{a}}ndez and
Rosa Martha L{\'{o}}pez{-}Guti{\'{e}}rrez and
Miguel {\'{A}}ngel Murillo{-}Escobar},
title = {Chaotic encryption of real-time {ECG} signal in embedded system for
secure telemedicine},
journal = {Integr.},
volume = {89},
pages = {261--270},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.004},
doi = {10.1016/J.VLSI.2023.01.004},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MurilloEscobarCLM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MurilloEscobarLCEM23,
author = {Miguel {\'{A}}ngel Murillo{-}Escobar and
Rosa Martha L{\'{o}}pez{-}Guti{\'{e}}rrez and
C{\'{e}}sar Cruz{-}Hern{\'{a}}ndez and
Erick Enrique Espinoza{-}Peralta and
Daniel Murillo{-}Escobar},
title = {Secure access microcontroller system based on fingerprint template
with hyperchaotic encryption},
journal = {Integr.},
volume = {90},
pages = {27--39},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.002},
doi = {10.1016/J.VLSI.2023.01.002},
timestamp = {Wed, 28 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MurilloEscobarLCEM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NarayanasamyG23,
author = {Poornima Narayanasamy and
Seetharaman Gopalakrishnan},
title = {Novel fault tolerance topology using corvus seek algorithm for application
specific NoC},
journal = {Integr.},
volume = {89},
pages = {146--154},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.011},
doi = {10.1016/J.VLSI.2022.11.011},
timestamp = {Sun, 19 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NarayanasamyG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Naskar23,
author = {Sourav Naskar},
title = {Complete design approach of a 3rd order continuous-time sigma-delta
{ADC} with {FIR} feedback and low-noise low-distortion op-amp achieving
101.8 dB {SNDR} and -110dB {THD}},
journal = {Integr.},
volume = {91},
pages = {98--106},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.002},
doi = {10.1016/J.VLSI.2023.03.002},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Naskar23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NathPLPYCLHC23,
author = {Bipasha Nath and
Sheng{-}Yu Peng and
Zu{-}Jia Lo and
Yu{-}Hsuan Pai and
Yi{-}Ting Yeh and
Huang{-}Hsiang Chang and
Yi{-}Ching Lu and
Shu{-}Hui Huang and
Fang{-}Chia Chang},
title = {A biphasic current-mode stimulator integrated circuit with a novel
residual charge compensation mechanism},
journal = {Integr.},
volume = {91},
pages = {79--88},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.003},
doi = {10.1016/J.VLSI.2023.03.003},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/NathPLPYCLHC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OuyangXQZWL23,
author = {Yiming Ouyang and
Dongyu Xu and
Chang Qian and
Wu Zhou and
Qi Wang and
Huaguo Liang},
title = {Dynamic detection of wireless interface faults and fault-tolerant
routing algorithm in WiNoC},
journal = {Integr.},
volume = {90},
pages = {236--244},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.008},
doi = {10.1016/J.VLSI.2023.02.008},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/OuyangXQZWL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PangWSYSYS23,
author = {Liang Pang and
Ziqi Wang and
Rui Shi and
Mengyun Yao and
Xiao Shi and
Hao Yan and
Longxin Shi},
title = {An efficient {SRAM} yield analysis method based on scaled-sigma adaptive
importance sampling with meta-model accelerated},
journal = {Integr.},
volume = {89},
pages = {155--167},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.015},
doi = {10.1016/J.VLSI.2022.11.015},
timestamp = {Thu, 11 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PangWSYSYS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PengSCLWBSWWWY23,
author = {Zhaokang Peng and
Nengyuan Sun and
Jiafeng Cheng and
Wenrui Liu and
Chunyang Wang and
Yijian Bi and
Caiban Sun and
Yufei Wang and
Yiming Wen and
Yubin Wang and
Weize Yu},
title = {A sequential strong {PUF} architecture based on reconfigurable neural
networks (RNNs) against state-of-the-art modeling attacks},
journal = {Integr.},
volume = {92},
pages = {83--90},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.05.003},
doi = {10.1016/J.VLSI.2023.05.003},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PengSCLWBSWWWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PetavratzisVS23,
author = {Eleftherios K. Petavratzis and
Christos K. Volos and
Ioannis N. Stouboulos},
title = {Experimental study of terrain coverage of an autonomous chaotic mobile
robot},
journal = {Integr.},
volume = {90},
pages = {104--114},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.010},
doi = {10.1016/J.VLSI.2023.01.010},
timestamp = {Wed, 22 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PetavratzisVS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PonrajJVS23,
author = {Jeyakumar Ponraj and
R. Jeyabharath and
P. Veena and
Tharumar Srihari},
title = {High-performance multiply-accumulate unit by integrating binary carry
select adder and counter-based modular wallace tree multiplier for
embedding system},
journal = {Integr.},
volume = {93},
pages = {102055},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102055},
doi = {10.1016/J.VLSI.2023.102055},
timestamp = {Sat, 28 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PonrajJVS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PullaiahMM23,
author = {T. Pullaiah and
K. Manjunathachari and
B. L. Malleswari},
title = {B{\(\Delta\)}-NIS: Performance analysis of an efficient data compression
technique for on-chip communication network},
journal = {Integr.},
volume = {89},
pages = {83--93},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.010},
doi = {10.1016/J.VLSI.2022.11.010},
timestamp = {Sun, 19 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PullaiahMM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RajaMSA23,
author = {Kaluri Praveen Raja and
Zeesha Mishra and
Pulkit Singh and
Bibhudendra Acharya},
title = {Efficient hardware implementations of lightweight Simeck Cipher for
resource-constrained applications},
journal = {Integr.},
volume = {88},
pages = {343--352},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.009},
doi = {10.1016/J.VLSI.2022.10.009},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RajaMSA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SakaliVM23,
author = {Raghavendra Kumar Sakali and
Sreehari Veeramachaneni and
Sk. Noor Mahammad},
title = {Preferential fault-tolerance multiplier design to mitigate soft errors
in FPGAs},
journal = {Integr.},
volume = {93},
pages = {102068},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102068},
doi = {10.1016/J.VLSI.2023.102068},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SakaliVM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SantosFAC23,
author = {Paulo C. Santos and
Bruno E. Forlin and
Marco A. Z. Alves and
Luigi Carro},
title = {Plug N' {PIM:} An integration strategy for Processing-in-Memory accelerators},
journal = {Integr.},
volume = {88},
pages = {185--195},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.016},
doi = {10.1016/J.VLSI.2022.09.016},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SantosFAC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SarangiB23,
author = {Satyabrata Sarangi and
Bevan M. Baas},
title = {Energy-efficient canonical Huffman decoders on many-core processor
arrays and FPGAs},
journal = {Integr.},
volume = {88},
pages = {156--165},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.015},
doi = {10.1016/J.VLSI.2022.09.015},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SarangiB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SelvapriyaS23,
author = {E. S. Selvapriya and
L. Suganthi},
title = {Design and implementation of low power Advanced Encryption Standard
cryptocore utilizing dynamic pipelined asynchronous model},
journal = {Integr.},
volume = {93},
pages = {102057},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102057},
doi = {10.1016/J.VLSI.2023.102057},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SelvapriyaS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SethiNB23,
author = {Deeksha Sethi and
Nithin Nagaraj and
Harikrishnan N. B.},
title = {Neurochaos feature transformation for Machine Learning},
journal = {Integr.},
volume = {90},
pages = {157--162},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.014},
doi = {10.1016/J.VLSI.2023.01.014},
timestamp = {Wed, 22 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SethiNB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShangZZLL23,
author = {Jiangwei Shang and
Kun Zhang and
Zhan Zhang and
Chuanyou Li and
Hongwei Liu},
title = {A high-performance convolution block oriented accelerator for MBConv-Based
CNNs},
journal = {Integr.},
volume = {88},
pages = {298--312},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.012},
doi = {10.1016/J.VLSI.2022.10.012},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShangZZLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShengLFJHYL23,
author = {Yongxia Sheng and
Huaguo Liang and
Bao Fang and
Cuiyun Jiang and
Zhengfeng Huang and
Maoxiang Yi and
Yingchun Lu},
title = {Design of approximate Booth multipliers based on error compensation},
journal = {Integr.},
volume = {90},
pages = {183--189},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.001},
doi = {10.1016/J.VLSI.2023.02.001},
timestamp = {Wed, 22 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShengLFJHYL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShihSL23,
author = {Xin{-}Yu Shih and
Chen{-}Yen Song and
Yao{-}Yu Lu},
title = {Unified chip hardware architecture of KD-tree mean-based trainer and
speeding-up classifier with repeat-point searching for various applications},
journal = {Integr.},
volume = {93},
pages = {102056},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102056},
doi = {10.1016/J.VLSI.2023.102056},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ShihSL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShuklaJR23,
author = {Satyam Shukla and
Punyesh Kumar Jha and
Kailash Chandra Ray},
title = {An energy-efficient single-cycle {RV32I} microprocessor for edge computing
applications},
journal = {Integr.},
volume = {88},
pages = {233--240},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.005},
doi = {10.1016/J.VLSI.2022.09.005},
timestamp = {Tue, 06 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShuklaJR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SiLZ23,
author = {Yuanyuan Si and
Hongjun Liu and
Mengdi Zhao},
title = {Constructing keyed strong S-Box with higher nonlinearity based on
2D hyper chaotic map and algebraic operation},
journal = {Integr.},
volume = {88},
pages = {269--277},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.011},
doi = {10.1016/J.VLSI.2022.10.011},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SiLZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SinghK23,
author = {Jayant K. Singh and
Garima Kapur},
title = {Design of an adaptive winner takes all circuit explaining features
of binocular rivalry in visual brain},
journal = {Integr.},
volume = {88},
pages = {11--19},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.08.009},
doi = {10.1016/J.VLSI.2022.08.009},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SinghK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SongZTZCU23,
author = {Rui Song and
Jun Zhang and
Jie Tong and
Minghao Zhang and
Sandy Cochran and
Ian Underwood},
title = {Design and analysis of a frequency division and duty cycle control
circuit for on-chip signal synthesis},
journal = {Integr.},
volume = {90},
pages = {115--125},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.017},
doi = {10.1016/J.VLSI.2023.01.017},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SongZTZCU23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SunCLPSWSWY23,
author = {Nengyuan Sun and
Jiafeng Cheng and
Wenrui Liu and
Zhaokang Peng and
Caiban Sun and
Chunyang Wang and
Heng Sha and
Yufei Wang and
Weize Yu},
title = {A novel on-chip linear and switching mixed regulation against power
analysis attacks},
journal = {Integr.},
volume = {93},
pages = {102049},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.06.003},
doi = {10.1016/J.VLSI.2023.06.003},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SunCLPSWSWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TasnimRYST23,
author = {Maliha Tasnim and
Chinmay Raje and
Shuyuan Yu and
Elaheh Sadredini and
Sheldon X.{-}D. Tan},
title = {{MAGIC-DHT:} Fast in-memory computing for Discrete Hadamard Transform},
journal = {Integr.},
volume = {93},
pages = {102060},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102060},
doi = {10.1016/J.VLSI.2023.102060},
timestamp = {Wed, 01 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TasnimRYST23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TeibMK23,
author = {Malek Teib and
Alexandre Malherbe and
Edith Kussener},
title = {Multi-harvesting smart solution for self-powered wearable objects:
System-level model and transistor-level design},
journal = {Integr.},
volume = {91},
pages = {165--172},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.010},
doi = {10.1016/J.VLSI.2023.03.010},
timestamp = {Wed, 14 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TeibMK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TontiniGMPP23,
author = {Alessandro Tontini and
Leonardo Gasparini and
Enrico Manuzzato and
Matteo Perenzoni and
Roberto Passerone},
title = {Comparative evaluation of background-rejection techniques for SPAD-based
LiDAR systems},
journal = {Integr.},
volume = {90},
pages = {1--10},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.007},
doi = {10.1016/J.VLSI.2022.12.007},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TontiniGMPP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TrikABMVM23,
author = {Mohammad Trik and
Hoda Akhavan and
Amir{-}Massoud Bidgoli and
Ali Mohammad Norouzzadeh Gil Molk and
Hossein Vashani and
Saadat Pour Mozaffari},
title = {A new adaptive selection strategy for reducing latency in networks
on chip},
journal = {Integr.},
volume = {89},
pages = {9--24},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.004},
doi = {10.1016/J.VLSI.2022.11.004},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TrikABMVM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TripathiJB23,
author = {Sayan Tripathi and
Jhilam Jana and
Jaydeb Bhaumik},
title = {New low power and fast {SEC-DAEC} and {SEC-DAEC-TAEC} codes for memories
in space application},
journal = {Integr.},
volume = {89},
pages = {56--72},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.003},
doi = {10.1016/J.VLSI.2022.11.003},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TripathiJB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TrujilloToledoLGECTAI23,
author = {Diego Armando Trujillo{-}Toledo and
Oscar Roberto L{\'{o}}pez{-}Bonilla and
Enrique Efr{\'{e}}n Garc{\'{\i}}a{-}Guerrero and
Jos{\'{e}} Jaime Esqueda{-}Elizondo and
Jos{\'{e}} Ricardo C{\'{a}}rdenas{-}Valdez and
Ulises Jes{\'{u}}s Tamayo{-}P{\'{e}}rez and
Oscar Adrian Aguirre{-}Castro and
Everardo Inzunza{-}Gonz{\'{a}}lez},
title = {Real-time medical image encryption for H-IoT applications using improved
sequences from chaotic maps},
journal = {Integr.},
volume = {90},
pages = {131--145},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.008},
doi = {10.1016/J.VLSI.2023.01.008},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TrujilloToledoLGECTAI23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VafaeiHAS23,
author = {Mehrnoosh Vafaei and
M. R. Hosseini and
Ebrahim Abiri and
Mohammad Reza Salehi},
title = {A 0.2-V 1.2 nW 1-KS/s {SAR} {ADC} with a novel comparator structure
for biomedical applications},
journal = {Integr.},
volume = {88},
pages = {362--370},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.016},
doi = {10.1016/J.VLSI.2022.10.016},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/VafaeiHAS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VelazquezMoralesSHS23,
author = {Carlos Alejandro Vel{\'{a}}zquez{-}Morales and
Carlos S{\'{a}}nchez{-}L{\'{o}}pez and
C. M. Hern{\'{a}}ndez{-}Mej{\'{\i}}a and
Luis Abraham S{\'{a}}nchez{-}Gaspariano},
title = {Artificial synapse topologies using arbitrary-order memristors},
journal = {Integr.},
volume = {89},
pages = {178--184},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.12.004},
doi = {10.1016/J.VLSI.2022.12.004},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/VelazquezMoralesSHS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangLCFCW23,
author = {Zheng Wang and
Xu Liu and
Yunao Chen and
Qiumeng Fan and
Zhijie Chen and
Peiyuan Wan},
title = {Design of analog front-end integrated circuit of tactile sensor for
human-machine interface},
journal = {Integr.},
volume = {93},
pages = {102065},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102065},
doi = {10.1016/J.VLSI.2023.102065},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangLCFCW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangLWPC23,
author = {Weizheng Wang and
Jian Liang and
Xiangqi Wang and
Xianmin Pan and
Shuo Cai},
title = {A secure scan architecture using parallel latch-based lock},
journal = {Integr.},
volume = {93},
pages = {102067},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102067},
doi = {10.1016/J.VLSI.2023.102067},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangLWPC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangPTJ23,
author = {Zhen Wang and
Fatemeh Parastesh and
Huaigu Tian and
Sajad Jafari},
title = {Symmetric synchronization behavior of multistable chaotic systems
and circuits in attractive and repulsive couplings},
journal = {Integr.},
volume = {89},
pages = {37--46},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.007},
doi = {10.1016/J.VLSI.2022.11.007},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangPTJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangTLJSLLC23,
author = {Chua{-}Chin Wang and
Lean Karlo S. Tolentino and
Shao{-}Wei Lu and
Oliver Lexter July A. Jose and
Ralph Gerard B. Sangalang and
Tzung{-}Je Lee and
Pang{-}Yen Lou and
Wei{-}Chih Chang},
title = {A 2xVDD digital output buffer with gate driving stability and non-overlapping
signaling control for slew-rate auto-adjustment using 16-nm FinFET
{CMOS} process},
journal = {Integr.},
volume = {90},
pages = {245--260},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.004},
doi = {10.1016/J.VLSI.2023.02.004},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangTLJSLLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XiaoXWQL23,
author = {Lu Xiao and
Zheng Xiao and
Fan Wu and
Yunchuan Qin and
Kenli Li},
title = {Optimization on operation sorting for {HLS} scheduling algorithms},
journal = {Integr.},
volume = {93},
pages = {102058},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102058},
doi = {10.1016/J.VLSI.2023.102058},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/XiaoXWQL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XinL23,
author = {Zeng{-}Jun Xin and
Qiang Lai},
title = {A novel one-equilibrium memristive chaotic system with multi-parameter
amplitude modulation and large-scale offset boosting},
journal = {Integr.},
volume = {92},
pages = {106--115},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.05.008},
doi = {10.1016/J.VLSI.2023.05.008},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/XinL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuGYL23,
author = {Ruiming Xu and
Zhongjie Guo and
Ningmei Yu and
Suiyang Liu},
title = {A high-speed 13-bit two-step single-slope {ADC} for large array {CMOS}
image sensors},
journal = {Integr.},
volume = {91},
pages = {119--125},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.009},
doi = {10.1016/J.VLSI.2023.03.009},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/XuGYL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuOZL23,
author = {Dongyu Xu and
Yiming Ouyang and
Wu Zhou and
Huaguo Liang},
title = {Improving power and performance of on-chip network through virtual
channel sharing and power gating},
journal = {Integr.},
volume = {93},
pages = {102059},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102059},
doi = {10.1016/J.VLSI.2023.102059},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/XuOZL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuZMLHL23,
author = {Hui Xu and
Jing Zhou and
Ruijun Ma and
Huaguo Liang and
Zhengfeng Huang and
Chaoming Liu},
title = {{LQNTL:} Low-overhead quadruple-node-upset self-recovery latch based
on triple-mode redundancy},
journal = {Integr.},
volume = {91},
pages = {126--135},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.008},
doi = {10.1016/J.VLSI.2023.03.008},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/XuZMLHL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YanLGCWS23,
author = {Shaohui Yan and
Lin Li and
Binxian Gu and
Yu Cui and
Jianjian Wang and
Jincai Song},
title = {Design of hyperchaotic system based on multi-scroll and its encryption
algorithm in color image},
journal = {Integr.},
volume = {88},
pages = {203--221},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.002},
doi = {10.1016/J.VLSI.2022.10.002},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YanLGCWS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YanWWWSL23,
author = {Shaohui Yan and
Jianjian Wang and
Ertong Wang and
Qiyu Wang and
Xi Sun and
Lin Li},
title = {A four-dimensional chaotic system with coexisting attractors and its
backstepping control and synchronization},
journal = {Integr.},
volume = {91},
pages = {67--78},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.001},
doi = {10.1016/J.VLSI.2023.03.001},
timestamp = {Wed, 14 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YanWWWSL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangLR23,
author = {Huijing Yang and
Shichang Li and
Mingyuan Ren},
title = {A low offset low power {CMOS} dynamic comparator for analog to digital
converters},
journal = {Integr.},
volume = {91},
pages = {136--143},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.007},
doi = {10.1016/J.VLSI.2023.03.007},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YangLR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangW0FC00023,
author = {Yipei Yang and
Zongyue Wang and
Jing Ye and
Junfeng Fan and
Shuai Chen and
Huawei Li and
Xiaowei Li and
Yuan Cao},
title = {Chosen ciphertext correlation power analysis on Kyber},
journal = {Integr.},
volume = {91},
pages = {10--22},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.012},
doi = {10.1016/J.VLSI.2023.02.012},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YangW0FC00023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YaoWZ23,
author = {Liang Yao and
Xinya Wu and
Huishan Zhang},
title = {{DCDRO:A} true random number generator based on dynamically configurable
dual-output ring oscillator},
journal = {Integr.},
volume = {93},
pages = {102053},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102053},
doi = {10.1016/J.VLSI.2023.102053},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YaoWZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YuXSBY23,
author = {Shengqi Yu and
Fei Xia and
Rishad A. Shafik and
Domenico Balsamo and
Alex Yakovlev},
title = {Approximate digital-in analog-out multiplier with asymmetric nonvolatility
and low energy consumption},
journal = {Integr.},
volume = {93},
pages = {102045},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.05.009},
doi = {10.1016/J.VLSI.2023.05.009},
timestamp = {Wed, 01 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YuXSBY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YuXXYHCYL23,
author = {Fei Yu and
Si Xu and
Xiaoli Xiao and
Wei Yao and
Yuanyuan Huang and
Shuo Cai and
Bo Yin and
Yi Li},
title = {Dynamics analysis, {FPGA} realization and image encryption application
of a 5D memristive exponential hyperchaotic system},
journal = {Integr.},
volume = {90},
pages = {58--70},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.01.006},
doi = {10.1016/J.VLSI.2023.01.006},
timestamp = {Sat, 26 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YuXXYHCYL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YuYZH23,
author = {Lanya Yu and
Jinfeng Yan and
Xiao Zhao and
Jinhui Huang},
title = {A fast transient response current-feedback low-dropout regulator with
dynamic current-enhancement technique},
journal = {Integr.},
volume = {88},
pages = {262--268},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.012},
doi = {10.1016/J.VLSI.2022.09.012},
timestamp = {Tue, 06 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YuYZH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZacharelosNSSN23,
author = {Efstratios Zacharelos and
Italo Nunziata and
Gerardo Saggese and
Antonio G. M. Strollo and
Ettore Napoli},
title = {Approximate squaring circuits exploiting recursive architectures},
journal = {Integr.},
volume = {91},
pages = {35--42},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.02.007},
doi = {10.1016/J.VLSI.2023.02.007},
timestamp = {Tue, 12 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZacharelosNSSN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZengDT23,
author = {Wei Zeng and
Azadeh Davoodi and
Rasit Onur Topaloglu},
title = {ObfusX: Routing obfuscation with explanatory analysis of a machine
learning attack},
journal = {Integr.},
volume = {89},
pages = {47--55},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.013},
doi = {10.1016/J.VLSI.2022.10.013},
timestamp = {Sun, 19 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZengDT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZengGZZCL23,
author = {Yanhan Zeng and
Qianhui Ge and
Xin Zhang and
Yuting Zhang and
Meiling Chen and
Yongfu Li},
title = {A CAFVF-based output-capacitor-less {LDO} with {PSRR} improvement
by feed forward and negative capacitance},
journal = {Integr.},
volume = {93},
pages = {102063},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102063},
doi = {10.1016/J.VLSI.2023.102063},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZengGZZCL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangD23,
author = {Chenkai Zhang and
Baoxiang Du},
title = {A fast piecewise image encryption scheme combining {NC1DNSM} and P-Box},
journal = {Integr.},
volume = {88},
pages = {328--342},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.003},
doi = {10.1016/J.VLSI.2022.10.003},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhangD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangLGZMYZ23,
author = {Li Zhang and
Qishen Lv and
Di Gao and
Xian Zhou and
Wenchao Meng and
Qinmin Yang and
Cheng Zhuo},
title = {A fine-grained mixed precision {DNN} accelerator using a two-stage
big-little core {RISC-V} {MCU}},
journal = {Integr.},
volume = {88},
pages = {241--248},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.006},
doi = {10.1016/J.VLSI.2022.10.006},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhangLGZMYZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangSCTSAT23,
author = {Jinwei Zhang and
Sheriff Sadiqbatcha and
Liang Chen and
Cuong Thi and
Sachin Sachdeva and
Hussam Amrouch and
Sheldon X.{-}D. Tan},
title = {Hot-spot aware thermoelectric array based cooling for multicore processors},
journal = {Integr.},
volume = {89},
pages = {73--82},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.11.006},
doi = {10.1016/J.VLSI.2022.11.006},
timestamp = {Tue, 19 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangSCTSAT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangWM23,
author = {Jiahong Zhang and
Zhuo Wang and
Chao Ma},
title = {A {CMOS} transimpedance amplifier with broad-band and high gain based
on negative Miller capacitance},
journal = {Integr.},
volume = {91},
pages = {60--66},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.03.004},
doi = {10.1016/J.VLSI.2023.03.004},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhangWM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangZLL23,
author = {Qing Zhang and
Yuhang Zhang and
Jizuo Li and
Yongfu Li},
title = {Corrigendum to "WDP-BNN: Efficient wafer defect pattern classification
via binarized neural network" [Integration 85 {(2022)} 76-86]},
journal = {Integr.},
volume = {88},
pages = {10},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.001},
doi = {10.1016/J.VLSI.2022.09.001},
timestamp = {Wed, 31 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangZLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhaoHZWCHH23,
author = {Yunan Zhao and
Haomin Hou and
Shuhao Zhang and
Hao Wang and
Sheng Chang and
Qijun Huang and
Jin He},
title = {A 28-GHz wideband power amplifier with dual-pole tuning superposition
technique in 55-nm {RF} {CMOS}},
journal = {Integr.},
volume = {88},
pages = {101--107},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.007},
doi = {10.1016/J.VLSI.2022.09.007},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhaoHZWCHH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhaoLN23,
author = {Mengdi Zhao and
Hongjun Liu and
Yujun Niu},
title = {Batch generating keyed strong S-Boxes with high nonlinearity using
2D hyper chaotic map},
journal = {Integr.},
volume = {92},
pages = {91--98},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.05.006},
doi = {10.1016/J.VLSI.2023.05.006},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhaoLN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhouCJZ23,
author = {Jindong Zhou and
Yuyang Chen and
Youliang Jing and
Pingqiang Zhou},
title = {The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs},
journal = {Integr.},
volume = {88},
pages = {196--202},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.017},
doi = {10.1016/J.VLSI.2022.09.017},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhouCJZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhouOLX23,
author = {Wu Zhou and
Yiming Ouyang and
Jianhua Li and
Dongyu Xu},
title = {A transparent virtual channel power gating method for on-chip network
routers},
journal = {Integr.},
volume = {88},
pages = {286--297},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.10.004},
doi = {10.1016/J.VLSI.2022.10.004},
timestamp = {Sun, 25 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhouOLX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhouQCYSS23,
author = {Chencan Zhou and
Jie Qiu and
Yang Cao and
Geng{-}Chen Yang and
Qin{-}Qin Shen and
Quan Shi},
title = {An accelerated modulus-based matrix splitting iteration method for
mixed-size cell circuits legalization},
journal = {Integr.},
volume = {88},
pages = {20--31},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.08.010},
doi = {10.1016/J.VLSI.2022.08.010},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhouQCYSS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AbbassiGAHM22,
author = {Nessrine Abbassi and
Mohamed Gafsi and
Rim Amdouni and
Mohamed Ali Hajjaji and
Abdellatif Mtibaa},
title = {Hardware implementation of a robust image cryptosystem using reversible
cellular-automata rules and 3-D chaotic systems},
journal = {Integr.},
volume = {87},
pages = {49--66},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.007},
doi = {10.1016/J.VLSI.2022.06.007},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AbbassiGAHM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AbelNG22,
author = {Inga Abel and
Maximilian Neuner and
Helmut Graeb},
title = {A functional block decomposition method for automatic op-amp design},
journal = {Integr.},
volume = {85},
pages = {108--120},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.04.006},
doi = {10.1016/J.VLSI.2022.04.006},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AbelNG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AghasharifMBT22,
author = {Farshad Aghasharif and
Mohammadreza Malekpour and
Reza Bigdeli and
Pooya Torkzadeh},
title = {An 8 bits, {RF} UHF-Band {DAC} based on interleaved bandpass delta
sigma modulator assisted by background digital calibration},
journal = {Integr.},
volume = {84},
pages = {102--110},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.11.001},
doi = {10.1016/J.VLSI.2021.11.001},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AghasharifMBT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AhsanEKZ22,
author = {Javad Ahsan and
Mohammad Esmaeildoust and
Amer Kaabi and
Vahid Zarei},
title = {Efficient {FPGA} implementation of {RNS} Montgomery multiplication
using balanced {RNS} bases},
journal = {Integr.},
volume = {84},
pages = {72--83},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.12.006},
doi = {10.1016/J.VLSI.2021.12.006},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AhsanEKZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AlagarsamyMLK22,
author = {Aravindhan Alagarsamy and
Sundarakannan Mahilmaran and
Gopalakrishnan Lakshminarayanan and
Seok{-}Bum Ko},
title = {{FRDS:} An efficient unique on-Chip interconnection network architecture},
journal = {Integr.},
volume = {87},
pages = {90--103},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.014},
doi = {10.1016/J.VLSI.2022.06.014},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AlagarsamyMLK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AmdouniGGHMB22,
author = {Rim Amdouni and
Mohamed Gafsi and
Ramzi Guesmi and
Mohamed Ali Hajjaji and
Abdellatif Mtibaa and
El{-}Bay Bourennane},
title = {High-performance hardware architecture of a robust block-cipher algorithm
based on different chaotic maps and {DNA} sequence encoding},
journal = {Integr.},
volume = {87},
pages = {346--363},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.08.002},
doi = {10.1016/J.VLSI.2022.08.002},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AmdouniGGHMB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AminzadehV22,
author = {Hamed Aminzadeh and
Mohammad Mahdi Valinezhad},
title = {Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode
current generator},
journal = {Integr.},
volume = {87},
pages = {284--292},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.014},
doi = {10.1016/J.VLSI.2022.07.014},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AminzadehV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AparicioIL22,
author = {Hernan Aparicio and
Pablo Ituero and
Marisa L{\'{o}}pez{-}Vallejo},
title = {Reference-free power supply monitor with enhanced robustness against
process and temperature variations},
journal = {Integr.},
volume = {82},
pages = {127--135},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.09.004},
doi = {10.1016/J.VLSI.2021.09.004},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AparicioIL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BarenysVL22,
author = {Arnau Salas Barenys and
Neus Vidal and
Jos{\'{e}} Mar{\'{\i}}a L{\'{o}}pez{-}Villegas},
title = {Very compact 3D-printed folded branch-line hybrid coupler based on
loaded helical-microstrip transmission lines},
journal = {Integr.},
volume = {84},
pages = {142--150},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.001},
doi = {10.1016/J.VLSI.2022.02.001},
timestamp = {Fri, 13 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BarenysVL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BerndtMRB22,
author = {Augusto Andre Souza Berndt and
Cristina Meinhardt and
Andr{\'{e}} In{\'{a}}cio Reis and
Paulo F. Butzen},
title = {Optimizing machine learning logic circuits with constant signal propagation},
journal = {Integr.},
volume = {87},
pages = {293--305},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.08.004},
doi = {10.1016/J.VLSI.2022.08.004},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BerndtMRB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BouhdjeurATTM22,
author = {Abderrezzaq Bouhdjeur and
Mohamed Salah Azzaz and
Djamel Teguig and
Camel Tanougast and
Abdelmadjid Maali},
title = {An optimised hardware architecture of the angular-domain cyclostationary
detector for cognitive radio communications},
journal = {Integr.},
volume = {87},
pages = {111--121},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.001},
doi = {10.1016/J.VLSI.2022.07.001},
timestamp = {Tue, 06 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BouhdjeurATTM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BoulhamBL22,
author = {Ihab Abderraouf Boulham and
Ahsene Boubakir and
Salim Labiod},
title = {Neural network {\(\mathscr{L}\)}1 adaptive control for a class of
uncertain fractional order nonlinear systems},
journal = {Integr.},
volume = {83},
pages = {1--11},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.11.002},
doi = {10.1016/J.VLSI.2021.11.002},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BoulhamBL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BukkapatnamS22,
author = {Krishnaveni Bukkapatnam and
Jaikaran Singh},
title = {{VLSI} implementation of low-power and area efficient parallel memory
allocation with {EC-TCAM}},
journal = {Integr.},
volume = {87},
pages = {336--345},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.08.011},
doi = {10.1016/J.VLSI.2022.08.011},
timestamp = {Wed, 05 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BukkapatnamS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CaoG22,
author = {Chao Cao and
Haijun Guo},
title = {High-resolution calibrated successive-approximation-register analog-to-digital
converter},
journal = {Integr.},
volume = {87},
pages = {205--210},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.08.005},
doi = {10.1016/J.VLSI.2022.08.005},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CaoG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenFFZCX22,
author = {Xuanqi Chen and
Yuxiang Fu and
Jun Feng and
Jiaxu Zhang and
Shixi Chen and
Jiang Xu},
title = {Improving the thermal reliability of photonic chiplets on multicore
processors},
journal = {Integr.},
volume = {86},
pages = {9--21},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.03.004},
doi = {10.1016/J.VLSI.2022.03.004},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChenFFZCX22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChengGP22,
author = {Yuanqing Cheng and
Xiaochen Guo and
Vasilis F. Pavlidis},
title = {Emerging monolithic 3D integration: Opportunities and challenges from
the computer system perspective},
journal = {Integr.},
volume = {85},
pages = {97--107},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.04.004},
doi = {10.1016/J.VLSI.2022.04.004},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChengGP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChentoufI22,
author = {Mohamed Chentouf and
Zine El Abidine Alaoui Ismaili},
title = {A {PUS} based nets weighting mechanism for power, hold, and setup
timing optimization},
journal = {Integr.},
volume = {84},
pages = {122--130},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.01.006},
doi = {10.1016/J.VLSI.2022.01.006},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChentoufI22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChungK22,
author = {Sehyeon Chung and
Taewhan Kim},
title = {{ECO} routing based on network flow method},
journal = {Integr.},
volume = {86},
pages = {1--8},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.04.002},
doi = {10.1016/J.VLSI.2022.04.002},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChungK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DeepsitaM22,
author = {S. Skandha Deepsita and
Sk. Noor Mahammad},
title = {Low power, high speed approximate multiplier for error resilient applications},
journal = {Integr.},
volume = {84},
pages = {37--46},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.01.001},
doi = {10.1016/J.VLSI.2022.01.001},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DeepsitaM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DelwarSBBRCR22,
author = {Tahesin Samira Delwar and
Abrar Siddique and
Manas Ranjan Biswal and
Prangyadarsini Behera and
Ahmed Nabih Zaki Rashed and
Yeji Choi and
Jee{-}Youl Ryu},
title = {A novel dual mode configurable and tunable high-gain, high-efficient
{CMOS} power amplifier for 5G applications},
journal = {Integr.},
volume = {83},
pages = {77--87},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.12.004},
doi = {10.1016/J.VLSI.2021.12.004},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DelwarSBBRCR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ElamienMEB22,
author = {Mohamed B. Elamien and
Brent J. Maundy and
Ahmed S. Elwakil and
Leonid Belostotski},
title = {Second-order cascode-based filters},
journal = {Integr.},
volume = {84},
pages = {111--121},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.12.009},
doi = {10.1016/J.VLSI.2021.12.009},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ElamienMEB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ElwakilMPE22,
author = {Ahmed S. Elwakil and
Brent J. Maundy and
Costas Psychalinos and
Mohamed B. Elamien},
title = {Synthesis of resonance-based common-gate fully differential band-pass
filters},
journal = {Integr.},
volume = {87},
pages = {67--73},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.002},
doi = {10.1016/J.VLSI.2022.06.002},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ElwakilMPE22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FreitasSMNM22,
author = {David C. C. Freitas and
Jarbas Silveira and
C{\'{e}}sar A. M. Marcon and
Lirida A. B. Naviner and
Jo{\~{a}}o Cesar M. Mota},
title = {OPCoSA: an Optimized Product Code for space applications},
journal = {Integr.},
volume = {84},
pages = {131--141},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.005},
doi = {10.1016/J.VLSI.2022.02.005},
timestamp = {Thu, 20 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FreitasSMNM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GhorbaniDZB22,
author = {Ali Ghorbani and
Mehdi Dolatshahi and
Sayed Mohammad Ali Zanjani and
Behrang Barekatain},
title = {A new low-power Dynamic-GDI full adder in {CNFET} technology},
journal = {Integr.},
volume = {83},
pages = {46--59},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.12.001},
doi = {10.1016/J.VLSI.2021.12.001},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GhorbaniDZB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GogoiGSKM22,
author = {Ankur Gogoi and
Bibhas Ghoshal and
Akash Sachan and
Rakesh Kumar and
Kanchan Manna},
title = {Application driven routing for mesh based Network-on-Chip architectures},
journal = {Integr.},
volume = {84},
pages = {26--36},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.12.008},
doi = {10.1016/J.VLSI.2021.12.008},
timestamp = {Thu, 18 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GogoiGSKM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuldenZC22,
author = {Mehmet Ali Gulden and
Ertan Zencir and
Enver {\c{C}}avus},
title = {Self calibrated cooler-less microbolometer readout architecture},
journal = {Integr.},
volume = {82},
pages = {14--19},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.08.014},
doi = {10.1016/J.VLSI.2021.08.014},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GuldenZC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuoEMWSS22,
author = {Xinfei Guo and
Mohamed El{-}Hadedy and
Sergiu Mosanu and
Xiangdong Wei and
Kevin Skadron and
Mircea R. Stan},
title = {Agile-AES: Implementation of configurable {AES} primitive with agile
design approach},
journal = {Integr.},
volume = {85},
pages = {87--96},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.04.005},
doi = {10.1016/J.VLSI.2022.04.005},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GuoEMWSS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuptaSBA22,
author = {Ashima Gupta and
Anil Singh and
Manu Bansal and
Alpana Agarwal},
title = {Functional validation of highly synthesizable voltage comparator on
{FPGA}},
journal = {Integr.},
volume = {84},
pages = {151--158},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.004},
doi = {10.1016/J.VLSI.2022.02.004},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GuptaSBA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HaoCZ22,
author = {Rui Hao and
Yici Cai and
Qiang Zhou},
title = {Intelligent and kernelized placement: {A} survey},
journal = {Integr.},
volume = {86},
pages = {44--50},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.05.002},
doi = {10.1016/J.VLSI.2022.05.002},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HaoCZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HeC22,
author = {Xiang He and
Zhufei Chu},
title = {Stochastic circuit synthesis via satisfiability},
journal = {Integr.},
volume = {84},
pages = {84--91},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.11.003},
doi = {10.1016/J.VLSI.2021.11.003},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HeC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HuSNCCK22,
author = {Ke Hu and
Wenhao Sun and
Zhongbo Nie and
Ran Cheng and
Song Chen and
Yi Kang},
title = {Real-time infrared small target detection network and accelerator
design},
journal = {Integr.},
volume = {87},
pages = {241--252},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.008},
doi = {10.1016/J.VLSI.2022.07.008},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HuSNCCK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JanvejaT22,
author = {Meenali Janveja and
Gaurav Trivedi},
title = {An area and power efficient {VLSI} architecture for {ECG} feature
extraction for wearable IoT healthcare applications},
journal = {Integr.},
volume = {82},
pages = {96--103},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.09.006},
doi = {10.1016/J.VLSI.2021.09.006},
timestamp = {Sat, 25 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JanvejaT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JoshiR22,
author = {Manoj Joshi and
Ashish Ranjan},
title = {Low power chaotic oscillator employing {CMOS}},
journal = {Integr.},
volume = {85},
pages = {57--62},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.011},
doi = {10.1016/J.VLSI.2022.02.011},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/JoshiR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KangarshahiZ22,
author = {Azadeh Norouzi Kangarshahi and
Abdulhamid Zahedi},
title = {A novel class-E class-D doherty power amplifier based on past matching
network with linearity region extension and flat output power},
journal = {Integr.},
volume = {87},
pages = {264--274},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.08.001},
doi = {10.1016/J.VLSI.2022.08.001},
timestamp = {Wed, 05 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KangarshahiZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KnechtelAFPNASA22,
author = {Johann Knechtel and
Tarek Ashraf and
Natascha Fernengel and
Satwik Patnaik and
Mohammed Nabeel and
Mohammed Ashraf and
Ozgur Sinanoglu and
Hussam Amrouch},
title = {Design-time exploration of voltage switching against power analysis
attacks in 14 nm FinFET technology},
journal = {Integr.},
volume = {85},
pages = {27--34},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.006},
doi = {10.1016/J.VLSI.2022.02.006},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KnechtelAFPNASA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KortliGJAA22,
author = {Yassin Kortli and
Souhir Gabsi and
Maher Jridi and
Ayman Alfalou and
Mohamed Atri},
title = {Hw/Sw Co-Design technique for 2D fast fourier transform algorithm
on Zynq SoC},
journal = {Integr.},
volume = {82},
pages = {78--88},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.09.005},
doi = {10.1016/J.VLSI.2021.09.005},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KortliGJAA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarMMRB22,
author = {Mithilesh Kumar and
Alak Majumder and
Abir J. Mondal and
Arijit Raychowdhury and
Bidyut K. Bhattacharyya},
title = {A low power and {PVT} variation tolerant mux-latch for serializer
interface and on-chip serial link},
journal = {Integr.},
volume = {87},
pages = {364--377},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.08.008},
doi = {10.1016/J.VLSI.2022.08.008},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KumarMMRB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarS22,
author = {B. Dinesh Kumar and
Hitesh Shrimali},
title = {Design and implementation of a second order {PLL} based frequency
synthesizer for implantable medical devices},
journal = {Integr.},
volume = {86},
pages = {57--63},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.05.004},
doi = {10.1016/J.VLSI.2022.05.004},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KumarS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiCZ22,
author = {Lin Li and
Yici Cai and
Qiang Zhou},
title = {A survey on machine learning-based routing for {VLSI} physical design},
journal = {Integr.},
volume = {86},
pages = {51--56},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.05.003},
doi = {10.1016/J.VLSI.2022.05.003},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiCZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiFZYWWZ22,
author = {Chuxi Li and
Xiaoya Fan and
Shengbing Zhang and
Zhao Yang and
Miao Wang and
Danghui Wang and
Meng Zhang},
title = {{DCNN} search and accelerator co-design: Improve the adaptability
between {NAS} frameworks and embedded platforms},
journal = {Integr.},
volume = {87},
pages = {147--157},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.003},
doi = {10.1016/J.VLSI.2022.07.003},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiFZYWWZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiLT22,
author = {Mingtai Li and
Tuanjie Li and
Yaqiong Tang},
title = {Improved thermal network modeling of die stacking {DRAM} and optimization},
journal = {Integr.},
volume = {85},
pages = {35--41},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.03.001},
doi = {10.1016/J.VLSI.2022.03.001},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiLT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiQTHY22,
author = {Benzheng Li and
Zhongdong Qi and
Zhengguang Tang and
Xiyi He and
Hailong You},
title = {High quality hypergraph partitioning for logic emulation},
journal = {Integr.},
volume = {83},
pages = {67--76},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.11.005},
doi = {10.1016/J.VLSI.2021.11.005},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiQTHY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiS22,
author = {Bo Li and
Guoyong Shi},
title = {A {CMOS} rectified linear unit operating in weak inversion for memristive
neuromorphic circuits},
journal = {Integr.},
volume = {87},
pages = {24--28},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.05.007},
doi = {10.1016/J.VLSI.2022.05.007},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiZLGWLTQ22,
author = {Yanze Li and
Yufan Zhang and
Jiafeng Liu and
Jun Gong and
Jian Wang and
Jinmei Lai and
Xinxuan Tao and
Gang Qu},
title = {AutoTEA: An Automated Transistor-level Efficient and Accurate design
tool for {FPGA} design},
journal = {Integr.},
volume = {87},
pages = {231--240},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.010},
doi = {10.1016/J.VLSI.2022.06.010},
timestamp = {Fri, 20 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiZLGWLTQ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuHCLLHG22,
author = {Genggeng Liu and
Hongbin Huang and
Zhisheng Chen and
Hongxing Lin and
Hui Liu and
Xing Huang and
Wenzhong Guo},
title = {Design automation for continuous-flow microfluidic biochips: {A} comprehensive
review},
journal = {Integr.},
volume = {82},
pages = {48--66},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.09.002},
doi = {10.1016/J.VLSI.2021.09.002},
timestamp = {Sat, 25 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiuHCLLHG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuLLJ22,
author = {Wenhao Liu and
Huakui Lei and
Hongfei Liu and
Peng Jiang},
title = {Design of an ultra-wideband {LNA} using transformer matching method},
journal = {Integr.},
volume = {87},
pages = {122--136},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.012},
doi = {10.1016/J.VLSI.2022.06.012},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiuLLJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuWLXZZ22,
author = {Bo Liu and
Pengfei Wang and
Kai Li and
Binrui Xu and
Jincan Zhang and
Liwen Zhang},
title = {A precision programmable multilevel voltage output and low-temperature-variation
{CMOS} bandgap reference with area-efficient transistor-array layout},
journal = {Integr.},
volume = {87},
pages = {74--81},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.003},
doi = {10.1016/J.VLSI.2022.06.003},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiuWLXZZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LuoLCZS22,
author = {Dan Luo and
Tun Li and
Liqian Chen and
Hongji Zou and
Mingchuan Shi},
title = {Grammar-based fuzz testing for microprocessor {RTL} design},
journal = {Integr.},
volume = {86},
pages = {64--73},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.05.001},
doi = {10.1016/J.VLSI.2022.05.001},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LuoLCZS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/M22,
author = {M. Mohamed Asan Basiri},
title = {Efficient {VLSI} architecture of 3D discrete transformation},
journal = {Integr.},
volume = {82},
pages = {136--146},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.10.001},
doi = {10.1016/J.VLSI.2021.10.001},
timestamp = {Sat, 25 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/M22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MachaIRR22,
author = {Naveen Kumar Macha and
Md Arif Iqbal and
Bhavana Tejaswini Repalle and
Mostafizur Rahman},
title = {On circuit developments to enable large scale circuit design while
computing with noise},
journal = {Integr.},
volume = {84},
pages = {62--71},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.01.002},
doi = {10.1016/J.VLSI.2022.01.002},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MachaIRR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MahendraKG22,
author = {Mihika Mahendra and
Shweta Kumari and
Maneesha Gupta},
title = {Low voltage fully differential {OTA} using {DTMOS} based self cascode
transistor with slew-rate enhancement and its filter application},
journal = {Integr.},
volume = {84},
pages = {47--61},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.01.003},
doi = {10.1016/J.VLSI.2022.01.003},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MahendraKG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaryanAV22,
author = {Mohammad Moradinezhad Maryan and
Seyed Javad Azhari and
Majid Amini Valashani},
title = {A self-control leakage-suppression block for low-power high-efficient
static logic circuit design in 22 nm {CMOS} process},
journal = {Integr.},
volume = {87},
pages = {1--10},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.05.006},
doi = {10.1016/J.VLSI.2022.05.006},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MaryanAV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MirandaCGLL22,
author = {Jose Angel Miranda and
Manuel Felipe Canabal and
Laura Guti{\'{e}}rrez{-}Mart{\'{\i}}n and
Jos{\'{e}} Manuel Lanza{-}Guti{\'{e}}rrez and
Celia L{\'{o}}pez{-}Ongil},
title = {Edge computing design space exploration for heart rate monitoring},
journal = {Integr.},
volume = {84},
pages = {171--179},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.003},
doi = {10.1016/J.VLSI.2022.02.003},
timestamp = {Wed, 27 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MirandaCGLL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MohanA22,
author = {Navya Mohan and
J. P. Anita},
title = {Test and diagnosis pattern generation for distinguishing stuck-at
faults and bridging faults},
journal = {Integr.},
volume = {83},
pages = {24--32},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.12.002},
doi = {10.1016/J.VLSI.2021.12.002},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MohanA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MorsaliS22,
author = {M. Mehrdad Morsali and
Majid Shalchian},
title = {Switched pseudo-current mirror inverter for low-power, thermally stable
and robust ring oscillator},
journal = {Integr.},
volume = {82},
pages = {20--28},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.08.012},
doi = {10.1016/J.VLSI.2021.08.012},
timestamp = {Sat, 25 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MorsaliS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NaseerNSYMAM22,
author = {Raja Arslan Naseer and
Muneeba Nasim and
Muhummad Sohaib and
Ch. Jabbar Younis and
Anzar Mehmood and
Mehboob Alam and
Yehia Massoud},
title = {{VLSI} architecture design and implementation of 5/3 and 9/7 lifting
Discrete Wavelet Transform},
journal = {Integr.},
volume = {87},
pages = {253--259},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.009},
doi = {10.1016/J.VLSI.2022.07.009},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/NaseerNSYMAM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NedalgiS22,
author = {Dharmaray Nedalgi and
Saroja V. Siddamal},
title = {Differential receiver with 2 {\texttimes} {VDD} input signals using
1 {\texttimes} {VDD} devices},
journal = {Integr.},
volume = {87},
pages = {306--312},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.08.003},
doi = {10.1016/J.VLSI.2022.08.003},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/NedalgiS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OduguNP22,
author = {Venkata Krishna Odugu and
C. Venkata Narasimhulu and
K. Satya Prasad},
title = {A novel filter-bank architecture of 2D-FIR symmetry filters using
{LUT} based multipliers},
journal = {Integr.},
volume = {84},
pages = {12--25},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.01.004},
doi = {10.1016/J.VLSI.2022.01.004},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/OduguNP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ParaiSGR22,
author = {Manas Parai and
Supriyo Srimani and
Kasturi Ghosh and
Hafizur Rahaman},
title = {Multi-source data fusion technique for parametric fault diagnosis
in analog circuits},
journal = {Integr.},
volume = {84},
pages = {92--101},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.01.005},
doi = {10.1016/J.VLSI.2022.01.005},
timestamp = {Wed, 23 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ParaiSGR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ParkK22,
author = {Heechun Park and
Taewhan Kim},
title = {Speeding-up neuromorphic computation for neural networks: Structure
optimization approach},
journal = {Integr.},
volume = {82},
pages = {104--114},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.09.001},
doi = {10.1016/J.VLSI.2021.09.001},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ParkK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Rashidi22,
author = {Bahram Rashidi},
title = {Glitch-less hardware implementation of block ciphers based on an efficient
glitch filter},
journal = {Integr.},
volume = {85},
pages = {20--26},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.007},
doi = {10.1016/J.VLSI.2022.02.007},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Rashidi22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RazzaqSY22,
author = {Anas Razzaq and
Sajjad Rostami Sani and
Andy Gean Ye},
title = {The effect of gate voltage boosting on the power efficiency of multi-context
FPGAs},
journal = {Integr.},
volume = {86},
pages = {30--43},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.04.007},
doi = {10.1016/J.VLSI.2022.04.007},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RazzaqSY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RenW22,
author = {Jijun Ren and
Xing Wang},
title = {Research on digital predistortion technique of harmonic cancellation
based on volterra series},
journal = {Integr.},
volume = {87},
pages = {332--335},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.007},
doi = {10.1016/J.VLSI.2022.07.007},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RenW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Santana-AndreoS22,
author = {Andr{\'{e}}s Santana{-}Andreo and
Pablo Saraza{-}Canflanca and
H{\'{e}}ctor Carrasco{-}Lopez and
Piedad Brox and
Rafael Castro{-}L{\'{o}}pez and
Elisenda Roca and
Francisco V. Fern{\'{a}}ndez},
title = {A DRV-based bit selection method for {SRAM} {PUF} key generation and
its impact on ECCs},
journal = {Integr.},
volume = {85},
pages = {1--9},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.008},
doi = {10.1016/J.VLSI.2022.02.008},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Santana-AndreoS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SarmaCBR22,
author = {Jitumani Sarma and
Shatadal Chatterjee and
Rakesh Biswas and
Sounak Roy},
title = {A digitally controlled adaptive {LDO} for power management unit in
sensor node},
journal = {Integr.},
volume = {87},
pages = {29--39},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.004},
doi = {10.1016/J.VLSI.2022.06.004},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SarmaCBR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShaikSPG22,
author = {Jani Babu Shaik and
Sonal Singhal and
Siona Menezes Picardo and
Nilesh Goel},
title = {Impact of various {NBTI} distributions on {SRAM} performance for FinFET
technology},
journal = {Integr.},
volume = {83},
pages = {60--66},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.12.005},
doi = {10.1016/J.VLSI.2021.12.005},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShaikSPG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShanthiRR22,
author = {J. Shanthi and
D. Gracia Nirmala Rani and
S. Rajaram},
title = {An Enhanced Memetic Algorithm using {SKB} tree representation for
fixed-outline and temperature driven non-slicing floorplanning},
journal = {Integr.},
volume = {86},
pages = {84--97},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.04.001},
doi = {10.1016/J.VLSI.2022.04.001},
timestamp = {Thu, 28 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ShanthiRR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShekharK22,
author = {Raghav Shekhar and
Chaudhry Indra Kumar},
title = {Design of highly reliable radiation hardened 10T {SRAM} cell for low
voltage applications},
journal = {Integr.},
volume = {87},
pages = {176--181},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.004},
doi = {10.1016/J.VLSI.2022.07.004},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ShekharK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SilvaOZMR22,
author = {F{\'{a}}bio G. R. G. da Silva and
Rafael N. M. Oliveira and
Alexandra L. Zimpeck and
Cristina Meinhardt and
Ricardo Reis},
title = {Exploring XOR-based Full Adders and decoupling cells to variability
mitigation at FinFET technology},
journal = {Integr.},
volume = {87},
pages = {137--146},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.008},
doi = {10.1016/J.VLSI.2022.06.008},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SilvaOZMR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SiroisAM22,
author = {Samuel Sirois and
Messaoud Ahmed Ouameur and
Daniel Massicotte},
title = {High level synthesis strategies for ultra fast and low latency matrix
inversion implementation for massive {MIMO} processing},
journal = {Integr.},
volume = {82},
pages = {29--36},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.08.011},
doi = {10.1016/J.VLSI.2021.08.011},
timestamp = {Thu, 07 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SiroisAM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SongHY22,
author = {Tai Song and
Zhengfeng Huang and
Aibin Yan},
title = {Machine learning classification algorithm for {VLSI} test cost reduction},
journal = {Integr.},
volume = {87},
pages = {40--48},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.005},
doi = {10.1016/J.VLSI.2022.06.005},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SongHY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SongNHW22,
author = {Tai Song and
Tianming Ni and
Zhengfeng Huang and
Jinlei Wan},
title = {Valid test pattern identification for {VLSI} adaptive test},
journal = {Integr.},
volume = {82},
pages = {1--6},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.08.009},
doi = {10.1016/J.VLSI.2021.08.009},
timestamp = {Sat, 25 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SongNHW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SotiriadisT22,
author = {Paul P. Sotiriadis and
Nikos Temenos},
title = {Compact {MAX} and {MIN} Stochastic Computing architectures},
journal = {Integr.},
volume = {87},
pages = {194--204},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.006},
doi = {10.1016/J.VLSI.2022.06.006},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SotiriadisT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SuanesDTS22,
author = {Alejandro Suanes and
Michele Dei and
Llu{\'{\i}}s Ter{\'{e}}s and
Francisco Serra{-}Graells},
title = {A 85dB-SNDR 50 kHz bootstrapping-free resistor-less {SC} Delta-Sigma
modulator {IP} block for PVT-robust low-power ADCs},
journal = {Integr.},
volume = {84},
pages = {159--170},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.002},
doi = {10.1016/J.VLSI.2022.02.002},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SuanesDTS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SukumaranP22,
author = {Pournamy Sukumaran and
Maran Ponnambalam},
title = {A two stage cascode {LNA} using modified derivative superposition
technique in 0.13{\(\mu\)}m {HBT} with an {IIP3} of 2 dBm and {NF}
of 4.8 dB for {IEEE} 802.11ad standard},
journal = {Integr.},
volume = {87},
pages = {211--220},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.010},
doi = {10.1016/J.VLSI.2022.07.010},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SukumaranP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SureshM22,
author = {Lakshmi Nediyara Suresh and
Bhaskar Manickam},
title = {Design and application of {CMOS} active inductor in bandpass filter
and {VCO} for reconfigurable {RF} front-end},
journal = {Integr.},
volume = {82},
pages = {115--126},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.09.003},
doi = {10.1016/J.VLSI.2021.09.003},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SureshM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SwainS22,
author = {Monalisa Swain and
Debabala Swain},
title = {An effective watermarking technique using {BTC} and {SVD} for image
authentication and quality recovery},
journal = {Integr.},
volume = {83},
pages = {12--23},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.11.004},
doi = {10.1016/J.VLSI.2021.11.004},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SwainS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TianLJLLY22,
author = {Chen Tian and
Jianyong Lu and
Liu Jun and
Huaguo Liang and
Yingchun Lu and
Maoxiang Yi},
title = {A reconfigurable test method based on {LFSR} for 3D stacking integrated
circuits},
journal = {Integr.},
volume = {87},
pages = {82--89},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.011},
doi = {10.1016/J.VLSI.2022.06.011},
timestamp = {Thu, 13 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TianLJLLY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TombakGAD22,
author = {G{\"{u}}ney Isik Tombak and
Seyda Nur G{\"{u}}zelhan and
Engin Afacan and
G{\"{u}}nhan D{\"{u}}ndar},
title = {Simulated annealing assisted NSGA-III-based multi-objective analog
{IC} sizing tool},
journal = {Integr.},
volume = {85},
pages = {48--56},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.009},
doi = {10.1016/J.VLSI.2022.02.009},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TombakGAD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TranTH22,
author = {Van{-}Toan Tran and
Quang{-}Kien Trinh and
Van{-}Phuc Hoang},
title = {A robust Euclidean metric based {ID} extraction method using RO-PUFs
in {FPGA}},
journal = {Integr.},
volume = {82},
pages = {37--47},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.08.010},
doi = {10.1016/J.VLSI.2021.08.010},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TranTH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TsaiL22,
author = {Tsung{-}Han Tsai and
Hsing{-}Chuang Liu},
title = {Design and implementation of filterbank for {MPEG-2/4} {AAC} system},
journal = {Integr.},
volume = {82},
pages = {155--162},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.10.003},
doi = {10.1016/J.VLSI.2021.10.003},
timestamp = {Sat, 25 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TsaiL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TsaiLC22,
author = {Tsung{-}Han Tsai and
Pei{-}Yun Liu and
Yu{-}He Chiou},
title = {Hardware design for blind source separation using fast time-frequency
mask technique},
journal = {Integr.},
volume = {82},
pages = {67--77},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.07.001},
doi = {10.1016/J.VLSI.2021.07.001},
timestamp = {Sat, 25 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TsaiLC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ValuskarSR22,
author = {Ashish Valuskar and
Madhu Shandilya and
Arvind Rajawat},
title = {Statistical traffic pattern for mixed torus topology and pathfinder
based traffic and thermal aware routing protocol on NoC},
journal = {Integr.},
volume = {87},
pages = {158--168},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.009},
doi = {10.1016/J.VLSI.2022.06.009},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ValuskarSR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VidyaS22,
author = {P. Meenakshi Vidya and
S. Sudha},
title = {A fully integrated {VLSI} architecture using chaotic {PWM} for {RF}
transmitter design with electromagnetic interference reduction},
journal = {Integr.},
volume = {83},
pages = {33--45},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.12.003},
doi = {10.1016/J.VLSI.2021.12.003},
timestamp = {Tue, 22 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/VidyaS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangMZYX22,
author = {Bo Wang and
Sheng Ma and
Guoyi Zhu and
Xiao Yi and
Rui Xu},
title = {A novel systolic array processor with dynamic dataflows},
journal = {Integr.},
volume = {85},
pages = {42--47},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.03.002},
doi = {10.1016/J.VLSI.2022.03.002},
timestamp = {Mon, 13 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangMZYX22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangTWLT22,
author = {Yaru Wang and
Ming Tang and
Pengbo Wang and
Botao Liu and
Rui Tian},
title = {The Levene test based-leakage assessment},
journal = {Integr.},
volume = {87},
pages = {182--193},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.013},
doi = {10.1016/J.VLSI.2022.06.013},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangTWLT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangWL22,
author = {Bo Wang and
Haoying Wu and
Mingyu Liu},
title = {Resource allocation applied to flexible printed circuit routing based
on constrained Delaunay triangulation},
journal = {Integr.},
volume = {87},
pages = {16--23},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.05.008},
doi = {10.1016/J.VLSI.2022.05.008},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WeiZZW22,
author = {JiaHao Wei and
Tian Zhao and
Zheng Zhang and
Jing Wan},
title = {Modeling of {CMOS} transistors from 0.18 {\(\mu\)}m process by artificial
neural network},
journal = {Integr.},
volume = {87},
pages = {11--15},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.06.001},
doi = {10.1016/J.VLSI.2022.06.001},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WeiZZW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Xie22,
author = {Shuang Xie},
title = {{BJT} induced dark current in {CMOS} image sensors},
journal = {Integr.},
volume = {87},
pages = {260--263},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.013},
doi = {10.1016/J.VLSI.2022.07.013},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Xie22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuYS22,
author = {Rongjin Xu and
Dawei Ye and
Chuanjin Richard Shi},
title = {A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a
self-alignment frequency-tracking loop for reference spur reduction},
journal = {Integr.},
volume = {84},
pages = {1--11},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.12.007},
doi = {10.1016/J.VLSI.2021.12.007},
timestamp = {Fri, 12 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/XuYS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuZ22,
author = {Longhao Xu and
Jie Zhang},
title = {A Novel four - Wing chaotic system with multiple attractors based
on hyperbolic sine: Application to image encryption*},
journal = {Integr.},
volume = {87},
pages = {313--331},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.012},
doi = {10.1016/J.VLSI.2022.07.012},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/XuZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YanQSHNCW22,
author = {Aibin Yan and
Kuikui Qian and
Tai Song and
Zhengfeng Huang and
Tianming Ni and
Yu Chen and
Xiaoqing Wen},
title = {A double-node-upset completely tolerant {CMOS} latch design with extremely
low cost for high-performance applications},
journal = {Integr.},
volume = {86},
pages = {22--29},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.04.008},
doi = {10.1016/J.VLSI.2022.04.008},
timestamp = {Thu, 28 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YanQSHNCW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YanRSSS22,
author = {Shaohui Yan and
Yu Ren and
Zhenlong Song and
Wanlin Shi and
Xi Sun},
title = {A memristive chaotic system with rich dynamical behavior and circuit
implementation},
journal = {Integr.},
volume = {85},
pages = {63--75},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.03.003},
doi = {10.1016/J.VLSI.2022.03.003},
timestamp = {Wed, 01 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YanRSSS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangLGH22,
author = {Jinling Yang and
Lang Li and
Ying Guo and
Xiantong Huang},
title = {{DULBC:} {A} dynamic ultra-lightweight block cipher with high-throughput},
journal = {Integr.},
volume = {87},
pages = {221--230},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.011},
doi = {10.1016/J.VLSI.2022.07.011},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YangLGH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangYDZW22,
author = {Dingcheng Yang and
Wenjian Yu and
Xiangyun Ding and
Ao Zhou and
Xiaoyi Wang},
title = {DP-Nets: Dynamic programming assisted quantization schemes for {DNN}
compression and acceleration},
journal = {Integr.},
volume = {82},
pages = {147--154},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.10.002},
doi = {10.1016/J.VLSI.2021.10.002},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YangYDZW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Yu22,
author = {Weize Yu},
title = {Convex optimization of random dynamic voltage and frequency scaling
against power attacks},
journal = {Integr.},
volume = {82},
pages = {7--13},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.08.013},
doi = {10.1016/J.VLSI.2021.08.013},
timestamp = {Sat, 25 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Yu22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhanC22,
author = {Suoyue Zhan and
Chunhong Chen},
title = {A hybrid method for signal probability and reliability estimation
with combinational circuits},
journal = {Integr.},
volume = {87},
pages = {275--283},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.006},
doi = {10.1016/J.VLSI.2022.07.006},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhanC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangXLLC22,
author = {Zhang Zhang and
Ao Xu and
Chao Li and
Gang Liu and
Xin Cheng},
title = {Mathematical analysis and circuit emulator design of the three-valued
memristor},
journal = {Integr.},
volume = {86},
pages = {74--83},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.05.005},
doi = {10.1016/J.VLSI.2022.05.005},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhangXLLC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangZDL22,
author = {Zewei Zhang and
Xiao Zhao and
Liyuan Dong and
Shuoyang Li},
title = {A high-efficiency feedforward compensation method for capacitor-less
{LDO}},
journal = {Integr.},
volume = {87},
pages = {104--110},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.002},
doi = {10.1016/J.VLSI.2022.07.002},
timestamp = {Wed, 05 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhangZDL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangZLL22,
author = {Qing Zhang and
Yuhang Zhang and
Jizuo Li and
Yongfu Li},
title = {{WDP-BNN:} Efficient wafer defect pattern classification via binarized
neural network},
journal = {Integr.},
volume = {85},
pages = {76--86},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.04.003},
doi = {10.1016/J.VLSI.2022.04.003},
timestamp = {Wed, 31 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangZLL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangZLLL22,
author = {Qing Zhang and
Yuhang Zhang and
Jizuo Li and
Wei Lu and
Yongfu Li},
title = {Litho-NeuralODE 2.0: Improving hotspot detection accuracy with advanced
data augmentation, DCT-based features, and neural ordinary differential
equations},
journal = {Integr.},
volume = {85},
pages = {10--19},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.02.010},
doi = {10.1016/J.VLSI.2022.02.010},
timestamp = {Wed, 31 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangZLLL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhaoCLWL22,
author = {Yi Zhao and
Hui Chen and
Peng Liu and
Jigang Wu and
Dongxiang Luo},
title = {An improved reconfigurable logic in resistive random access memory},
journal = {Integr.},
volume = {87},
pages = {169--175},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.07.005},
doi = {10.1016/J.VLSI.2022.07.005},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhaoCLWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZiaSM22,
author = {Ehsan Zia and
Alireza Shamsi and
Jalil Mazloum},
title = {New approach for digital calibration of pipelined analog to digital
converters based on secant method},
journal = {Integr.},
volume = {82},
pages = {89--95},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.09.007},
doi = {10.1016/J.VLSI.2021.09.007},
timestamp = {Sat, 25 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZiaSM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AalamMH21,
author = {Umar Aalam and
Bodhisatwa Mazumdar and
Neminath Hubballi},
title = {mMIG: Inversion optimization in majority inverter graph with minority
operations},
journal = {Integr.},
volume = {81},
pages = {195--210},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.005},
doi = {10.1016/J.VLSI.2021.05.005},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AalamMH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AbelNG21,
author = {Inga Abel and
Maximilian Neuner and
Helmut Graeb},
title = {{COPRICSI:} COnstraint-PRogrammed Initial Circuit SIzing},
journal = {Integr.},
volume = {76},
pages = {148--158},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.10.002},
doi = {10.1016/J.VLSI.2020.10.002},
timestamp = {Fri, 08 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AbelNG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AfacanLMD21,
author = {Engin Afacan and
Nuno Louren{\c{c}}o and
Ricardo Martins and
G{\"{u}}nhan D{\"{u}}ndar},
title = {Review: Machine learning techniques in analog/RF integrated circuit
design, synthesis, layout, and test},
journal = {Integr.},
volume = {77},
pages = {113--130},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.006},
doi = {10.1016/J.VLSI.2020.11.006},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AfacanLMD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Aggarwal21,
author = {Supriya Aggarwal},
title = {Efficient design of decimation filter using linear programming and
its {FPGA} implementation},
journal = {Integr.},
volume = {79},
pages = {94--106},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.03.008},
doi = {10.1016/J.VLSI.2021.03.008},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Aggarwal21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AgrawalM21,
author = {Deepak Agrawal and
Sudhanshu Maheshwari},
title = {Design and implementation of current mode circuit for digital modulation},
journal = {Integr.},
volume = {78},
pages = {118--123},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.02.002},
doi = {10.1016/J.VLSI.2021.02.002},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AgrawalM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AkgulGPYKG21,
author = {Akif Akgul and
Bilal Gurevin and
Ihsan Pehlivan and
Muhammed Yildiz and
Mustafa {\c{C}}agri Kutlu and
Emre G{\"{u}}lery{\"{u}}z},
title = {Development of micro computer based mobile random number generator
with an encryption application},
journal = {Integr.},
volume = {81},
pages = {1--16},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.010},
doi = {10.1016/J.VLSI.2021.04.010},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AkgulGPYKG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AnandakumarHT21,
author = {N. Nalla Anandakumar and
Mohammad S. Hashmi and
Mark M. Tehranipoor},
title = {FPGA-based Physical Unclonable Functions: {A} comprehensive overview
of theory and architectures},
journal = {Integr.},
volume = {81},
pages = {175--194},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.06.001},
doi = {10.1016/J.VLSI.2021.06.001},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AnandakumarHT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AryaSPS21,
author = {Neelam Arya and
Teena Soni and
Manisha Pattanaik and
G. K. Sharma},
title = {{READ:} {A} fixed restoring array based accuracy-configurable approximate
divider for energy efficiency},
journal = {Integr.},
volume = {76},
pages = {1--12},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.08.002},
doi = {10.1016/J.VLSI.2020.08.002},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AryaSPS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Attarzadeh-Niaki21,
author = {Seyed{-}Hosein Attarzadeh{-}Niaki and
Ingo Sander and
Mohammad Ahmadi},
title = {An automated parallel simulation flow for cyber-physical system design},
journal = {Integr.},
volume = {77},
pages = {48--58},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.010},
doi = {10.1016/J.VLSI.2020.11.010},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Attarzadeh-Niaki21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BabuK21,
author = {M. Babu and
G. A. Sathish Kumar},
title = {Design of novel {SMS4-BSK} encryption transmission system},
journal = {Integr.},
volume = {78},
pages = {60--69},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.01.003},
doi = {10.1016/J.VLSI.2021.01.003},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BabuK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BanerjeeMDB21,
author = {Sabyasachee Banerjee and
Subhashis Majumder and
Debesh K. Das and
Bhargab B. Bhattacharya},
title = {Fast algorithms for test optimization of core based 3D SoC},
journal = {Integr.},
volume = {77},
pages = {70--88},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.009},
doi = {10.1016/J.VLSI.2020.11.009},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BanerjeeMDB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BhattacharjeeBM21,
author = {Anirban Bhattacharjee and
Chandan Bandyopadhyay and
Angshu Mukherjee and
Robert Wille and
Rolf Drechsler and
Hafizur Rahaman},
title = {An ant colony based mapping of quantum circuits to nearest neighbor
architectures},
journal = {Integr.},
volume = {78},
pages = {11--24},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.12.002},
doi = {10.1016/J.VLSI.2020.12.002},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BhattacharjeeBM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BhattacharjeeBN21,
author = {Anirban Bhattacharjee and
Chandan Bandyopadhyay and
Philipp Niemann and
Bappaditya Mondal and
Rolf Drechsler and
Hafizur Rahaman},
title = {An improved heuristic technique for nearest neighbor realization of
quantum circuits in 2D architecture},
journal = {Integr.},
volume = {76},
pages = {40--54},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.09.003},
doi = {10.1016/J.VLSI.2020.09.003},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BhattacharjeeBN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BusnotSVM21,
author = {Gabriel Busnot and
Tanguy Sassolas and
Nicolas Ventroux and
Matthieu Moy},
title = {Standard-compliant parallel SystemC simulation of loosely-timed transaction
level models: From baremetal to Linux-based applications support},
journal = {Integr.},
volume = {79},
pages = {23--40},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.12.006},
doi = {10.1016/J.VLSI.2020.12.006},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BusnotSVM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChakrabortyGSDR21,
author = {Anindita Chakraborty and
Partha Sarathi Gupta and
Ritika Singh and
Rakesh Das and
Hafizur Rahaman},
title = {BDD-based synthesis approach for in-memory logic realization utilizing
Memristor Aided loGIC {(MAGIC)}},
journal = {Integr.},
volume = {81},
pages = {254--267},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.08.002},
doi = {10.1016/J.VLSI.2021.08.002},
timestamp = {Wed, 13 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChakrabortyGSDR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChandraKR21,
author = {Abhijit Chandra and
Amit Kumar and
Subhabrata Roy},
title = {Design of {FIR} filter {ISOTA} with the aid of genetic algorithm},
journal = {Integr.},
volume = {79},
pages = {107--115},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.03.005},
doi = {10.1016/J.VLSI.2021.03.005},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChandraKR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChangelaZV21,
author = {Ankur Changela and
Mazad Zaveri and
Deepak Verma},
title = {Mixed-radix, virtually scaling-free {CORDIC} algorithm based rotator
for {DSP} applications},
journal = {Integr.},
volume = {78},
pages = {70--83},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.01.005},
doi = {10.1016/J.VLSI.2021.01.005},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChangelaZV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenLCL21,
author = {Yu{-}Guang Chen and
Ing{-}Chao Lin and
Kun{-}Wei Chiu and
Cheng{-}Hsuan Liu},
title = {An efficient \emph{NBTI}-aware wake-up strategy: Concept, design,
and manipulation},
journal = {Integr.},
volume = {80},
pages = {60--71},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.003},
doi = {10.1016/J.VLSI.2021.04.003},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChenLCL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenMCLJ21,
author = {Zhaohui Chen and
Yuan Ma and
Tianyu Chen and
Jingqiang Lin and
Jiwu Jing},
title = {High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber
on FPGAs},
journal = {Integr.},
volume = {78},
pages = {25--35},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.12.005},
doi = {10.1016/J.VLSI.2020.12.005},
timestamp = {Thu, 08 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChenMCLJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenWNJ21,
author = {Mingshu Chen and
Zhen Wang and
Fahimeh Nazarimehr and
Sajad Jafari},
title = {A novel memristive chaotic system without any equilibrium point},
journal = {Integr.},
volume = {79},
pages = {133--142},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.002},
doi = {10.1016/J.VLSI.2021.04.002},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChenWNJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChentoufSI21,
author = {Mohamed Chentouf and
Foffie Stevmelin and
Zine El Abidine Alaoui Ismaili},
title = {Power-aware hold optimization for {ASIC} physical synthesis},
journal = {Integr.},
volume = {76},
pages = {13--24},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.08.003},
doi = {10.1016/J.VLSI.2020.08.003},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChentoufSI21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DahirKPMY21,
author = {Nizar Dahir and
Ammar Karkar and
Maurizio Palesi and
Terrence S. T. Mak and
Alex Yakovlev},
title = {Power density aware application mapping in mesh-based network-on-chip
architecture: An evolutionary multi-objective approach},
journal = {Integr.},
volume = {81},
pages = {342--353},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.08.008},
doi = {10.1016/J.VLSI.2021.08.008},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DahirKPMY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DingQZZ21,
author = {Hao Ding and
Junyan Qian and
Lingzhong Zhao and
Zhongyi Zhai},
title = {A mathematical programming method for constructing the shortest interconnection
{VLSI} arrays},
journal = {Integr.},
volume = {81},
pages = {167--174},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.07.004},
doi = {10.1016/J.VLSI.2021.07.004},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DingQZZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/El-MalehT21,
author = {Aiman H. El{-}Maleh and
Ghashmi H. Bin Talib},
title = {Time redundancy and gate sizing soft error-tolerant based adder design},
journal = {Integr.},
volume = {78},
pages = {49--59},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.01.001},
doi = {10.1016/J.VLSI.2021.01.001},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/El-MalehT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FangLXYSJHL21,
author = {Bao Fang and
Huaguo Liang and
Dawen Xu and
Maoxiang Yi and
Yongxia Sheng and
Cuiyun Jiang and
Zhengfeng Huang and
Yingchun Lu},
title = {Approximate multipliers based on a novel unbiased approximate 4-2
compressor},
journal = {Integr.},
volume = {81},
pages = {17--24},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.003},
doi = {10.1016/J.VLSI.2021.05.003},
timestamp = {Wed, 13 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FangLXYSJHL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Garcia-HerreroS21,
author = {Francisco Garcia{-}Herrero and
Alfonso S{\'{a}}nchez{-}Maci{\'{a}}n and
Juan Antonio Maestro},
title = {Low delay non-binary error correction codes based on Orthogonal Latin
Squares},
journal = {Integr.},
volume = {76},
pages = {55--60},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.09.004},
doi = {10.1016/J.VLSI.2020.09.004},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Garcia-HerreroS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuangshanCJLL21,
author = {Niu Guangshan and
Liu Cong and
Zhang Jianwei and
Xuetao Li and
Xiangdong Luo},
title = {Research progress of time-interleaved analog-to-digital converters},
journal = {Integr.},
volume = {81},
pages = {313--321},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.08.007},
doi = {10.1016/J.VLSI.2021.08.007},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GuangshanCJLL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GunduK21,
author = {Anil Kumar Gundu and
Volkan Kursun},
title = {Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater},
journal = {Integr.},
volume = {78},
pages = {110--117},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.02.001},
doi = {10.1016/J.VLSI.2021.02.001},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GunduK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuoKWZCLX21,
author = {Shasha Guo and
Ziyang Kang and
Lei Wang and
Limeng Zhang and
Xiaofan Chen and
Shiming Li and
Weixia Xu},
title = {HashHeat: {A} hashing-based spatiotemporal filter for dynamic vision
sensor},
journal = {Integr.},
volume = {81},
pages = {99--107},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.006},
doi = {10.1016/J.VLSI.2021.04.006},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GuoKWZCLX21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuoWZ21,
author = {Qi Guo and
Ning Wang and
Guoshan Zhang},
title = {A novel current-controlled memristor-based chaotic circuit},
journal = {Integr.},
volume = {80},
pages = {20--28},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.008},
doi = {10.1016/J.VLSI.2021.05.008},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GuoWZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuptaC21,
author = {Mangal Deep Gupta and
Rajeev K. Chauhan},
title = {Secure image encryption scheme using 4D-Hyperchaotic systems based
reconfigurable pseudo-random number generator and S-Box},
journal = {Integr.},
volume = {81},
pages = {137--159},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.07.002},
doi = {10.1016/J.VLSI.2021.07.002},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GuptaC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HanK21,
author = {Changho Han and
Taewhan Kim},
title = {Synthesis of representative critical path circuits considering {BEOL}
variations for deep sub-micron circuits},
journal = {Integr.},
volume = {78},
pages = {1--10},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.12.003},
doi = {10.1016/J.VLSI.2020.12.003},
timestamp = {Thu, 08 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HanK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HanMXMLC21,
author = {Xintong Han and
Jun Mou and
Li Xiong and
Chenguang Ma and
Tianming Liu and
Yinghong Cao},
title = {Coexistence of infinite attractors in a fractional-order chaotic system
with two nonlinear functions and its {DSP} implementation},
journal = {Integr.},
volume = {81},
pages = {43--55},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.010},
doi = {10.1016/J.VLSI.2021.05.010},
timestamp = {Mon, 19 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HanMXMLC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HarrisonAT21,
author = {Jacob Harrison and
Navid Asadizanjani and
Mark M. Tehranipoor},
title = {On malicious implants in PCBs throughout the supply chain},
journal = {Integr.},
volume = {79},
pages = {12--22},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.03.002},
doi = {10.1016/J.VLSI.2021.03.002},
timestamp = {Tue, 30 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HarrisonAT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HerzelEF21,
author = {Frank Herzel and
Arzu Ergintav and
Gunter Fischer},
title = {A novel approach to fractional-N PLLs generating ultra-fast low-noise
chirps for {FMCW} radar},
journal = {Integr.},
volume = {76},
pages = {139--147},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.09.009},
doi = {10.1016/J.VLSI.2020.09.009},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HerzelEF21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HuangHLCL21,
author = {Shanze Huang and
Jin He and
Shuo Li and
Zhiyuan Cao and
Jiankang Li},
title = {A 20-Gb/s wideband {AGC} amplifier with 26-dB dynamic range in 0.18-{\(\mu\)}m
SiGe BiCMOS},
journal = {Integr.},
volume = {81},
pages = {160--166},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.06.003},
doi = {10.1016/J.VLSI.2021.06.003},
timestamp = {Wed, 13 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HuangHLCL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/IslamogluCGAD21,
author = {Gamze Islamoglu and
Tugberk Ogulcan {\c{C}}akici and
Seyda Nur G{\"{u}}zelhan and
Engin Afacan and
G{\"{u}}nhan D{\"{u}}ndar},
title = {Deep learning aided efficient yield analysis for multi-objective analog
integrated circuit synthesis},
journal = {Integr.},
volume = {81},
pages = {322--330},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.08.006},
doi = {10.1016/J.VLSI.2021.08.006},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/IslamogluCGAD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JindalP21,
author = {Caffey Jindal and
Rishikesh Pandey},
title = {A very low output resistance and wide-swing class-AB level-shifted
folded flipped voltage follower cell},
journal = {Integr.},
volume = {81},
pages = {84--98},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.001},
doi = {10.1016/J.VLSI.2021.05.001},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JindalP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KapouleaPEH21,
author = {Stavroula Kapoulea and
Costas Psychalinos and
Ahmed S. Elwakil and
S. Hassan HosseinNia},
title = {Realizations of fractional-order {PID} loop-shaping controller for
mechatronic applications},
journal = {Integr.},
volume = {80},
pages = {5--12},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.009},
doi = {10.1016/J.VLSI.2021.04.009},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KapouleaPEH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KarimianE21,
author = {Mohammad Karimian and
Emad Ebrahimi},
title = {A C-band low-power sub-1volt current-reused multiphase oscillator},
journal = {Integr.},
volume = {79},
pages = {116--123},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.004},
doi = {10.1016/J.VLSI.2021.04.004},
timestamp = {Wed, 09 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KarimianE21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KashiPRF21,
author = {Somayeh Kashi and
Ahmad Patooghy and
Dara Rahmati and
Mahdi Fazeli},
title = {An energy efficient synthesis flow for application specific SoC design},
journal = {Integr.},
volume = {81},
pages = {331--341},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.08.005},
doi = {10.1016/J.VLSI.2021.08.005},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KashiPRF21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KatkooriIK21,
author = {Srinivas Katkoori and
Sheikh Ariful Islam and
Sujana Kakarla},
title = {Partial evaluation based triple modular redundancy for single event
upset mitigation},
journal = {Integr.},
volume = {77},
pages = {167--179},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.002},
doi = {10.1016/J.VLSI.2020.11.002},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KatkooriIK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KazemiH21,
author = {Amir Hossein Kazemi and
Mohsen Hayati},
title = {Design and analysis of a flat gain and linear low noise amplifier
using modified current reused structure with feedforward structure},
journal = {Integr.},
volume = {81},
pages = {123--136},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.013},
doi = {10.1016/J.VLSI.2021.05.013},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KazemiH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhanAHQ21,
author = {Najeeb Alam Khan and
Saeed Akbar and
Tooba Hameed and
Muhammad Ali Qureshi},
title = {Stumped nature hyperjerk system with fractional order and exponential
nonlinearity: Analog simulation, bifurcation analysis and cryptographic
applications},
journal = {Integr.},
volume = {79},
pages = {73--93},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.03.006},
doi = {10.1016/J.VLSI.2021.03.006},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KhanAHQ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhanJHAHA21,
author = {Majid Khan and
Sajjad Shaukat Jamal and
Mohammad Mazyad Hazzazi and
Khawaja Muhammad Ali and
Iqtadar Hussain and
Muhammad Asif},
title = {An efficient image encryption scheme based on double affine substitution
box and chaotic system},
journal = {Integr.},
volume = {81},
pages = {108--122},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.007},
doi = {10.1016/J.VLSI.2021.05.007},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KhanJHAHA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhatabOVA21,
author = {Esraa Khatab and
Ahmed Onsy and
Martin R. Varley and
Ahmed Abouelfarag},
title = {Vulnerable objects detection for autonomous driving: {A} review},
journal = {Integr.},
volume = {78},
pages = {36--48},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.01.002},
doi = {10.1016/J.VLSI.2021.01.002},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KhatabOVA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KidavSPG21,
author = {Jayaraj U. Kidav and
N. M. Sivamangai and
Perumal M. Pillai and
Sreejeesh S. G.},
title = {A broadband {MVDR} beamforming core for ultrasound imaging},
journal = {Integr.},
volume = {81},
pages = {221--233},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.07.006},
doi = {10.1016/J.VLSI.2021.07.006},
timestamp = {Wed, 26 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KidavSPG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KonstantinouNLD21,
author = {Dimitris Konstantinou and
Chrysostomos Nicopoulos and
Junghee Lee and
Giorgos Dimitrakopoulos},
title = {Multicast-enabled network-on-chip routers leveraging partitioned allocation
and switching},
journal = {Integr.},
volume = {77},
pages = {104--112},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.10.008},
doi = {10.1016/J.VLSI.2020.10.008},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KonstantinouNLD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KunduGM0Y21,
author = {Debraj Kundu and
Jitendra Giri and
Sataru Maruyama and
Sudip Roy and
Shigeru Yamashita},
title = {Fluid-to-cell assignment and fluid loading on programmable microfluidic
devices for bioprotocol execution},
journal = {Integr.},
volume = {78},
pages = {95--109},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.12.004},
doi = {10.1016/J.VLSI.2020.12.004},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KunduGM0Y21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LeeKLGKC21,
author = {Young Seo Lee and
Kyung Min Kim and
Ji Heon Lee and
Young{-}Ho Gong and
Seon Wook Kim and
Sung Woo Chung},
title = {Monolithic 3D stacked multiply-accumulate units},
journal = {Integr.},
volume = {76},
pages = {183--189},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.10.006},
doi = {10.1016/J.VLSI.2020.10.006},
timestamp = {Fri, 08 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LeeKLGKC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiPHCWCH21,
author = {Shuo Li and
Junren Pan and
Jin He and
Zhiyuan Cao and
Hao Wang and
Sheng Chang and
Qijun Huang},
title = {A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links},
journal = {Integr.},
volume = {77},
pages = {131--138},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.008},
doi = {10.1016/J.VLSI.2020.11.008},
timestamp = {Thu, 28 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiPHCWCH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiRLXL21,
author = {Jie Li and
Pedro Reviriego and
Shanshan Liu and
Liyi Xiao and
Fabrizio Lombardi},
title = {Designs for efficient low power cardinality and similarity sketches
by Two-Step Hashing {(TSH)}},
journal = {Integr.},
volume = {81},
pages = {246--253},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.08.003},
doi = {10.1016/J.VLSI.2021.08.003},
timestamp = {Wed, 10 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiRLXL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiRNL21,
author = {Changzhi Li and
Karthikeyan Rajagopal and
Fahimeh Nazarimehr and
Yongjian Liu},
title = {A non-autonomous chaotic system with no equilibrium},
journal = {Integr.},
volume = {79},
pages = {143--156},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.001},
doi = {10.1016/J.VLSI.2021.04.001},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiRNL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MenonKC21,
author = {Radhika V. Menon and
Shantharam Kalipatnapu and
Indrajit Chakrabarti},
title = {High speed {VLSI} architecture for improved region based active contour
segmentation technique},
journal = {Integr.},
volume = {77},
pages = {25--37},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.004},
doi = {10.1016/J.VLSI.2020.11.004},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MenonKC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MohammadianTSH21,
author = {Hamed Mohammadian and
Mohammad Bagher Tavakoli and
Farbod Setoudeh and
Ashkan Horri},
title = {Introduction of a new technique for simultaneous reduction of the
delay and leakage current in digital circuits},
journal = {Integr.},
volume = {78},
pages = {84--94},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.01.004},
doi = {10.1016/J.VLSI.2021.01.004},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MohammadianTSH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Moulik21,
author = {Sanjay Moulik},
title = {{RESET:} {A} real-time scheduler for energy and temperature aware
heterogeneous multi-core systems},
journal = {Integr.},
volume = {77},
pages = {59--69},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.012},
doi = {10.1016/J.VLSI.2020.11.012},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Moulik21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MoustaphaHTE21,
author = {El Bakkali Moustapha and
Elftouh Hanae and
Naima Amar Touhami and
Taj{-}eddin Elhamadi},
title = {2.3-21 GHz broadband and high linearity distributed low noise amplifier},
journal = {Integr.},
volume = {76},
pages = {61--68},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.09.005},
doi = {10.1016/J.VLSI.2020.09.005},
timestamp = {Fri, 08 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MoustaphaHTE21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MunirKSAH21,
author = {Noor Munir and
Majid Khan and
Tariq Shah and
Ammar S. Alanazi and
Iqtadar Hussain},
title = {Cryptanalysis of nonlinear confusion component based encryption algorithm},
journal = {Integr.},
volume = {79},
pages = {41--47},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.03.004},
doi = {10.1016/J.VLSI.2021.03.004},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MunirKSAH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NaifarM21,
author = {Omar Naifar and
Abdellatif Ben Makhlouf},
title = {Synchronization of mutual coupled fractional order one-sided lipschitz
systems},
journal = {Integr.},
volume = {80},
pages = {41--45},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.008},
doi = {10.1016/J.VLSI.2021.04.008},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/NaifarM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NarayanasamyGM21,
author = {Poornima Narayanasamy and
Seetharaman Gopalakrishnan and
Santhi Muthurathinam},
title = {Custom NoC topology generation using Discrete Antlion Trapping Mechanism},
journal = {Integr.},
volume = {76},
pages = {76--86},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.09.001},
doi = {10.1016/J.VLSI.2020.09.001},
timestamp = {Fri, 08 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NarayanasamyGM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OhlingerMFS21,
author = {Daniel {\"{O}}hlinger and
J{\"{u}}rgen Maier and
Matthias F{\"{u}}gger and
Ulrich Schmid},
title = {The Involution Tool for Accurate Digital Timing and Power Analysis},
journal = {Integr.},
volume = {76},
pages = {87--98},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.09.007},
doi = {10.1016/J.VLSI.2020.09.007},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/OhlingerMFS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OuannasKOPGD21,
author = {Adel Ouannas and
Amina{-}Aicha Khennaoui and
Taki{-}Eddine Oussaeif and
Viet{-}Thanh Pham and
Giuseppe Grassi and
Zohir Dibi},
title = {Hyperchaotic fractional Grassi-Miller map and its hardware implementation},
journal = {Integr.},
volume = {80},
pages = {13--19},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.006},
doi = {10.1016/J.VLSI.2021.05.006},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/OuannasKOPGD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Pierre21,
author = {Laurence Pierre},
title = {Refinement rules for the automatic TLM-to-RTL conversion of temporal
assertions},
journal = {Integr.},
volume = {76},
pages = {190--204},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.06.003},
doi = {10.1016/J.VLSI.2020.06.003},
timestamp = {Fri, 08 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Pierre21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Pulido-LunaLCC21,
author = {Jesus R. Pulido{-}Luna and
Jorge{-}Antonio L{\'{o}}pez{-}Renter{\'{\i}}a and
Noh{\'{e}} R. C{\'{a}}zarez{-}Castro and
Eric Campos{-}Cant{\'{o}}n},
title = {A two-directional grid multiscroll hidden attractor based on piecewise
linear system and its application in pseudo-random bit generator},
journal = {Integr.},
volume = {81},
pages = {34--42},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.011},
doi = {10.1016/J.VLSI.2021.04.011},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Pulido-LunaLCC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/QiCCCW21,
author = {Fei Qi and
Yi Chai and
Liping Chen and
YangQuan Chen and
Ranchao Wu},
title = {Passivity-based non-fragile control of a class of uncertain fractional-order
nonlinear systems},
journal = {Integr.},
volume = {81},
pages = {25--33},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.009},
doi = {10.1016/J.VLSI.2021.05.009},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/QiCCCW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/QianMDZZZ21,
author = {Junyan Qian and
Fuhao Mo and
Hao Ding and
Zhide Zhou and
Lingzhong Zhao and
Zhongyi Zhai},
title = {An improved algorithm for accelerating reconfiguration of {VLSI} array},
journal = {Integr.},
volume = {79},
pages = {124--132},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.005},
doi = {10.1016/J.VLSI.2021.04.005},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/QianMDZZZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RajeshP21,
author = {Kolluri Rajesh and
Sumanta Pyne},
title = {Invasive weed optimization based scheduling for digital microfluidic
biochip operations},
journal = {Integr.},
volume = {76},
pages = {122--134},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.10.003},
doi = {10.1016/J.VLSI.2020.10.003},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RajeshP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Rashidi21,
author = {Bahram Rashidi},
title = {Compact and efficient structure of 8-bit S-box for lightweight cryptography},
journal = {Integr.},
volume = {76},
pages = {172--182},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.10.009},
doi = {10.1016/J.VLSI.2020.10.009},
timestamp = {Fri, 08 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Rashidi21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RazzaqSY21,
author = {Anas Razzaq and
Sajjad Rostami Sani and
Andy Gean Ye},
title = {Designing efficient {FPGA} tiles for power-constrained ultra-low-power
applications},
journal = {Integr.},
volume = {78},
pages = {124--134},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.02.004},
doi = {10.1016/J.VLSI.2021.02.004},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RazzaqSY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ReddyVKGD21,
author = {Karri Manikantta Reddy and
M. H. Vasantha and
Nithin Y. B. Kumar and
Ch. Keshava Gopal and
Devesh Dwivedi},
title = {Quantization aware approximate multiplier and hardware accelerator
for edge computing of deep learning applications},
journal = {Integr.},
volume = {81},
pages = {268--279},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.08.001},
doi = {10.1016/J.VLSI.2021.08.001},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ReddyVKGD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RemyaSD21,
author = {Jayachandran Remya and
P. C. Subramaniam and
K. J. Dhanaraj},
title = {A novel tunable gain {CMOS} buffer amplifier for large resistive loads},
journal = {Integr.},
volume = {77},
pages = {1--12},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.10.007},
doi = {10.1016/J.VLSI.2020.10.007},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RemyaSD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Rojas-PerezM21,
author = {Leticia Oyuki Rojas{-}Perez and
Jos{\'{e}} Mart{\'{\i}}nez{-}Carranza},
title = {On-board processing for autonomous drone racing: An overview},
journal = {Integr.},
volume = {80},
pages = {46--59},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.04.007},
doi = {10.1016/J.VLSI.2021.04.007},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Rojas-PerezM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RoyC21,
author = {Subhabrata Roy and
Abhijit Chandra},
title = {A Survey of {FIR} Filter Design Techniques: Low-complexity, Narrow
Transition-band and Variable Bandwidth},
journal = {Integr.},
volume = {77},
pages = {193--204},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.12.001},
doi = {10.1016/J.VLSI.2020.12.001},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RoyC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RoyP21,
author = {Suvajit Roy and
Radha Raman Pal},
title = {Electronically tunable third-order dual-mode quadrature sinusoidal
oscillators employing VDCCs and all grounded components},
journal = {Integr.},
volume = {76},
pages = {99--112},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.09.006},
doi = {10.1016/J.VLSI.2020.09.006},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RoyP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RudposhtiV21,
author = {Maytham Allahi Rudposhti and
Mojtaba Valinataj},
title = {High-speed and low-cost carry select adders utilizing new optimized
add-one circuit and multiplexer-based logic},
journal = {Integr.},
volume = {79},
pages = {61--72},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.03.007},
doi = {10.1016/J.VLSI.2021.03.007},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RudposhtiV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SGL21,
author = {Bibin Sam Paul S and
Antony Xavier Glittas and
Gopalakrishnan Lakshminarayanan},
title = {A low latency modular-level deeply integrated {MFCC} feature extraction
architecture for speech recognition},
journal = {Integr.},
volume = {76},
pages = {69--75},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.09.002},
doi = {10.1016/J.VLSI.2020.09.002},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SGL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SadiM21,
author = {Mohamad Hasani Sadi and
Ali Mahani},
title = {Accelerating Deep Convolutional Neural Network base on stochastic
computing},
journal = {Integr.},
volume = {76},
pages = {113--121},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.09.008},
doi = {10.1016/J.VLSI.2020.09.008},
timestamp = {Fri, 15 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SadiM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SaidiODS21,
author = {Afef Saidi and
Slim Ben Othman and
Meriam Dhouibi and
Slim Ben Saoud},
title = {FPGA-based implementation of classification techniques: {A} survey},
journal = {Integr.},
volume = {81},
pages = {280--299},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.08.004},
doi = {10.1016/J.VLSI.2021.08.004},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SaidiODS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SanatiKSM21,
author = {Roohollah Sanati and
Farzan Khatib and
Mohammad Javadian Sarraf and
Reihaneh Kardehi Moghaddam},
title = {Low power time-domain rail-to-rail comparator with a new delay element
for {ADC} applications},
journal = {Integr.},
volume = {77},
pages = {89--95},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.007},
doi = {10.1016/J.VLSI.2020.11.007},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SanatiKSM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SharmaBK21,
author = {Gaurav Sharma and
Lava Bhargava and
Vinod Kumar},
title = {Real-time automated register abstraction active power-aware electronic
system level verification framework},
journal = {Integr.},
volume = {77},
pages = {151--166},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.013},
doi = {10.1016/J.VLSI.2020.11.013},
timestamp = {Tue, 10 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SharmaBK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SharmaPPMS21,
author = {Kulbhushan Sharma and
Anisha Pathania and
Rahul Pandey and
Jaya Madan and
Rajnish Sharma},
title = {{MOS} based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance
for biomedical applications: Analysis and proof of concept},
journal = {Integr.},
volume = {76},
pages = {25--39},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.08.001},
doi = {10.1016/J.VLSI.2020.08.001},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SharmaPPMS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SharmaRSP21,
author = {Richa Sharma and
Vijaypal Singh Rathor and
G. K. Sharma and
Manisha Pattanaik},
title = {A new hardware Trojan detection technique using deep convolutional
neural network},
journal = {Integr.},
volume = {79},
pages = {1--11},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.03.001},
doi = {10.1016/J.VLSI.2021.03.001},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SharmaRSP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Shi21,
author = {Guoyong Shi},
title = {Sizing of multi-stage Op Amps by combining design equations with the
gm/ID method},
journal = {Integr.},
volume = {79},
pages = {48--60},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.03.003},
doi = {10.1016/J.VLSI.2021.03.003},
timestamp = {Wed, 09 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Shi21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SinghCD21,
author = {Ashish Singh and
Rajeevan Chandel and
Rohit Dhiman},
title = {Proposal and analysis of relative stability in mixed {CNT} bundle
for sub-threshold interconnects},
journal = {Integr.},
volume = {80},
pages = {29--40},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.004},
doi = {10.1016/J.VLSI.2021.05.004},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SinghCD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TarafdarMBB21,
author = {Anirban Tarafdar and
Abir J. Mondal and
Uttam Kumar Bera and
Bidyut K. Bhattacharyya},
title = {A {PVT} aware differential delay circuit and its performance variation
due to power supply noise},
journal = {Integr.},
volume = {76},
pages = {159--171},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.10.004},
doi = {10.1016/J.VLSI.2020.10.004},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TarafdarMBB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TorresF21,
author = {Jorge Alves Torres and
Jo{\~{a}}o Costa Freire},
title = {30 GHz SiGe active inductor with voltage controlled {Q}},
journal = {Integr.},
volume = {77},
pages = {13--24},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.003},
doi = {10.1016/J.VLSI.2020.11.003},
timestamp = {Thu, 28 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TorresF21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ValinatajA21,
author = {Mojtaba Valinataj and
Zahra Yazdanian Amiri},
title = {Comments on "Improved designs of digit-by-digit decimal multiplier"},
journal = {Integr.},
volume = {76},
pages = {135--138},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.10.005},
doi = {10.1016/J.VLSI.2020.10.005},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ValinatajA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VuNN21,
author = {Hoang Gia Vu and
Takashi Nakada and
Yasuhiko Nakashima},
title = {Efficient hardware task migration for heterogeneous {FPGA} computing
using HDL-based checkpointing},
journal = {Integr.},
volume = {77},
pages = {180--192},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.011},
doi = {10.1016/J.VLSI.2020.11.011},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/VuNN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangRC21,
author = {Yu Wang and
Jianfeng Ren and
Chien{-}In Henry Chen},
title = {Calibration of optimized minimum inductor bandpass filter with controllable
bandwidth and stopband rejection},
journal = {Integr.},
volume = {81},
pages = {300--312},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.06.002},
doi = {10.1016/J.VLSI.2021.06.002},
timestamp = {Tue, 22 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangRC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangRYYY21,
author = {Fengjuan Wang and
Ruinan Ren and
Xiangkun Yin and
Ningmei Yu and
Yuan Yang},
title = {A transformer with high coupling coefficient and small area based
on {TSV}},
journal = {Integr.},
volume = {81},
pages = {211--220},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.07.003},
doi = {10.1016/J.VLSI.2021.07.003},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangRYYY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WenY21,
author = {Yiming Wen and
Weize Yu},
title = {Breaking LPA-resistant cryptographic circuits with principal component
analysis},
journal = {Integr.},
volume = {80},
pages = {1--4},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.002},
doi = {10.1016/J.VLSI.2021.05.002},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WenY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangZMGCCY21,
author = {Haoyu Yang and
Wei Zhong and
Yuzhe Ma and
Hao Geng and
Ran Chen and
Wanli Chen and
Bei Yu},
title = {{VLSI} mask optimization: From shallow to deep learning},
journal = {Integr.},
volume = {77},
pages = {96--103},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.001},
doi = {10.1016/J.VLSI.2020.11.001},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YangZMGCCY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YuSZHCD21,
author = {Fei Yu and
Hui Shen and
ZiNan Zhang and
Yuanyuan Huang and
Shuo Cai and
Sichun Du},
title = {A new multi-scroll Chua's circuit with composite hyperbolic tangent-cubic
nonlinearity: Complex dynamics, Hardware implementation and Image
encryption application},
journal = {Integr.},
volume = {81},
pages = {71--83},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.011},
doi = {10.1016/J.VLSI.2021.05.011},
timestamp = {Fri, 02 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YuSZHCD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Zambrano-Serrano21,
author = {Ernesto Zambrano{-}Serrano and
Jes{\'{u}}s M. Mu{\~{n}}oz{-}Pacheco and
Fernando E. Serrano and
Luis Abraham S{\'{a}}nchez{-}Gaspariano and
Christos K. Volos},
title = {Experimental verification of the multi-scroll chaotic attractors synchronization
in {PWL} arbitrary-order systems using direct coupling and passivity-based
control},
journal = {Integr.},
volume = {81},
pages = {56--70},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.05.012},
doi = {10.1016/J.VLSI.2021.05.012},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Zambrano-Serrano21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangWWXZ21,
author = {Yuejun Zhang and
Jiawei Wang and
Pengjun Wang and
Xiaoyong Xue and
Xiaoyang Zeng},
title = {Orthogonal obfuscation based key management for multiple {IP} protection},
journal = {Integr.},
volume = {77},
pages = {139--150},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.11.005},
doi = {10.1016/J.VLSI.2020.11.005},
timestamp = {Thu, 28 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangWWXZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangZWWL21,
author = {Yuejun Zhang and
Haiming Zhang and
Pengjun Wang and
Qiufeng Wu and
Gang Li},
title = {A 0.004{\%} resolution {\&} {SAT}},
journal = {Integr.},
volume = {78},
pages = {135--143},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.02.003},
doi = {10.1016/J.VLSI.2021.02.003},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhangZWWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhouCT21,
author = {Han Zhou and
Liang Chen and
Sheldon X.{-}D. Tan},
title = {Robust power grid network design considering {EM} aging effects for
multi-segment wires},
journal = {Integr.},
volume = {77},
pages = {38--47},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.10.001},
doi = {10.1016/J.VLSI.2020.10.001},
timestamp = {Wed, 28 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhouCT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhouKW21,
author = {Junyi Zhou and
Roger Kahn and
Shlomo Weiss},
title = {A novel low power hybrid cache using {GC-EDRAM} cells},
journal = {Integr.},
volume = {81},
pages = {234--245},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.07.005},
doi = {10.1016/J.VLSI.2021.07.005},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhouKW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BaehrBSS20,
author = {Johanna Baehr and
Alessandro Bernardini and
Georg Sigl and
Ulf Schlichtmann},
title = {Machine learning and structural characteristics for reverse engineering},
journal = {Integr.},
volume = {72},
pages = {1--12},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.10.002},
doi = {10.1016/J.VLSI.2019.10.002},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BaehrBSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BanoNA20,
author = {Saleha Bano and
Ghous Bakhsh Narejo and
Syed M. Usman Ali},
title = {Flipped voltage follower based fourth order filter and its application
to portable {ECG} acquisition system},
journal = {Integr.},
volume = {72},
pages = {29--38},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.12.003},
doi = {10.1016/J.VLSI.2019.12.003},
timestamp = {Tue, 24 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BanoNA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BchirAH20,
author = {Mounira Bchir and
Imen Aloui and
Nejib Hassen},
title = {A bulk-driven quasi-floating gate {FVF} current mirror for low voltage,
low power applications},
journal = {Integr.},
volume = {74},
pages = {45--54},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.04.002},
doi = {10.1016/J.VLSI.2020.04.002},
timestamp = {Thu, 25 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BchirAH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BigalkeL20,
author = {Steve Bigalke and
Jens Lienig},
title = {Avoidance vs. repair: New approaches to increasing electromigration
robustness in {VLSI} routing},
journal = {Integr.},
volume = {75},
pages = {189--198},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.04.009},
doi = {10.1016/J.VLSI.2020.04.009},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BigalkeL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CaselliB20,
author = {Michele Caselli and
Andrea Boni},
title = {Modeling and design of 3-D {MPPT} for ultra low power {RF} energy
harvesters},
journal = {Integr.},
volume = {72},
pages = {21--28},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.02.008},
doi = {10.1016/J.VLSI.2020.02.008},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CaselliB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChangelaZV20,
author = {Ankur Changela and
Mazad Zaveri and
Deepak Verma},
title = {{FPGA} implementation of high-performance, resource-efficient Radix-16
{CORDIC} rotator based {FFT} algorithm},
journal = {Integr.},
volume = {73},
pages = {89--100},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.03.008},
doi = {10.1016/J.VLSI.2020.03.008},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChangelaZV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenC20,
author = {Ethan Chen and
Vanessa Chen},
title = {In-sensor time-domain classifiers using pseudo sigmoid activation
functions},
journal = {Integr.},
volume = {73},
pages = {43--49},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.03.002},
doi = {10.1016/J.VLSI.2020.03.002},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChenC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenYLGXYD20,
author = {Hongmei Chen and
Yongsheng Yin and
Tao Liu and
Linhao Gan and
Rui Xiao and
Hui Yan and
Honghui Deng},
title = {A split-based fully digital feedforward background calibration technique
for timing mismatch in {TIADC}},
journal = {Integr.},
volume = {71},
pages = {105--114},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.009},
doi = {10.1016/J.VLSI.2019.11.009},
timestamp = {Mon, 06 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChenYLGXYD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChengMCYH20,
author = {TaiYu Cheng and
Yukata Masuda and
Jun Chen and
Jaehoon Yu and
Masanori Hashimoto},
title = {Logarithm-approximate floating-point multiplier is applicable to power-efficient
neural network training},
journal = {Integr.},
volume = {74},
pages = {19--31},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.05.002},
doi = {10.1016/J.VLSI.2020.05.002},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChengMCYH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CopicLA20,
author = {Milan Copic and
Rainer Leupers and
Gerd Ascheid},
title = {Reducing idle time in event-triggered software execution via runnable
migration and DPM-Aware scheduling},
journal = {Integr.},
volume = {70},
pages = {10--20},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.09.004},
doi = {10.1016/J.VLSI.2019.09.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CopicLA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CuiLCWLK20,
author = {Xiaole Cui and
Qiujun Lin and
Xiaoxin Cui and
Feng Wei and
Xiaoyan Liu and
Jinfeng Kang},
title = {The synthesis method of logic circuits based on the iMemComp gates},
journal = {Integr.},
volume = {74},
pages = {115--126},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.01.007},
doi = {10.1016/J.VLSI.2020.01.007},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CuiLCWLK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DengHW20,
author = {Honghui Deng and
Yijun Hu and
Liang Wang},
title = {An efficient background calibration technique for analog-to-digital
converters based on neural network},
journal = {Integr.},
volume = {74},
pages = {63--70},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.04.003},
doi = {10.1016/J.VLSI.2020.04.003},
timestamp = {Thu, 25 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DengHW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DengSF20,
author = {Libao Deng and
Ning Sun and
Ning Fu},
title = {Boundary scan based interconnect testing design for silicon interposer
in 2.5D ICs},
journal = {Integr.},
volume = {72},
pages = {171--182},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.02.006},
doi = {10.1016/J.VLSI.2020.02.006},
timestamp = {Tue, 24 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DengSF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DrechselJE20,
author = {Tom Drechsel and
Niko Joram and
Frank Ellinger},
title = {An ultra-wideband 6-14 GHz frequency modulated continuous wave primary
radar with 3 cm range resolution},
journal = {Integr.},
volume = {75},
pages = {19--29},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.05.008},
doi = {10.1016/J.VLSI.2020.05.008},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DrechselJE20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DuongTK20,
author = {Vu Trung Duong Le and
Nguyen Thi Thanh Thuy and
Lam Duc Khai},
title = {A fast approach for bitcoin blockchain cryptocurrency mining system},
journal = {Integr.},
volume = {74},
pages = {107--114},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.05.003},
doi = {10.1016/J.VLSI.2020.05.003},
timestamp = {Thu, 04 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DuongTK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/EslamiGRM20,
author = {Mohammad Eslami and
Behnam Ghavami and
Mohsen Raji and
Ali Mahani},
title = {A survey on fault injection methods of digital integrated circuits},
journal = {Integr.},
volume = {71},
pages = {154--163},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.006},
doi = {10.1016/J.VLSI.2019.11.006},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/EslamiGRM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FeilerVSO20,
author = {Andr{\'{e}} Feiler and
Dominik Veit and
Lukas Straczek and
J{\"{u}}rgen Oehm},
title = {Verification of a high precision {CMOS} sensor for angle-of-arrival
{(AOA)} measurement of {LED} light in ultra-miniaturized applications},
journal = {Integr.},
volume = {75},
pages = {1--10},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.05.009},
doi = {10.1016/J.VLSI.2020.05.009},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FeilerVSO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FogacaKMRWW20,
author = {Mateus Foga{\c{c}}a and
Andrew B. Kahng and
Eder Monteiro and
Ricardo Reis and
Lutong Wang and
Mingyu Woo},
title = {On the superiority of modularity-based clustering for determining
placement-relevant clusters},
journal = {Integr.},
volume = {74},
pages = {32--44},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.03.007},
doi = {10.1016/J.VLSI.2020.03.007},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FogacaKMRWW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FreitasMGMVSM20,
author = {David C. C. Freitas and
David F. M. Mota and
Roger C. Goerl and
C{\'{e}}sar A. M. Marcon and
Fabian Vargas and
Jarbas A. N. Silveira and
Jo{\~{a}}o Cesar M. Mota},
title = {PCoSA: {A} product error correction code for use in memory devices
targeting space applications},
journal = {Integr.},
volume = {74},
pages = {71--80},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.04.006},
doi = {10.1016/J.VLSI.2020.04.006},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FreitasMGMVSM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GarzonRCTFCL20,
author = {Esteban Garz{\'{o}}n and
Raffaele De Rose and
Felice Crupi and
Lionel Trojman and
Giovanni Finocchio and
Mario Carpentieri and
Marco Lanuzza},
title = {Assessment of STT-MRAMs based on double-barrier MTJs for cache applications
by means of a device-to-system level simulation framework},
journal = {Integr.},
volume = {71},
pages = {56--69},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.01.002},
doi = {10.1016/J.VLSI.2020.01.002},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GarzonRCTFCL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GhoshBKB20,
author = {Arindrajit Ghosh and
Uddalak Bhattacharya and
Manish Kumar and
Swapna Banerjee},
title = {Compiler compatible 5.66{\unicode{8239}}Mb/mm\({}^{\mbox{2}}\) 8T
1R1W register file in 14{\unicode{8239}}nm FinFET technology},
journal = {Integr.},
volume = {70},
pages = {126--137},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.08.006},
doi = {10.1016/J.VLSI.2019.08.006},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GhoshBKB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GutierrezL20,
author = {Valentin Gutierrez and
Gildas L{\'{e}}ger},
title = {An adaptive simulation framework for {AMS-RF} test quality},
journal = {Integr.},
volume = {73},
pages = {10--17},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.03.003},
doi = {10.1016/J.VLSI.2020.03.003},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GutierrezL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HadjmohammadiNG20,
author = {Mahsa Hadjmohammadi and
Hossein Miar Naimi and
Hojat Ghonoodi},
title = {On the quadrature accuracy of in-phase coupled quadrature {LC} oscillator},
journal = {Integr.},
volume = {75},
pages = {131--140},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.06.004},
doi = {10.1016/J.VLSI.2020.06.004},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HadjmohammadiNG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HerranzL20,
author = {Amadeo de Gracia Herranz and
Marisa L{\'{o}}pez{-}Vallejo},
title = {Time-domain writing architecture for multilevel {RRAM} cells resilient
to temperature and process variations},
journal = {Integr.},
volume = {75},
pages = {141--149},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.07.001},
doi = {10.1016/J.VLSI.2020.07.001},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HerranzL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HosseinyJ20,
author = {Adel Hosseiny and
Ghassem Jaberipur},
title = {Complex exponential functions: {A} high-precision hardware realization},
journal = {Integr.},
volume = {73},
pages = {18--29},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.02.005},
doi = {10.1016/J.VLSI.2020.02.005},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HosseinyJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HussainMMD20,
author = {Sheikh Wasmir Hussain and
Telajala Venkata Mahendra and
Sandeep Mishra and
Anup Dandapat},
title = {Low-power content addressable memory design using two-layer {P-N}
match-line control and sensing},
journal = {Integr.},
volume = {75},
pages = {73--84},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.06.001},
doi = {10.1016/J.VLSI.2020.06.001},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HussainMMD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ImanaL20,
author = {Jos{\'{e}} Luis Ima{\~{n}}a and
Ignacio Luengo},
title = {High-throughput architecture for post-quantum {DME} cryptosystem},
journal = {Integr.},
volume = {75},
pages = {114--121},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.07.002},
doi = {10.1016/J.VLSI.2020.07.002},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ImanaL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ItokoRIM20,
author = {Toshinari Itoko and
Rudy Raymond and
Takashi Imamichi and
Atsushi Matsuo},
title = {Optimization of quantum circuit mapping using gate transformation
and commutation},
journal = {Integr.},
volume = {70},
pages = {43--50},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.10.004},
doi = {10.1016/J.VLSI.2019.10.004},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ItokoRIM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Jafari-Nodoushan20,
author = {Mostafa Jafari{-}Nodoushan and
Alireza Ejlali},
title = {An optimal analytical solution for maximizing expected battery lifetime
using the calculus of variations},
journal = {Integr.},
volume = {71},
pages = {86--94},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.002},
doi = {10.1016/J.VLSI.2019.11.002},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Jafari-Nodoushan20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JainLTGB20,
author = {Anugrah Jain and
Vijay Laxmi and
Meenakshi Tripathi and
Manoj Singh Gaur and
Rimpy Bishnoi},
title = {{TRACK:} An algorithm for fault-tolerant, dynamic and scalable 2D
mesh network-on-chip routing reconfiguration},
journal = {Integr.},
volume = {72},
pages = {92--110},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.01.005},
doi = {10.1016/J.VLSI.2020.01.005},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/JainLTGB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JiangLSFZX20,
author = {Lin Jiang and
Yang Liu and
Rui Shan and
Yani Feng and
Yuan Zhang and
Xiaoyan Xie},
title = {{RDMM:} Runtime dynamic migration mechanism of distributed cache for
reconfigurable array processor},
journal = {Integr.},
volume = {72},
pages = {82--91},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.01.003},
doi = {10.1016/J.VLSI.2020.01.003},
timestamp = {Tue, 24 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JiangLSFZX20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JooqMMF20,
author = {Mohammad Khaleqi Qaleh Jooq and
Ali Mir and
Sattar Mirzakuchaki and
Ali Farmani},
title = {Design and performance analysis of wrap-gate CNTFET-based ring oscillators
for IoT applications},
journal = {Integr.},
volume = {70},
pages = {116--125},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.10.005},
doi = {10.1016/J.VLSI.2019.10.005},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JooqMMF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KabinDKL20,
author = {Ievgen Kabin and
Zoya Dyka and
Dan Klann and
Peter Langend{\"{o}}rfer},
title = {Methods increasing inherent resistance of {ECC} designs against horizontal
attacks},
journal = {Integr.},
volume = {73},
pages = {50--67},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.03.001},
doi = {10.1016/J.VLSI.2020.03.001},
timestamp = {Fri, 14 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KabinDKL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KabraP20,
author = {Naveen Kr. Kabra and
Zuber M. Patel},
title = {Area and power efficient hard multiple generator for radix-8 modulo
2\({}^{\mbox{\emph{n}}}\) - 1 multiplier},
journal = {Integr.},
volume = {75},
pages = {102--113},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.06.009},
doi = {10.1016/J.VLSI.2020.06.009},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KabraP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KangK20,
author = {Jongsung Kang and
Taewhan Kim},
title = {{PV-MAC:} Multiply-and-accumulate unit structure exploiting precision
variability in on-device convolutional neural networks},
journal = {Integr.},
volume = {71},
pages = {76--85},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.003},
doi = {10.1016/J.VLSI.2019.11.003},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KangK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KarmakarJC20,
author = {Rajit Karmakar and
Suman Sekhar Jana and
Santanu Chattopadhyay},
title = {A cellular automata guided two level obfuscation of Finite-State-Machine
for {IP} protection},
journal = {Integr.},
volume = {74},
pages = {93--106},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.04.001},
doi = {10.1016/J.VLSI.2020.04.001},
timestamp = {Thu, 25 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KarmakarJC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhoshaviMBFJS20,
author = {Navid Khoshavi and
Mohammad Maghsoudloo and
Yu Bi and
William Francois and
Luis Gabriel Jaimes and
Arman Sargolzaei},
title = {A survey on attack vectors in stack cache memory},
journal = {Integr.},
volume = {72},
pages = {134--147},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.02.004},
doi = {10.1016/J.VLSI.2020.02.004},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KhoshaviMBFJS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimJCKC20,
author = {Taehwan Kim and
Kwangok Jeong and
Jungyun Choi and
Taewhan Kim and
Kyu{-}Myung Choi},
title = {{SRAM} on-chip monitoring methodology for high yield and energy efficient
memory operation at near threshold voltage},
journal = {Integr.},
volume = {74},
pages = {81--92},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.04.005},
doi = {10.1016/J.VLSI.2020.04.005},
timestamp = {Thu, 25 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KimJCKC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiTLZ20,
author = {Yanbin Li and
Ming Tang and
Yuguang Li and
Huanguo Zhang},
title = {A pre-silicon logic level security verification flow for higher-order
masking schemes against glitches on FPGAs},
journal = {Integr.},
volume = {70},
pages = {60--69},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.09.003},
doi = {10.1016/J.VLSI.2019.09.003},
timestamp = {Mon, 16 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiTLZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiYCZ20,
author = {Xingquan Li and
Bei Yu and
Jianli Chen and
Wenxing Zhu},
title = {{DSA} guiding template assignment with multiple redundant via and
dummy via insertion},
journal = {Integr.},
volume = {70},
pages = {32--42},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.09.011},
doi = {10.1016/J.VLSI.2019.09.011},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiYCZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LippmannUSLWEDG20,
author = {Bernhard Lippmann and
Niklas Unverricht and
Aayush Singla and
Matthias Ludwig and
Michael Werner and
Peter Egger and
Anja D{\"{u}}botzky and
Helmut Gr{\"{a}}b and
Horst A. Gieser and
Martin Rasche and
Oliver Kellermann},
title = {Verification of physical designs using an integrated reverse engineering
flow for nanoscale technologies},
journal = {Integr.},
volume = {71},
pages = {11--29},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.005},
doi = {10.1016/J.VLSI.2019.11.005},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LippmannUSLWEDG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuC20,
author = {Feiran Liu and
Chien{-}In Henry Chen},
title = {High two-signal dynamic range and accurate frequency measurement for
close frequency separation wideband digital receiver using adaptive
gain control and adaptive thresholding},
journal = {Integr.},
volume = {72},
pages = {72--81},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.012},
doi = {10.1016/J.VLSI.2019.11.012},
timestamp = {Tue, 24 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiuC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LyuWCS20,
author = {Liangjian Lyu and
Yu Wang and
Chixiao Chen and
Chuanjin Richard Shi},
title = {A 0.6V 1.07 {\(\mu\)}W/Channel neural interface {IC} using level-shifted
feedback},
journal = {Integr.},
volume = {70},
pages = {51--59},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.001},
doi = {10.1016/J.VLSI.2019.11.001},
timestamp = {Fri, 12 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LyuWCS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaCJHLX20,
author = {Shang Ma and
Wei Cao and
Shengqiang Jiang and
Jianhao Hu and
Xin Lei and
Xiongzhong Xiong},
title = {Design and implementation of {SVM} {OTPC} searching based on Shared
Dot Product Matrix},
journal = {Integr.},
volume = {71},
pages = {30--37},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.007},
doi = {10.1016/J.VLSI.2019.11.007},
timestamp = {Fri, 14 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MaCJHLX20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MahmoodiG20,
author = {Ehsan Mahmoodi and
Morteza Gholipour},
title = {Design space exploration of low-power flip-flops in FinFET technology},
journal = {Integr.},
volume = {75},
pages = {52--62},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.06.006},
doi = {10.1016/J.VLSI.2020.06.006},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MahmoodiG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaryanSAR20,
author = {Mohammad Moradinezhad Maryan and
Reza Rezaei Siahrood and
Seyed Javad Azhari and
Abdolreza Rahmati},
title = {A high-precision current-mode multifunction analog cell suitable for
computational signal processing},
journal = {Integr.},
volume = {70},
pages = {80--89},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.09.010},
doi = {10.1016/J.VLSI.2019.09.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MaryanSAR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MauroRPFB20,
author = {Alfio Di Mauro and
Davide Rossi and
Antonio Pullini and
Philippe Flatresse and
Luca Benini},
title = {Performance-aware predictive-model-based on-chip body-bias regulation
strategy for an {ULP} multi-core cluster in 28 nm {UTBB} {FD-SOI}},
journal = {Integr.},
volume = {72},
pages = {194--207},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.12.006},
doi = {10.1016/J.VLSI.2019.12.006},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MauroRPFB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MinettoDHC20,
author = {Andrea Minetto and
Bernd Deutschmann and
Oliver H{\"{a}}berlen and
Gilberto Curatola},
title = {System-level evaluation of dynamic effects in a GaN-based class-E
power amplifier},
journal = {Integr.},
volume = {75},
pages = {11--18},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.05.010},
doi = {10.1016/J.VLSI.2020.05.010},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MinettoDHC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NajafiBO20,
author = {Amir Najafi and
Lennart Bamberg and
Alberto Garc{\'{\i}}a Ortiz},
title = {Misalignment-aware energy modeling of narrow buses for data encoding
schemes},
journal = {Integr.},
volume = {72},
pages = {58--65},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.01.001},
doi = {10.1016/J.VLSI.2020.01.001},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/NajafiBO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NarimaniSE20,
author = {Reza Narimani and
Bardia Safaei and
Alireza Ejlali},
title = {A comprehensive analysis on the resilience of adiabatic logic families
against transient faults},
journal = {Integr.},
volume = {72},
pages = {183--193},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.01.004},
doi = {10.1016/J.VLSI.2020.01.004},
timestamp = {Fri, 23 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NarimaniSE20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NathB20,
author = {Pallab Kumar Nath and
Swapna Banerjee},
title = {A high throughput pass parallel block decoder architecture for {JPEG}
2000 that prevents stalling in the decoding process},
journal = {Integr.},
volume = {71},
pages = {170--182},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.013},
doi = {10.1016/J.VLSI.2019.11.013},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NathB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NeunerG20,
author = {Maximilian Neuner and
Helmut Graeb},
title = {Verification and revision of the power-down mode for hierarchical
analog circuits},
journal = {Integr.},
volume = {73},
pages = {1--9},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.02.009},
doi = {10.1016/J.VLSI.2020.02.009},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/NeunerG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NiemannASHT20,
author = {Christoph Niemann and
Munawar Ali and
Obaid Ullah Shah and
Jakob Heller and
Dirk Timmermann},
title = {Sensor based adaptive voltage scaling on FPGAs: Calibration and parametrization},
journal = {Integr.},
volume = {75},
pages = {30--39},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.05.006},
doi = {10.1016/J.VLSI.2020.05.006},
timestamp = {Thu, 04 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/NiemannASHT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NojehdehA20,
author = {Mohammadreza Esmali Nojehdeh and
Mustafa Altun},
title = {Systematic synthesis of approximate adders and multipliers with accurate
error calculations},
journal = {Integr.},
volume = {70},
pages = {99--107},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.10.001},
doi = {10.1016/J.VLSI.2019.10.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NojehdehA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NtouskasEP20,
author = {Fotios Ntouskas and
Constantinos Efstathiou and
Kiamal Z. Pekmestzi},
title = {Efficient design of magnitude and 2's complement comparators},
journal = {Integr.},
volume = {71},
pages = {164--169},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.015},
doi = {10.1016/J.VLSI.2019.11.015},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NtouskasEP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OgasaharaHKIAIK20,
author = {Yasuhiro Ogasahara and
Yohei Hori and
Toshihiro Katashita and
Tomoki Iizuka and
Hiromitsu Awano and
Makoto Ikeda and
Hanpei Koike},
title = {Implementation of pseudo-linear feedback shift register-based physical
unclonable functions on silicon and sufficient Challenge-Response
pair acquisition using Built-In Self-Test before shipping},
journal = {Integr.},
volume = {71},
pages = {144--153},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.12.002},
doi = {10.1016/J.VLSI.2019.12.002},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/OgasaharaHKIAIK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PalN20,
author = {Pratosh Kumar Pal and
Rajendra Kumar Nagaria},
title = {A Sub-1 {V} nanopower subthreshold current and voltage reference using
current subtraction technique and cascoded active load},
journal = {Integr.},
volume = {71},
pages = {115--124},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.016},
doi = {10.1016/J.VLSI.2019.11.016},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PalN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PanPXHX20,
author = {Min Pan and
Lili Pang and
Jiaye Xie and
Yufei Han and
Qiqing Xu},
title = {A 0.6V 44.6 ppm/{\textordmasculine}C subthreshold {CMOS} voltage reference
with wide temperature range and inherent leakage compensation},
journal = {Integr.},
volume = {72},
pages = {111--122},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.01.008},
doi = {10.1016/J.VLSI.2020.01.008},
timestamp = {Wed, 28 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PanPXHX20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PaolinoPPMRS20,
author = {Carmine Paolino and
Luciano Prono and
Fabio Pareschi and
Mauro Mangia and
Riccardo Rovatti and
Gianluca Setti},
title = {A passive and low-complexity Compressed Sensing architecture based
on a charge-redistribution {SAR} {ADC}},
journal = {Integr.},
volume = {75},
pages = {40--51},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.05.007},
doi = {10.1016/J.VLSI.2020.05.007},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PaolinoPPMRS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Patronik20,
author = {Piotr Patronik},
title = {On reverse converters for arbitrary multi-moduli {RNS}},
journal = {Integr.},
volume = {75},
pages = {158--167},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.07.003},
doi = {10.1016/J.VLSI.2020.07.003},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Patronik20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PengDST20,
author = {Shaoyi Peng and
Ertugrul Demircan and
Mehul D. Shroff and
Sheldon X.{-}D. Tan},
title = {Full-chip wire-oriented back-end-of-line {TDDB} hotspot detection
and lifetime analysis},
journal = {Integr.},
volume = {70},
pages = {90--98},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.09.012},
doi = {10.1016/J.VLSI.2019.09.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PengDST20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PengPBD20,
author = {Hui Peng and
Herbert De Pauw and
Pieter Bauwens and
Jan Doutreloigne},
title = {A high-efficiency charge pump with charge recycling scheme and finger
boost capacitor},
journal = {Integr.},
volume = {75},
pages = {85--90},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.06.002},
doi = {10.1016/J.VLSI.2020.06.002},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PengPBD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PovoaCMHLG20,
author = {Ricardo P{\'{o}}voa and
Ant{\'{o}}nio Canelas and
Ricardo Martins and
Nuno Horta and
Nuno Louren{\c{c}}o and
Jo{\~{a}}o Goes},
title = {A new family of {CMOS} inverter-based OTAs for biomedical and healthcare
applications},
journal = {Integr.},
volume = {71},
pages = {38--48},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.12.004},
doi = {10.1016/J.VLSI.2019.12.004},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PovoaCMHLG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/QianHDZZZ20,
author = {Junyan Qian and
Bisheng Huang and
Hao Ding and
Zhide Zhou and
Lingzhong Zhao and
Zhongyi Zhai},
title = {An efficient multiple shortest augmenting paths algorithm for constructing
high performance {VLSI} subarray},
journal = {Integr.},
volume = {75},
pages = {63--72},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.06.005},
doi = {10.1016/J.VLSI.2020.06.005},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/QianHDZZZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/QinWMMH20,
author = {Maoyuan Qin and
Xinmu Wang and
Baolei Mao and
Dejun Mu and
Wei Hu},
title = {A formal model for proving hardware timing properties and identifying
timing channels},
journal = {Integr.},
volume = {72},
pages = {123--133},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.02.001},
doi = {10.1016/J.VLSI.2020.02.001},
timestamp = {Tue, 24 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/QinWMMH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RaghavB20,
author = {Himadri Singh Raghav and
V. A. Bartlett},
title = {Investigating the influence of adiabatic load on the 4-phase adiabatic
system design},
journal = {Integr.},
volume = {75},
pages = {150--157},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.06.007},
doi = {10.1016/J.VLSI.2020.06.007},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RaghavB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RahmanRWTKFFAT20,
author = {M. Tanjidur Rahman and
M. Sazadur Rahman and
Huanyu Wang and
Shahin Tajik and
Waleed Khalil and
Farimah Farahmandi and
Domenic Forte and
Navid Asadizanjani and
Mark M. Tehranipoor},
title = {Defense-in-depth: {A} recipe for logic locking to prevail},
journal = {Integr.},
volume = {72},
pages = {39--57},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.12.007},
doi = {10.1016/J.VLSI.2019.12.007},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RahmanRWTKFFAT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RathorGS20,
author = {Vijaypal Singh Rathor and
Bharat Garg and
G. K. Sharma},
title = {New lightweight Anti-SAT block design and obfuscation technique to
thwart removal attack},
journal = {Integr.},
volume = {75},
pages = {178--188},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.05.001},
doi = {10.1016/J.VLSI.2020.05.001},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RathorGS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RazaviR20,
author = {Sayyed Mohammad Razavi and
Seyyed Mohammad Razavi},
title = {An efficient and reliable MRF-based methodology for designing low-power
{VLSI} circuits},
journal = {Integr.},
volume = {73},
pages = {77--88},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.03.005},
doi = {10.1016/J.VLSI.2020.03.005},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RazaviR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Ren20,
author = {Jijun Ren},
title = {Digital predistorter with improving index accuracy of lookup table
based on {FPGA}},
journal = {Integr.},
volume = {71},
pages = {70--75},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.004},
doi = {10.1016/J.VLSI.2019.11.004},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Ren20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RheinlanderW20,
author = {Carl Christian Rheinl{\"{a}}nder and
Norbert Wehn},
title = {Harvester-aware transient computing: Utilizing the mechanical inertia
of kinetic energy harvesters for a proactive frequency-based power
loss detection},
journal = {Integr.},
volume = {75},
pages = {122--130},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.06.010},
doi = {10.1016/J.VLSI.2020.06.010},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RheinlanderW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RizzoCZ20,
author = {Roberto Giorgio Rizzo and
Andrea Calimera and
Jun Zhou},
title = {Corrigendum to"Approximate error detection-correction for efficient
adaptive voltage Over-Scaling"[Integration 63 {(2018)} 220-231]},
journal = {Integr.},
volume = {70},
pages = {159},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.011},
doi = {10.1016/J.VLSI.2019.11.011},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RizzoCZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SadrafshariSS20,
author = {Vala Sadrafshari and
Shamin Sadrafshari and
Mohammad Sharifkhani},
title = {Yield constrained automated design algorithm for power optimized pipeline
{ADC}},
journal = {Integr.},
volume = {74},
pages = {55--62},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.04.004},
doi = {10.1016/J.VLSI.2020.04.004},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SadrafshariSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SahooM20,
author = {Sauvagya Ranjan Sahoo and
Kamalakanta Mahapatra},
title = {A novel area efficient on-chip RO-Sensor for recycled {IC} detection},
journal = {Integr.},
volume = {70},
pages = {138--150},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.10.007},
doi = {10.1016/J.VLSI.2019.10.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SahooM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Saraza-Canflanca20,
author = {Pablo Saraza{-}Canflanca and
Javier Diaz{-}Fortuny and
Rafael Castro{-}L{\'{o}}pez and
Elisenda Roca and
Javier Mart{\'{\i}}n{-}Mart{\'{\i}}nez and
Rosana Rodr{\'{\i}}guez and
Montserrat Nafr{\'{\i}}a and
Francisco V. Fern{\'{a}}ndez},
title = {A robust and automated methodology for the analysis of Time-Dependent
Variability at transistor level},
journal = {Integr.},
volume = {72},
pages = {13--20},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.02.002},
doi = {10.1016/J.VLSI.2020.02.002},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Saraza-Canflanca20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Shahroury20,
author = {Fadi Riad Shahroury},
title = {Design of a low-power {CMOS} transceiver for semi-passive wireless
sensor network application},
journal = {Integr.},
volume = {71},
pages = {95--104},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.010},
doi = {10.1016/J.VLSI.2019.11.010},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Shahroury20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShaikSG20,
author = {Jani Babu Shaik and
Sonal Singhal and
Nilesh Goel},
title = {Analysis of {SRAM} metrics for data dependent {BTI} degradation and
process variability},
journal = {Integr.},
volume = {72},
pages = {148--162},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.01.006},
doi = {10.1016/J.VLSI.2020.01.006},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShaikSG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShepovalovA20,
author = {Maxim Shepovalov and
Venkatesh Akella},
title = {{FPGA} and GPU-based acceleration of {ML} workloads on Amazon cloud
- {A} case study using gradient boosted decision tree library},
journal = {Integr.},
volume = {70},
pages = {1--9},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.09.007},
doi = {10.1016/J.VLSI.2019.09.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShepovalovA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShijiW20,
author = {Zheng Shiji and
Guoquan Wu},
title = {A folded-cascode mixer for mixing-spur suppressions in a 2.4-to-5.8{\unicode{8239}}GHz
transmitter},
journal = {Integr.},
volume = {70},
pages = {108--115},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.10.003},
doi = {10.1016/J.VLSI.2019.10.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShijiW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SimoglouXSS20,
author = {Stavros Simoglou and
Nikolaos Xiromeritis and
Christos P. Sotiriou and
Nikolaos Sketopoulos},
title = {Graph-based {STA} for asynchronous controllers},
journal = {Integr.},
volume = {75},
pages = {91--101},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.05.005},
doi = {10.1016/J.VLSI.2020.05.005},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SimoglouXSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SivaramGP20,
author = {Ranjana Sivaram and
Kirti Gupta and
Neeta Pandey},
title = {A new realization scheme for dynamic {PFSCL} style},
journal = {Integr.},
volume = {75},
pages = {169--177},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.05.004},
doi = {10.1016/J.VLSI.2020.05.004},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SivaramGP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SpagnoloPC20,
author = {Fanny Spagnolo and
Stefania Perri and
Pasquale Corsonello},
title = {Design of a real-time face detection architecture for heterogeneous
systems-on-chips},
journal = {Integr.},
volume = {74},
pages = {1--10},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.04.008},
doi = {10.1016/J.VLSI.2020.04.008},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SpagnoloPC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SravaniR20,
author = {K. Sravani and
Rathnamala Rao},
title = {A High Performance Early Acknowledged Asynchronous Pipeline using
Hybrid-logic Encoding},
journal = {Integr.},
volume = {71},
pages = {134--143},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.12.001},
doi = {10.1016/J.VLSI.2019.12.001},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SravaniR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ThangkhiewZWDS20,
author = {Phrangboklang Lyngton Thangkhiew and
Alwin Zulehner and
Robert Wille and
Kamalika Datta and
Indranil Sengupta},
title = {An efficient memristor crossbar architecture for mapping Boolean functions
using Binary Decision Diagrams {(BDD)}},
journal = {Integr.},
volume = {71},
pages = {125--133},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.014},
doi = {10.1016/J.VLSI.2019.11.014},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ThangkhiewZWDS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TolbaEOEASR20,
author = {Mohamed F. Tolba and
Ahmed S. Elwakil and
Hammam Orabi and
Mohammed Elnawawy and
Fadi A. Aloul and
Assim Sagahyroon and
Ahmed G. Radwan},
title = {{FPGA} implementation of a chaotic oscillator with odd/even symmetry
and its application},
journal = {Integr.},
volume = {72},
pages = {163--170},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.02.003},
doi = {10.1016/J.VLSI.2020.02.003},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TolbaEOEASR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TuZZZ20,
author = {Jiankai Tu and
Qinming Zhang and
Chenyang Zhang and
Chengwei Zhou},
title = {A Noise-Aware Real-Time Processing Approach for Electroencephalogram
Signal Classification},
journal = {Integr.},
volume = {71},
pages = {49--55},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.12.005},
doi = {10.1016/J.VLSI.2019.12.005},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TuZZZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VallicelliTGBBF20,
author = {Elia A. Vallicelli and
Davide Turossi and
Luca Gelmi and
Alessandro Ba{\`{u}} and
Roberto Bertoni and
Walter Fulgione and
Alessandro Quintino and
Massimo Corcione and
Andrea Baschirotto and
Marcello De Matteis},
title = {A 0.3nV/{\(\surd\)}Hz input-referred-noise analog front-end for radiation-induced
thermo-acoustic pulses},
journal = {Integr.},
volume = {74},
pages = {11--18},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.04.007},
doi = {10.1016/J.VLSI.2020.04.007},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/VallicelliTGBBF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VidhyadharanDVY20,
author = {Sanjay Vidhyadharan and
Surya Shankar Dan and
Abhay S. Vidhyadharan and
Ramakant Yadav and
Simhadri Hariprasad},
title = {Novel gate-overlap tunnel {FET} based innovative ultra-low-power ternary
flash {ADC}},
journal = {Integr.},
volume = {73},
pages = {101--113},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.03.006},
doi = {10.1016/J.VLSI.2020.03.006},
timestamp = {Thu, 23 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/VidhyadharanDVY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VohraSG20,
author = {Harpreet Vohra and
Ashima Singh and
Sukhpal Singh Gill},
title = {An innovative two-stage data compression scheme using adaptive block
merging technique},
journal = {Integr.},
volume = {73},
pages = {68--76},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.03.004},
doi = {10.1016/J.VLSI.2020.03.004},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/VohraSG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XieCWY20,
author = {Lei Xie and
Hao Cai and
Chao Wang and
Jun Yang},
title = {Towards an automated design flow for memristor based {VLSI} circuits},
journal = {Integr.},
volume = {70},
pages = {21--31},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.09.009},
doi = {10.1016/J.VLSI.2019.09.009},
timestamp = {Thu, 18 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/XieCWY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuCGYYWH20,
author = {Qi Xu and
Song Chen and
Hao Geng and
Bo Yuan and
Bei Yu and
Feng Wu and
Zhengfeng Huang},
title = {Fault tolerance in memristive crossbar-based neuromorphic computing
systems},
journal = {Integr.},
volume = {70},
pages = {70--79},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.09.008},
doi = {10.1016/J.VLSI.2019.09.008},
timestamp = {Mon, 16 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/XuCGYYWH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YuZQ20,
author = {Wenjian Yu and
Cheng Zhuo and
Weikang Qian},
title = {Introduction to special issue of 2019 China Semiconductor Technology
International Conference {(CSTIC)} Symposium on Design and Automation
of Circuits and Systems},
journal = {Integr.},
volume = {75},
pages = {168},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.06.008},
doi = {10.1016/J.VLSI.2020.06.008},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YuZQ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhanS20,
author = {Wenfa Zhan and
Zhiwei Shao},
title = {Test patterns reordering method based on Gamma distribution},
journal = {Integr.},
volume = {72},
pages = {66--71},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.12.008},
doi = {10.1016/J.VLSI.2019.12.008},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhanS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangDY20,
author = {Zhiming Zhang and
Jaya Dofe and
Qiaoyan Yu},
title = {Improving power analysis attack resistance using intrinsic noise in
3D ICs},
journal = {Integr.},
volume = {73},
pages = {30--42},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.02.007},
doi = {10.1016/J.VLSI.2020.02.007},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhangDY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangGBM20,
author = {Chaoping Zhang and
Robert Gallichan and
David M. Budgett and
Daniel McCormick},
title = {A precision low-power analog front end in 180{\unicode{8239}}nm {CMOS}
for wireless implantable capacitive pressure sensors},
journal = {Integr.},
volume = {70},
pages = {151--158},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.10.006},
doi = {10.1016/J.VLSI.2019.10.006},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangGBM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhuHYZCZD20,
author = {Ziran Zhu and
Zhipeng Huang and
Peng Yang and
Wenxing Zhu and
Jianli Chen and
Hanbin Zhou and
Senhua Dong},
title = {Mixed-cell-height legalization considering complex minimum width constraints
and half-row fragmentation effect},
journal = {Integr.},
volume = {71},
pages = {1--10},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.008},
doi = {10.1016/J.VLSI.2019.11.008},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhuHYZCZD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AbdulfattahTY19,
author = {Ahmad N. Abdulfattah and
Charalampos C. Tsimenidis and
Alex Yakovlev},
title = {Ultra-low power \emph{m}-sequence code generator for body sensor node
applications},
journal = {Integr.},
volume = {65},
pages = {231--240},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.10.004},
doi = {10.1016/J.VLSI.2017.10.004},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AbdulfattahTY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AdionoAHPS19,
author = {Trio Adiono and
Khilda Afifah and
Suksmandhira Harimurti and
Prasetiyo and
Amy Hamidah Salman},
title = {Fully integrated transceiver module with a temperature compensation
for high bit rate contactless smart card},
journal = {Integr.},
volume = {64},
pages = {92--104},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.09.001},
doi = {10.1016/J.VLSI.2018.09.001},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AdionoAHPS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AfacanD19,
author = {Engin Afacan and
G{\"{u}}nhan D{\"{u}}ndar},
title = {A comprehensive analysis on differential cross-coupled {CMOS} {LC}
oscillators via multi-objective optimization},
journal = {Integr.},
volume = {67},
pages = {162--169},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.012},
doi = {10.1016/J.VLSI.2019.01.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AfacanD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AgarwalSSRHSB19,
author = {Varsha Agarwal and
Ananya Singla and
Mahammad Samiuddin and
Sudip Roy and
Tsung{-}Yi Ho and
Indranil Sengupta and
Bhargab B. Bhattacharya},
title = {Scheduling algorithms for reservoir- and mixer-aware sample preparation
with microfluidic biochips},
journal = {Integr.},
volume = {65},
pages = {428--443},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.01.002},
doi = {10.1016/J.VLSI.2018.01.002},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AgarwalSSRHSB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AghaeiS19,
author = {Tohid Aghaei and
Ali Naderi Saatlo},
title = {A new strategy to design low power translinear based {CMOS} analog
multiplier},
journal = {Integr.},
volume = {69},
pages = {180--188},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.03.009},
doi = {10.1016/J.VLSI.2019.03.009},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AghaeiS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AghnoutK19,
author = {Soraya Aghnout and
Gholamreza Karimi},
title = {Modeling triplet spike timing dependent plasticity using a hybrid
TFT-memristor neuromorphic synapse},
journal = {Integr.},
volume = {64},
pages = {184--191},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.004},
doi = {10.1016/J.VLSI.2018.10.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AghnoutK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AnEZSY19,
author = {Hongyu An and
M. Amimul Ehsan and
Zhen Zhou and
Fangyang Shen and
Yang Yi},
title = {Monolithic 3D neuromorphic computing system with hybrid {CMOS} and
memristor-based synapses and neurons},
journal = {Integr.},
volume = {65},
pages = {273--281},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.10.009},
doi = {10.1016/J.VLSI.2017.10.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AnEZSY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AnagnostouGHFGT19,
author = {P. Anagnostou and
Andres Gomez and
Pascal A. Hager and
Hamed Fatemi and
Jos{\'{e}} Pineda de Gyvez and
Lothar Thiele and
Luca Benini},
title = {Energy and power awareness in hardware schedulers for energy harvesting
IoT SoCs},
journal = {Integr.},
volume = {67},
pages = {33--43},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.03.007},
doi = {10.1016/J.VLSI.2019.03.007},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AnagnostouGHFGT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ArabiBBA19,
author = {Abderrazak Arabi and
Nacerdine Bourouba and
Abdesslam Belaout and
Mouloud Ayad},
title = {An accurate classifier based on adaptive neuro-fuzzy and features
selection techniques for fault classification in analog circuits},
journal = {Integr.},
volume = {64},
pages = {50--59},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.08.001},
doi = {10.1016/J.VLSI.2018.08.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ArabiBBA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AshokS19,
author = {Prathiba Ashok and
Kanchana Bhaaskaran Vettuvanam Somasundaram},
title = {Hardware footprints of S-box in lightweight symmetric block ciphers
for IoT and {CPS} information security systems},
journal = {Integr.},
volume = {69},
pages = {266--278},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.05.003},
doi = {10.1016/J.VLSI.2019.05.003},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AshokS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AzimiDSCGC19,
author = {Sarah Azimi and
Boyang Du and
Luca Sterpone and
David Merodio Codinachs and
Raoul Grimoldi and
L. Cattaneo},
title = {A new {CAD} tool for Single Event Transient Analysis and mitigation
on Flash-based FPGAs},
journal = {Integr.},
volume = {67},
pages = {73--81},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.02.001},
doi = {10.1016/J.VLSI.2019.02.001},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AzimiDSCGC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BabuMLS19,
author = {Geethu Sathees Babu and
Lakshmi Renuka Madala and
Gopalakrishnan Lakshminarayanan and
Mathini Sellathurai},
title = {Low-complex processing element architecture for successive cancellation
decoder},
journal = {Integr.},
volume = {66},
pages = {80--87},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.005},
doi = {10.1016/J.VLSI.2019.01.005},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BabuMLS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BagheriyeTSM19,
author = {Leila Bagheriye and
Siroos Toofan and
Roghayeh Saeidi and
Farshad Moradi},
title = {Highly stable, low power FinFET {SRAM} cells with exploiting dynamic
back-gate biasing},
journal = {Integr.},
volume = {65},
pages = {128--137},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.011},
doi = {10.1016/J.VLSI.2018.11.011},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BagheriyeTSM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BahramaliL19,
author = {Asghar Bahramali and
Marisa L{\'{o}}pez{-}Vallejo},
title = {A low power {RFID} based energy harvesting temperature resilient CMOS-only
reference voltage},
journal = {Integr.},
volume = {67},
pages = {155--161},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.014},
doi = {10.1016/J.VLSI.2019.01.014},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BahramaliL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BalanRRVSYMM19,
author = {Zechariah Balan and
Harikrishnan Ramiah and
Jagadheswaran Rajendran and
Nandini Vitee and
Pravinah Nair Shasidharan and
Jun Yin and
Pui{-}In Mak and
Rui Paulo Martins},
title = {A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee
receiver consuming 2{\unicode{8239}}mA},
journal = {Integr.},
volume = {66},
pages = {112--118},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.009},
doi = {10.1016/J.VLSI.2019.01.009},
timestamp = {Tue, 20 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BalanRRVSYMM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BambergJPO19,
author = {Lennart Bamberg and
Jan Moritz Joseph and
Thilo Pionteck and
Alberto Garc{\'{\i}}a Ortiz},
title = {Crosstalk optimization for through-silicon vias by exploiting temporal
signal misalignment},
journal = {Integr.},
volume = {67},
pages = {60--72},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.04.009},
doi = {10.1016/J.VLSI.2019.04.009},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BambergJPO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BambergNO19,
author = {Lennart Bamberg and
Amir Najafi and
Alberto Garc{\'{\i}}a Ortiz},
title = {Edge effect aware low-power crosstalk avoidance technique for 3D integration},
journal = {Integr.},
volume = {69},
pages = {98--110},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.03.008},
doi = {10.1016/J.VLSI.2018.03.008},
timestamp = {Fri, 05 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BambergNO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BuW19,
author = {Dengli Bu and
Pengjun Wang},
title = {An improved {KFDD} based reversible circuit synthesis method},
journal = {Integr.},
volume = {69},
pages = {251--265},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.04.008},
doi = {10.1016/J.VLSI.2019.04.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BuW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BurrascanoCFLR19,
author = {Pietro Burrascano and
Giulia Di Capua and
Nicola Femia and
Stefano Laureti and
Marco Ricci},
title = {A Pulse Compression procedure for power inductors modeling up to moderate
non-linearity},
journal = {Integr.},
volume = {66},
pages = {16--23},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.010},
doi = {10.1016/J.VLSI.2019.01.010},
timestamp = {Wed, 14 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BurrascanoCFLR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CabaRDBAL19,
author = {Juli{\'{a}}n Caba and
Fernando Rinc{\'{o}}n and
Julio Dondo and
Jes{\'{u}}s Barba and
Manuel J. Abaldea and
Juan Carlos L{\'{o}}pez},
title = {Testing framework for on-board verification of {HLS} modules using
grey-box technique and {FPGA} overlays},
journal = {Integr.},
volume = {68},
pages = {129--138},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.011},
doi = {10.1016/J.VLSI.2019.06.011},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CabaRDBAL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CaiYZ19,
author = {Xiangwei Cai and
Jieming Yin and
Pingqiang Zhou},
title = {An orchestrated NoC prioritization mechanism for heterogeneous {CPU-GPU}
systems},
journal = {Integr.},
volume = {65},
pages = {344--350},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.04.005},
doi = {10.1016/J.VLSI.2018.04.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CaiYZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Carbajal-GomezT19,
author = {Victor Hugo Carbajal{-}Gomez and
Esteban Tlelo{-}Cuautle and
Jes{\'{u}}s M. Mu{\~{n}}oz{-}Pacheco and
Luis Gerardo de la Fraga and
Carlos S{\'{a}}nchez{-}L{\'{o}}pez and
Francisco Vidal Fern{\'{a}}ndez Fern{\'{a}}ndez},
title = {Optimization and {CMOS} design of chaotic oscillators robust to {PVT}
variations: {INVITED}},
journal = {Integr.},
volume = {65},
pages = {32--42},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.010},
doi = {10.1016/J.VLSI.2018.10.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Carbajal-GomezT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChakrabortySGKM19,
author = {Anindita Chakraborty and
Vivek Saurabh and
Partha Sarathi Gupta and
Rituraj Kumar and
Saikat Majumdar and
Smriti Das and
Hafizur Rahaman},
title = {\emph{In}-memory designing of Delay and Toggle flip-flops utilizing
Memristor Aided loGIC {(MAGIC)}},
journal = {Integr.},
volume = {66},
pages = {24--34},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.12.005},
doi = {10.1016/J.VLSI.2018.12.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChakrabortySGKM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenJZT19,
author = {Xizi Chen and
Jingbo Jiang and
Jingyang Zhu and
Chi{-}Ying Tsui},
title = {SubMac: Exploiting the subword-based computation in RRAM-based {CNN}
accelerator for energy saving and speedup},
journal = {Integr.},
volume = {69},
pages = {356--368},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.09.001},
doi = {10.1016/J.VLSI.2019.09.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChenJZT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChengWCY19,
author = {Yuan Cheng and
Chao Wang and
Hai{-}Bao Chen and
Hao Yu},
title = {A large-scale in-memory computing for deep neural network with trained
quantization},
journal = {Integr.},
volume = {69},
pages = {345--355},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.08.004},
doi = {10.1016/J.VLSI.2019.08.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChengWCY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChiangCCCLK19,
author = {Yu{-}Fan Chiang and
Wei{-}Yu Chien and
Yue{-}Der Chih and
Jonathan Chang and
Chrong Jung Lin and
Ya{-}Chin King},
title = {FinFET {CMOS} logic gates with non-volatile states for reconfigurable
computing systems},
journal = {Integr.},
volume = {65},
pages = {97--103},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.007},
doi = {10.1016/J.VLSI.2018.11.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChiangCCCLK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChuSWX19,
author = {Zhufei Chu and
Lei Shi and
Lun{-}Yao Wang and
Yinshui Xia},
title = {Multi-objective algebraic rewriting in XOR-majority graphs},
journal = {Integr.},
volume = {69},
pages = {40--49},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.08.005},
doi = {10.1016/J.VLSI.2019.08.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChuSWX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ClarkAH19,
author = {Lawrence T. Clark and
James Adams and
Keith E. Holbert},
title = {Reliable techniques for integrated circuit identification and true
random number generation using 1.5-transistor flash memory},
journal = {Integr.},
volume = {65},
pages = {263--272},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.10.001},
doi = {10.1016/J.VLSI.2017.10.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ClarkAH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CofanoVSCTG19,
author = {Mario Cofano and
Marco Vacca and
Giulia Santoro and
Giovanni Causapruno and
Giovanna Turvani and
Mariagrazia Graziano},
title = {Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive
algorithms},
journal = {Integr.},
volume = {66},
pages = {153--163},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.02.007},
doi = {10.1016/J.VLSI.2019.02.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CofanoVSCTG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CookSST19,
author = {Chase Cook and
Sheriff Sadiqbatcha and
Zeyu Sun and
Sheldon X.{-}D. Tan},
title = {Reliability based hardware Trojan design using physics-based electromigration
models},
journal = {Integr.},
volume = {66},
pages = {9--15},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.011},
doi = {10.1016/J.VLSI.2019.01.011},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CookSST19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CookZSHT19,
author = {Chase Cook and
Hengyang Zhao and
Takashi Sato and
Masayuki Hiromoto and
Sheldon X.{-}D. Tan},
title = {GPU-based Ising computing for solving max-cut combinatorial optimization
problems},
journal = {Integr.},
volume = {69},
pages = {335--344},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.07.003},
doi = {10.1016/J.VLSI.2019.07.003},
timestamp = {Mon, 17 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CookZSHT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CostanzoGMFSL19,
author = {Ferdinando Costanzo and
Rocco Giofr{\`{e}} and
Antonino Massari and
Marziale Feudale and
Andrea Suriani and
Ernesto Limiti},
title = {A {MMIC} power amplifier in GaN on Si technology for next generation
{Q} band high throughput satellite systems},
journal = {Integr.},
volume = {68},
pages = {139--146},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.007},
doi = {10.1016/J.VLSI.2019.06.007},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CostanzoGMFSL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CrocettiBBSCF19,
author = {Luca Crocetti and
Luca Baldanzi and
Matteo Bertolucci and
Luca Sarti and
Berardino Carnevale and
Luca Fanucci},
title = {A simulated approach to evaluate side-channel attack countermeasures
for the Advanced Encryption Standard},
journal = {Integr.},
volume = {68},
pages = {80--86},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.005},
doi = {10.1016/J.VLSI.2019.06.005},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CrocettiBBSCF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DaryabariZRH19,
author = {Farzad Daryabari and
Abdulhamid Zahedi and
Abbas Rezaei and
Mohsen Hayati},
title = {Gain-controlled noise-reduction {LNA} design using source-bulk resistors
and double common-source topology},
journal = {Integr.},
volume = {68},
pages = {50--61},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.003},
doi = {10.1016/J.VLSI.2019.06.003},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DaryabariZRH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DekimpeXSGFB19,
author = {Remi Dekimpe and
Pengcheng Xu and
Maxime Schramme and
Pierre G{\'{e}}rard and
Denis Flandre and
David Bol},
title = {A battery-less {BLE} smart sensor for room occupancy tracking supplied
by 2.45-GHz wireless power transfer},
journal = {Integr.},
volume = {67},
pages = {8--18},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.03.006},
doi = {10.1016/J.VLSI.2019.03.006},
timestamp = {Wed, 25 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DekimpeXSGFB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DuDL19,
author = {Ke Du and
St{\'{e}}phane Domas and
Michel Lenczner},
title = {Actors with stretchable access patterns},
journal = {Integr.},
volume = {66},
pages = {44--59},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.001},
doi = {10.1016/J.VLSI.2019.01.001},
timestamp = {Fri, 29 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DuDL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FatemiKLLG19,
author = {Hamed Fatemi and
Andrew B. Kahng and
Hyein Lee and
Jiajia Li and
Jos{\'{e}} Pineda de Gyvez},
title = {Enhancing sensitivity-based power reduction for an industry {IC} design
context},
journal = {Integr.},
volume = {66},
pages = {96--111},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.008},
doi = {10.1016/J.VLSI.2019.01.008},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FatemiKLLG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FengJYDL19,
author = {Xin Feng and
Youni Jiang and
Xuejiao Yang and
Ming Du and
Xin Li},
title = {Computer vision algorithms and hardware implementations: {A} survey},
journal = {Integr.},
volume = {69},
pages = {309--320},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.07.005},
doi = {10.1016/J.VLSI.2019.07.005},
timestamp = {Thu, 13 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FengJYDL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FlorosES19,
author = {George Floros and
Nestoras E. Evmorfopoulos and
Georgios I. Stamoulis},
title = {Efficient {IC} hotspot thermal analysis via low-rank Model Order Reduction},
journal = {Integr.},
volume = {66},
pages = {1--8},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.02.002},
doi = {10.1016/J.VLSI.2019.02.002},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FlorosES19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FuhrHLAE19,
author = {Gereon F{\"{u}}hr and
Ahmed Hallawa and
Rainer Leupers and
Gerd Ascheid and
Juan Fernando Eusse},
title = {Multi-objective optimisation of software application mappings on heterogeneous
MPSoCs: {TONPET} versus {R2-EMOA}},
journal = {Integr.},
volume = {69},
pages = {50--61},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.09.005},
doi = {10.1016/J.VLSI.2019.09.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FuhrHLAE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GadeRD19,
author = {Sri Harsha Gade and
Shobha Sundar Ram and
Sujay Deb},
title = {Millimeter wave wireless interconnects in deep submicron chips: Challenges
and opportunities},
journal = {Integr.},
volume = {64},
pages = {127--136},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.09.004},
doi = {10.1016/J.VLSI.2018.09.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GadeRD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GaoQZ19,
author = {Wei Gao and
Zhiliang Qian and
Pingqiang Zhou},
title = {Reliability- and performance-driven mapping for regular 3D NoCs using
a novel latency model and Simulated Allocation},
journal = {Integr.},
volume = {65},
pages = {351--361},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.04.012},
doi = {10.1016/J.VLSI.2018.04.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GaoQZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuoYLHLLZ19,
author = {Qingli Guo and
Jing Ye and
Bing Li and
Yu Hu and
Xiaowei Li and
Yazhu Lan and
Guohe Zhang},
title = {PUFPass: {A} password management mechanism based on software/hardware
codesign},
journal = {Integr.},
volume = {64},
pages = {173--183},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.003},
doi = {10.1016/J.VLSI.2018.10.003},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GuoYLHLLZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HarrisBE19,
author = {Barend Harris and
Inpyo Bae and
Bernhard Egger},
title = {Architectures and algorithms for on-device user customization of CNNs},
journal = {Integr.},
volume = {67},
pages = {121--133},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.001},
doi = {10.1016/J.VLSI.2018.11.001},
timestamp = {Sun, 05 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HarrisBE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HashimotoKFAW19,
author = {Masanori Hashimoto and
Kazutoshi Kobayashi and
Jun Furuta and
Shin{-}ichiro Abe and
Yukinobu Watanabe},
title = {Characterizing {SRAM} and {FF} soft error rates with measurement and
simulation},
journal = {Integr.},
volume = {69},
pages = {161--179},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.03.005},
doi = {10.1016/J.VLSI.2019.03.005},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HashimotoKFAW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HatiB19,
author = {Manas Kumar Hati and
Tarun Kanti Bhattacharyya},
title = {A constant loop bandwidth in delta sigma fractional-N {PLL} frequency
synthesizer with phase noise cancellation},
journal = {Integr.},
volume = {65},
pages = {175--188},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.12.003},
doi = {10.1016/J.VLSI.2018.12.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HatiB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HeGMDZJ19,
author = {Jiaji He and
Xiaolong Guo and
Travis Meade and
Raj Gautam Dutta and
Yiqiang Zhao and
Yier Jin},
title = {SoC interconnection protection through formal verification},
journal = {Integr.},
volume = {64},
pages = {143--151},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.09.007},
doi = {10.1016/J.VLSI.2018.09.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HeGMDZJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HemmatD19,
author = {Maedeh Hemmat and
Azadeh Davoodi},
title = {Power-efficient ReRAM-aware {CNN} model generation},
journal = {Integr.},
volume = {69},
pages = {369--380},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.08.003},
doi = {10.1016/J.VLSI.2019.08.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HemmatD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HuLYHQ19,
author = {Junjun Hu and
Zhijing Li and
Meng Yang and
Zixin Huang and
Weikang Qian},
title = {A high-accuracy approximate adder with correct sign calculation},
journal = {Integr.},
volume = {65},
pages = {370--388},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.09.003},
doi = {10.1016/J.VLSI.2017.09.003},
timestamp = {Tue, 18 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HuLYHQ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HuangXWC19,
author = {Jinglei Huang and
Xiaodong Xu and
Nan Wang and
Song Chen},
title = {Reconfigurable topology synthesis for application-specific NoC on
partially dynamically reconfigurable systems},
journal = {Integr.},
volume = {65},
pages = {331--343},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.02.012},
doi = {10.1016/J.VLSI.2018.02.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HuangXWC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JaiswalS19,
author = {Manish Kumar Jaiswal and
Hayden Kwok{-}Hay So},
title = {Design of quadruple precision multiplier architectures with {SIMD}
single and double precision support},
journal = {Integr.},
volume = {65},
pages = {163--174},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.12.002},
doi = {10.1016/J.VLSI.2018.12.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JaiswalS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JiangWCZWEH19,
author = {Shuyan Jiang and
Qiong Wu and
Shuyu Chen and
Junkai Zhan and
Junshi Wang and
Masoumeh Ebrahimi and
Letian Huang},
title = {Testing aware dynamic mapping for path-centric network-on-chip test},
journal = {Integr.},
volume = {67},
pages = {134--143},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.009},
doi = {10.1016/J.VLSI.2018.11.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JiangWCZWEH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JosephBHSPO19,
author = {Jan Moritz Joseph and
Lennart Bamberg and
Imad Hajjar and
Robert Schmidt and
Thilo Pionteck and
Alberto Garc{\'{\i}}a Ortiz},
title = {Simulation environment for link energy estimation in networks-on-chip
with virtual channels},
journal = {Integr.},
volume = {68},
pages = {147--156},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.05.005},
doi = {10.1016/J.VLSI.2019.05.005},
timestamp = {Thu, 16 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/JosephBHSPO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KabirpourJ19,
author = {Saeideh Kabirpour and
Mohsen Jalali},
title = {A highly linear current-starved {VCO} based on a linearized current
control mechanism},
journal = {Integr.},
volume = {69},
pages = {1--9},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.008},
doi = {10.1016/J.VLSI.2019.06.008},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KabirpourJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KadeedTKE19,
author = {Thawra Kadeed and
Sebastian Tobuschat and
Adam Kostrzewa and
Rolf Ernst},
title = {Safe and efficient power management of hard real-time networks-on-chip},
journal = {Integr.},
volume = {65},
pages = {1--17},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.007},
doi = {10.1016/J.VLSI.2018.10.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KadeedTKE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KanikaPCG19,
author = {Kanika and
R. Sankara Prasad and
Nitin Chaturvedi and
S. Gurunarayanan},
title = {A low power high speed {MTJ} based non-volatile {SRAM} cell for energy
harvesting based IoT applications},
journal = {Integr.},
volume = {65},
pages = {43--50},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.002},
doi = {10.1016/J.VLSI.2018.11.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KanikaPCG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KapouleaPE19,
author = {Stavroula Kapoulea and
Costas Psychalinos and
Ahmed S. Elwakil},
title = {Realizations of simple fractional-order capacitor emulators with electronically-tunable
capacitance},
journal = {Integr.},
volume = {69},
pages = {225--233},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.04.004},
doi = {10.1016/J.VLSI.2019.04.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KapouleaPE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Kazeminia19,
author = {Sarang Kazeminia},
title = {A real-time pseudo-background gain calibration strategy for residue
amplifiers of pipeline ADCs},
journal = {Integr.},
volume = {65},
pages = {51--73},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.003},
doi = {10.1016/J.VLSI.2018.11.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Kazeminia19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KefalasT19,
author = {Nikolaos Kefalas and
George Theodoridis},
title = {Low-memory and high-performance architectures for the {CCSDS} 122.0-B-1
compression standard},
journal = {Integr.},
volume = {69},
pages = {85--97},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.03.004},
doi = {10.1016/J.VLSI.2018.03.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KefalasT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhadeVS19,
author = {Amitkumar S. Khade and
Vibha S. Vyas and
Mukul S. Sutaone},
title = {Performance enhancement of advanced recycling folded cascode operational
transconductance amplifier using an unbalanced biased input stage},
journal = {Integr.},
volume = {69},
pages = {242--250},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.04.007},
doi = {10.1016/J.VLSI.2019.04.007},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KhadeVS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhoramiSSS19,
author = {Ata Khorami and
Roghayeh Saeidi and
Manoj Sachdev and
Mohammad Sharifkhani},
title = {A low-power dynamic comparator for low-offset applications},
journal = {Integr.},
volume = {69},
pages = {23--30},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.07.001},
doi = {10.1016/J.VLSI.2019.07.001},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KhoramiSSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KrishnaMM19,
author = {R. S. S. M. R. Krishna and
Ashis Kumar Mal and
Rajat Mahapatra},
title = {All {MOS} noise-shaped time-mode temperature sensor},
journal = {Integr.},
volume = {65},
pages = {74--80},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.004},
doi = {10.1016/J.VLSI.2018.11.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KrishnaMM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarB19,
author = {Chaudhry Indra Kumar and
Anand Bulusu},
title = {High performance energy efficient radiation hardened latch for low
voltage applications},
journal = {Integr.},
volume = {66},
pages = {119--127},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.02.004},
doi = {10.1016/J.VLSI.2019.02.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KumarB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarR19,
author = {Puneeth Kumar and
S. Rekha},
title = {Fast start crystal oscillator design with negative resistance control},
journal = {Integr.},
volume = {65},
pages = {138--148},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.012},
doi = {10.1016/J.VLSI.2018.11.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KumarR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LeeDP19,
author = {Dongjin Lee and
Sourav Das and
Partha Pratim Pande},
title = {Analyzing power-thermal-performance trade-offs in a high-performance
3D NoC architecture},
journal = {Integr.},
volume = {65},
pages = {282--292},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.12.002},
doi = {10.1016/J.VLSI.2017.12.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LeeDP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiLYZC19,
author = {Yan Li and
Zhiwei Li and
Chen Yang and
Wei Zhong and
Song Chen},
title = {High throughput hardware architecture for accurate semi-global matching},
journal = {Integr.},
volume = {65},
pages = {417--427},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.12.007},
doi = {10.1016/J.VLSI.2017.12.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiLYZC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiXLZZS19,
author = {Dawei Li and
Xiaowei Xu and
Leibo Liu and
Li Zhang and
Cheng Zhuo and
Yiyu Shi},
title = {Optimal design of a low-power, phase-switching modulator for implantable
medical applications},
journal = {Integr.},
volume = {69},
pages = {289--300},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.02.003},
doi = {10.1016/J.VLSI.2019.02.003},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiXLZZS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiYLRDDNQYW19,
author = {Ji Li and
Zihao Yuan and
Zhe Li and
Ao Ren and
Caiwen Ding and
Jeffrey Draper and
Shahin Nazarian and
Qinru Qiu and
Bo Yuan and
Yanzhi Wang},
title = {Normalization and dropout for stochastic computing-based deep convolutional
neural networks},
journal = {Integr.},
volume = {65},
pages = {395--403},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.11.002},
doi = {10.1016/J.VLSI.2017.11.002},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiYLRDDNQYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Lomeli-Illescas19,
author = {Ismael Lomeli{-}Illescas and
Sergio A. Solis{-}Bustos and
Jos{\'{e}} Ernesto Rayas{-}S{\'{a}}nchez},
title = {A tool for the automatic generation and analysis of regular analog
layout modules},
journal = {Integr.},
volume = {65},
pages = {81--87},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.005},
doi = {10.1016/J.VLSI.2018.11.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Lomeli-Illescas19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MahapatraS19,
author = {Anushree Mahapatra and
Benjamin Carri{\'{o}}n Sch{\"{a}}fer},
title = {\emph{VeriIntel2C}: Abstracting {RTL} to {C} to maximize High-Level
Synthesis Design Space Exploration},
journal = {Integr.},
volume = {64},
pages = {1--12},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.03.011},
doi = {10.1016/J.VLSI.2018.03.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MahapatraS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MahendraHMD19,
author = {Telajala Venkata Mahendra and
Sheikh Wasmir Hussain and
Sandeep Mishra and
Anup Dandapat},
title = {Low discharge precharge free matchline structure for energy-efficient
search using {CAM}},
journal = {Integr.},
volume = {69},
pages = {31--39},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.08.002},
doi = {10.1016/J.VLSI.2019.08.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MahendraHMD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaheshwariBK19,
author = {Sachin Maheshwari and
Vivian A. Bartlett and
Izzet Kale},
title = {Modelling, simulation and verification of 4-phase adiabatic logic
design: {A} VHDL-Based approach},
journal = {Integr.},
volume = {67},
pages = {144--154},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.007},
doi = {10.1016/J.VLSI.2019.01.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MaheshwariBK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MahmoudiTD19,
author = {Azad Mahmoudi and
Pooya Torkzadeh and
Massoud Dousti},
title = {A study of analog decision feedback equalization for ADC-Based serial
link receivers},
journal = {Integr.},
volume = {64},
pages = {114--126},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.09.003},
doi = {10.1016/J.VLSI.2018.09.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MahmoudiTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MatamAA19,
author = {Kiran Kumar Matam and
Mohammad Abdel{-}Majeed and
Murali Annavaram},
title = {Efficient automatic parallelization of a single {GPU} program for
a multiple {GPU} system},
journal = {Integr.},
volume = {66},
pages = {35--43},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.12.006},
doi = {10.1016/J.VLSI.2018.12.006},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MatamAA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MatoussiP19,
author = {Omayma Matoussi and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot},
title = {Loop aware {CFG} matching strategy for accurate performance estimation
in IR-level native simulation},
journal = {Integr.},
volume = {65},
pages = {444--454},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.02.001},
doi = {10.1016/J.VLSI.2018.02.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MatoussiP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MatsuiT19,
author = {Chihiro Matsui and
Ken Takeuchi},
title = {Step-by-Step Design of memory hierarchy for heterogeneously-integrated
{SCM/NAND} flash storage},
journal = {Integr.},
volume = {69},
pages = {62--74},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.09.006},
doi = {10.1016/J.VLSI.2019.09.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MatsuiT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MewadaZT19,
author = {Manan Mewada and
Mazad Zaveri and
Rajesh Amratlal Thakker},
title = {Improving the performance of transmission gate and hybrid {CMOS} Full
Adders in chain and tree structure architectures},
journal = {Integr.},
volume = {69},
pages = {381--392},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.09.002},
doi = {10.1016/J.VLSI.2019.09.002},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MewadaZT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MispanDHZ19,
author = {Mohd Syafiq Mispan and
Shengyu Duan and
Basel Halak and
Mark Zwolinski},
title = {A reliable {PUF} in a dual function {SRAM}},
journal = {Integr.},
volume = {68},
pages = {12--21},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.001},
doi = {10.1016/J.VLSI.2019.06.001},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MispanDHZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MondalMR19,
author = {Sabir Ali Mondal and
Pradip Mandal and
Hafizur Rahaman},
title = {Fast locking, startup-circuit free, low area, 32-phase analog {DLL}},
journal = {Integr.},
volume = {66},
pages = {60--66},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.003},
doi = {10.1016/J.VLSI.2019.01.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MondalMR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MoradiFS19,
author = {Rasoul Moradi and
Ebrahim Farshidi and
Mohammad Soroosh},
title = {A low power passive-active {\(\Delta\)}{\(\Sigma\)} modulator with
high-resolution employing an integrator with open-loop unity-gain
buffer},
journal = {Integr.},
volume = {64},
pages = {137--142},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.09.006},
doi = {10.1016/J.VLSI.2018.09.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MoradiFS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MorgulA19,
author = {Muhammed Ceylan Morg{\"{u}}l and
Mustafa Altun},
title = {Optimal and heuristic algorithms to synthesize lattices of four-terminal
switches},
journal = {Integr.},
volume = {64},
pages = {60--70},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.08.002},
doi = {10.1016/J.VLSI.2018.08.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MorgulA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MottaAAM19,
author = {Lucas Lui Motta and
Byron Alejandro Acu{\~{n}}a Acurio and
Nath{\'{a}}lia Figueiredo Tinoco Aniceto and
Lu{\'{\i}}s Geraldo P. Meloni},
title = {Design and implementation of a digital down/up conversion directly
from/to {RF} channels in {HDL}},
journal = {Integr.},
volume = {68},
pages = {30--37},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.05.006},
doi = {10.1016/J.VLSI.2019.05.006},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MottaAAM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MozafariM19,
author = {Seyyed Hasan Mozafari and
Brett H. Meyer},
title = {Characterizing the Effectiveness of Hot Sparing on Cost and Performance-per-Watt
in Application Specific {SIMT}},
journal = {Integr.},
volume = {69},
pages = {198--209},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.03.010},
doi = {10.1016/J.VLSI.2019.03.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MozafariM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NafeaDEEIM19,
author = {Sherif F. Nafea and
Ahmed A. S. Dessouki and
S. El{-}Rabaie and
Basem E. Elnaghi and
Yehea Ismail and
Hassan Mostafa},
title = {An accurate model of domain-wall-based spintronic memristor},
journal = {Integr.},
volume = {65},
pages = {149--162},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.12.001},
doi = {10.1016/J.VLSI.2018.12.001},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/NafeaDEEIM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NawazBLSF19,
author = {Kashif Nawaz and
L{\'{e}}opold Van Brandt and
Itamar Levi and
Fran{\c{c}}ois{-}Xavier Standaert and
Denis Flandre},
title = {A security oriented transient-noise simulation methodology: Evaluation
of intrinsic physical noise of cryptographic designs},
journal = {Integr.},
volume = {68},
pages = {71--79},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.006},
doi = {10.1016/J.VLSI.2019.06.006},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NawazBLSF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NguyenL19,
author = {Tram Thi Bao Nguyen and
Hanho Lee},
title = {Low-complexity multi-mode multi-way split-row layered {LDPC} decoder
for gigabit wireless communications},
journal = {Integr.},
volume = {65},
pages = {189--200},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.12.004},
doi = {10.1016/J.VLSI.2018.12.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NguyenL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NiksereshtA19,
author = {Sasan Nikseresht and
Seyed Javad Azhari},
title = {A new current-mode computational analog block free from the body-effect},
journal = {Integr.},
volume = {65},
pages = {18--31},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.008},
doi = {10.1016/J.VLSI.2018.10.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NiksereshtA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NoltsisMRCS19,
author = {Michail Noltsis and
Eleni Maragkoudaki and
Dimitrios Rodopoulos and
Francky Catthoor and
Dimitrios Soudris},
title = {Failure probability of a FinFET-based {SRAM} cell utilizing the most
probable failure point},
journal = {Integr.},
volume = {69},
pages = {111--119},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.03.016},
doi = {10.1016/J.VLSI.2018.03.016},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NoltsisMRCS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OrieroH19,
author = {Enahoro Oriero and
Syed Rafay Hasan},
title = {Survey on recent counterfeit {IC} detection techniques and future
research directions},
journal = {Integr.},
volume = {66},
pages = {135--152},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.02.006},
doi = {10.1016/J.VLSI.2019.02.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/OrieroH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OuyangLLSLD19,
author = {Yiming Ouyang and
Zhe Li and
Jianhua Li and
Chenglong Sun and
Huaguo Liang and
Gaoming Du},
title = {{CPCA:} An efficient wireless routing algorithm in WiNoC for cross
path congestion awareness},
journal = {Integr.},
volume = {69},
pages = {75--84},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.03.008},
doi = {10.1016/J.VLSI.2019.03.008},
timestamp = {Wed, 10 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/OuyangLLSLD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ParkK19,
author = {Heechun Park and
Taewhan Kim},
title = {Hybrid asynchronous circuit generation amenable to conventional {EDA}
flow},
journal = {Integr.},
volume = {64},
pages = {29--39},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.07.006},
doi = {10.1016/J.VLSI.2018.07.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ParkK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PekcokgulerDD19,
author = {Naci Pekcokguler and
G{\"{u}}nhan D{\"{u}}ndar and
Catherine Dehollain},
title = {Analysis, modeling and design of a {CMOS} Super-Regenerative Receiver
for implanted medical devices under square and sinusoidal quench signals},
journal = {Integr.},
volume = {67},
pages = {1--7},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.03.003},
doi = {10.1016/J.VLSI.2019.03.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PekcokgulerDD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/QuLCZWLL19,
author = {Xiongfei Qu and
Ruifeng Liu and
Lingling Cao and
Yuanzhi Zhang and
Wenshen Wang and
Huimin Liu and
Chao Lu},
title = {A 5.8{\unicode{8239}}GHz digitally configurable {DSRC} RF-SoC transmitter
for China {ETC} systems},
journal = {Integr.},
volume = {68},
pages = {99--107},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.010},
doi = {10.1016/J.VLSI.2019.06.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/QuLCZWLL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RaghavK19,
author = {Himadri Singh Raghav and
Izzet Kale},
title = {A balanced power analysis attack resilient adiabatic logic using single
charge sharing transistor},
journal = {Integr.},
volume = {69},
pages = {147--160},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.07.010},
doi = {10.1016/J.VLSI.2018.07.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RaghavK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RagniSSFP19,
author = {Andrea Ragni and
Giuseppe Sciortino and
Marco Sampietro and
Giorgio Ferrari and
Dario Polli},
title = {Multi-channel lock-in based differential front-end for broadband Raman
spectroscopy},
journal = {Integr.},
volume = {67},
pages = {44--49},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.03.001},
doi = {10.1016/J.VLSI.2019.03.001},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RagniSSFP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RamosMMP19,
author = {Filipe Guimar{\~{a}}es Russo Ramos and
Thiago P. Mussolini and
Robson Luiz Moreno and
Tales Cleber Pimenta},
title = {A {CMOS} temperature-independent current reference optimized for mixed-signal
applications},
journal = {Integr.},
volume = {66},
pages = {88--95},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.006},
doi = {10.1016/J.VLSI.2019.01.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RamosMMP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RoseRL19,
author = {Raffaele De Rose and
Paul Romero and
Marco Lanuzza},
title = {Double-precision Dual Mode Logic carry-save multiplier},
journal = {Integr.},
volume = {64},
pages = {71--77},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.08.003},
doi = {10.1016/J.VLSI.2018.08.003},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RoseRL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RoyC19,
author = {Subhabrata Roy and
Abhijit Chandra},
title = {Design of Narrow Transition Band Digital Filter: An Analytical Approach},
journal = {Integr.},
volume = {68},
pages = {38--49},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.002},
doi = {10.1016/J.VLSI.2019.06.002},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RoyC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SadeghifarBWG19,
author = {M. Reza Sadeghifar and
H{\aa}kan Bengtsson and
J. Jacob Wikner and
Oscar Gustafsson},
title = {Direct digital-to-RF converter employing semi-digital {FIR} voltage-mode
{RF} {DAC}},
journal = {Integr.},
volume = {66},
pages = {128--134},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.02.005},
doi = {10.1016/J.VLSI.2019.02.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SadeghifarBWG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SahooNVK19,
author = {Siva Satyendra Sahoo and
Tuan D. A. Nguyen and
Bharadwaj Veeravalli and
Akash Kumar},
title = {Multi-objective design space exploration for system partitioning of
FPGA-based Dynamic Partially Reconfigurable Systems},
journal = {Integr.},
volume = {67},
pages = {95--107},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.006},
doi = {10.1016/J.VLSI.2018.10.006},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SahooNVK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SalehiKZD19,
author = {Soheil Salehi and
Navid Khoshavi and
Ramtin Zand and
Ronald F. DeMara},
title = {Self-Organized Sub-bank SHE-MRAM-based {LLC:} An energy-efficient
and variation-immune read and write architecture},
journal = {Integr.},
volume = {65},
pages = {293--307},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.03.001},
doi = {10.1016/J.VLSI.2018.03.001},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SalehiKZD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SaririTS19,
author = {Hossein Sariri and
Pooya Torkzadeh and
Sirus Sadughi},
title = {A novel design of hybrid-time-interleaved current steering digital
to analog converter and its behavioral simulation considering non-ideal
effects},
journal = {Integr.},
volume = {69},
pages = {321--334},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.07.004},
doi = {10.1016/J.VLSI.2019.07.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SaririTS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SavithaR19,
author = {M. Savitha and
R. Venkat Siva Reddy},
title = {Dual split-three segment capacitor array Design Based Successive approximation
{ADC} for Io-T ecosystem},
journal = {Integr.},
volume = {69},
pages = {279--288},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.05.004},
doi = {10.1016/J.VLSI.2019.05.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SavithaR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Scanlan19,
author = {Anthony G. Scanlan},
title = {Low power {\&} mobile hardware accelerators for deep convolutional
neural networks},
journal = {Integr.},
volume = {65},
pages = {110--127},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.010},
doi = {10.1016/J.VLSI.2018.11.010},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Scanlan19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ScerriGGC19,
author = {Jeremy Scerri and
Ivan Grech and
Edward Gatt and
Owen Casha},
title = {Dimensional optimisation of a {MEMS} {BPSK} to {ASK} converter in
SOIMUMPs},
journal = {Integr.},
volume = {67},
pages = {19--32},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.03.002},
doi = {10.1016/J.VLSI.2019.03.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ScerriGGC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SchneiderW19,
author = {Eric Schneider and
Hans{-}Joachim Wunderlich},
title = {Multi-level timing and fault simulation on GPUs},
journal = {Integr.},
volume = {64},
pages = {78--91},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.08.005},
doi = {10.1016/J.VLSI.2018.08.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SchneiderW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SeoPK19,
author = {Young{-}Ho Seo and
Sung{-}Ho Park and
Dong{-}Wook Kim},
title = {High-level hardware design of digital comparator with multiple inputs},
journal = {Integr.},
volume = {68},
pages = {157--165},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.04.003},
doi = {10.1016/J.VLSI.2019.04.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SeoPK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShihC19,
author = {Xin{-}Yu Shih and
Hong{-}Ru Chou},
title = {Flexible design and implementation of QC-Based {LDPC} decoder architecture
for on-line user-defined matrix downloading and efficient decoding},
journal = {Integr.},
volume = {64},
pages = {40--49},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.07.008},
doi = {10.1016/J.VLSI.2018.07.008},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ShihC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShiomiIO19,
author = {Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Area-efficient fully digital memory using minimum height standard
cells for near-threshold voltage computing},
journal = {Integr.},
volume = {65},
pages = {201--210},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.07.001},
doi = {10.1016/J.VLSI.2017.07.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShiomiIO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Shirmohammadi19,
author = {Zahra Shirmohammadi},
title = {OP-Fibo: An efficient Forbidden Pattern Free {CAC} design},
journal = {Integr.},
volume = {65},
pages = {104--109},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.008},
doi = {10.1016/J.VLSI.2018.11.008},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Shirmohammadi19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShiroeiAF19,
author = {Masoud Shiroei and
Bijan Alizadeh and
Masahiro Fujita},
title = {Data-path aware high-level {ECO} synthesis},
journal = {Integr.},
volume = {65},
pages = {88--96},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.11.006},
doi = {10.1016/J.VLSI.2018.11.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShiroeiAF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SierraCC19,
author = {Roberto Sierra and
Carlos Carreras and
Gabriel Caffarena},
title = {Witelo: Automated generation and timing characterization of distributed-control
macroblocks for high-performance {FPGA} designs},
journal = {Integr.},
volume = {68},
pages = {1--11},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.05.001},
doi = {10.1016/J.VLSI.2019.05.001},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SierraCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SinghTG19,
author = {Kunwar Singh and
Satish Chandra Tiwari and
Maneesha Gupta},
title = {A closed-loop {ASIC} design approach based on logical effort theory
and artificial neural networks},
journal = {Integr.},
volume = {69},
pages = {10--22},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.07.006},
doi = {10.1016/J.VLSI.2019.07.006},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SinghTG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SolimanJAHAASM19,
author = {Shady M. Soliman and
Mohammed A. Jaela and
Abdelrhman M. Abotaleb and
Youssef Hassan and
Mohamed Abdelghany and
Amr T. Abdel{-}Hamid and
Khaled N. Salama and
Hassan Mostafa},
title = {{FPGA} implementation of dynamically reconfigurable IoT security module
using algorithm hopping},
journal = {Integr.},
volume = {68},
pages = {108--121},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.004},
doi = {10.1016/J.VLSI.2019.06.004},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SolimanJAHAASM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/StamelakosXPS19,
author = {Ioannis S. Stamelakos and
Sotirios Xydis and
Gianluca Palermo and
Cristina Silvano},
title = {Workload- and process-variation aware voltage/frequency tuning for
energy efficient performance sustainability of {NTC} manycores},
journal = {Integr.},
volume = {65},
pages = {252--262},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.02.013},
doi = {10.1016/J.VLSI.2018.02.013},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/StamelakosXPS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/StillmakerB19,
author = {Aaron Stillmaker and
Bevan M. Baas},
title = {Corrigendum to "Scaling equations for the accurate prediction of {CMOS}
device performance from 180{\unicode{8239}}nm to 7{\unicode{8239}}nm"
[Integr. {VLSI} J. 58. {(2017)} 74-81]},
journal = {Integr.},
volume = {67},
pages = {170},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.04.006},
doi = {10.1016/J.VLSI.2019.04.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/StillmakerB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TarighatY19,
author = {Asieh Parhizkar Tarighat and
Mostafa Yargholi},
title = {Low power active shunt feedback {CMOS} low noise amplifier for wideband
wireless systems},
journal = {Integr.},
volume = {69},
pages = {189--197},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.04.001},
doi = {10.1016/J.VLSI.2019.04.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TarighatY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ThiLP19,
author = {Huyen Pham Thi and
Hanho Lee and
Xuan Nghia Pham},
title = {Half-row modified two-extra-column trellis min-max decoder architecture
for nonbinary {LDPC} codes},
journal = {Integr.},
volume = {69},
pages = {234--241},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.04.005},
doi = {10.1016/J.VLSI.2019.04.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ThiLP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ToanTL19,
author = {Nguyen Van Toan and
Dam Minh Tung and
Jeong{-}Gun Lee},
title = {A {GALS} design based on multi-frequency clocking for digital switching
noise reduction},
journal = {Integr.},
volume = {69},
pages = {210--224},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.04.002},
doi = {10.1016/J.VLSI.2019.04.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ToanTL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TobuschatKE19,
author = {Sebastian Tobuschat and
Adam Kostrzewa and
Rolf Ernst},
title = {Selective congestion control for mixed-critical networks-on-chip},
journal = {Integr.},
volume = {65},
pages = {404--416},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.12.003},
doi = {10.1016/J.VLSI.2017.12.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TobuschatKE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TurkSVJV19,
author = {Semih Turk and
Alexander Schug and
Reinhard Viga and
Andreas Jupe and
Holger Vogt},
title = {Optimization of the dielectric layer for electrowetting on dielectric},
journal = {Integr.},
volume = {67},
pages = {50--59},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.03.004},
doi = {10.1016/J.VLSI.2019.03.004},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TurkSVJV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VeiranoNS19,
author = {Francisco Veirano and
Lirida A. B. Naviner and
Fernando Silveira},
title = {Optimal asymmetrical back plane biasing for energy efficient digital
circuits in 28 nm {UTBB} {FD-SOI}},
journal = {Integr.},
volume = {65},
pages = {211--218},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.08.008},
doi = {10.1016/J.VLSI.2017.08.008},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/VeiranoNS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangCMLZ19,
author = {Nan Wang and
Song Chen and
Zhiyuan Ma and
Xiaofeng Ling and
Yu Zhu},
title = {Integrating operation scheduling and binding for functional unit power-gating
in high-level synthesis},
journal = {Integr.},
volume = {65},
pages = {308--321},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.11.008},
doi = {10.1016/J.VLSI.2017.11.008},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangCMLZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangGW19,
author = {Tengfei Wang and
Wei Guo and
Jizeng Wei},
title = {Highly-parallel hardware implementation of optimal ate pairing over
Barreto-Naehrig curves},
journal = {Integr.},
volume = {64},
pages = {13--21},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.04.013},
doi = {10.1016/J.VLSI.2018.04.013},
timestamp = {Wed, 25 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangGW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangJCWH19,
author = {Lihuan Wang and
Shuyan Jiang and
Shuyu Chen and
Junshi Wang and
Letian Huang},
title = {Optimized mapping algorithm to extend lifetime of both NoC and cores
in many-core system},
journal = {Integr.},
volume = {67},
pages = {82--94},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.005},
doi = {10.1016/J.VLSI.2018.10.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangJCWH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangJW19,
author = {Zhen Wang and
Jianhui Jiang and
Tao Wang},
title = {Failure probability analysis and critical node determination for approximate
circuits},
journal = {Integr.},
volume = {68},
pages = {122--128},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.05.008},
doi = {10.1016/J.VLSI.2019.05.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangJW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangWCZ19,
author = {Haoyi Wang and
Chenguang Wang and
Yici Cai and
Qiang Zhou},
title = {A high-level information flow tracking method for detecting information
leakage},
journal = {Integr.},
volume = {69},
pages = {393--399},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.08.001},
doi = {10.1016/J.VLSI.2019.08.001},
timestamp = {Thu, 06 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangWCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangYL19,
author = {Sying{-}Jyan Wang and
Kuan{-}Ting Yeh and
Katherine Shu{-}Min Li},
title = {Exploiting distribution of unknown values in test responses to optimize
test output compactors},
journal = {Integr.},
volume = {65},
pages = {389--394},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.12.008},
doi = {10.1016/J.VLSI.2017.12.008},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangYL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangZCQ19,
author = {Xueyan Wang and
Qiang Zhou and
Yici Cai and
Gang Qu},
title = {Parallelizing SAT-based de-camouflaging attacks by circuit partitioning
and conflict avoiding},
journal = {Integr.},
volume = {67},
pages = {108--120},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.009},
doi = {10.1016/J.VLSI.2018.10.009},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangZCQ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangZZ19,
author = {Leilei Wang and
Cheng Zhuo and
Pingqiang Zhou},
title = {Run-time demand estimation and modulation of on-chip decaps at system
level for leakage power reduction in multicore chips},
journal = {Integr.},
volume = {65},
pages = {322--330},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.01.009},
doi = {10.1016/J.VLSI.2018.01.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangZZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WeiCLXZWYD19,
author = {Baolin Wei and
Tian Chen and
Chao Lu and
Weilin Xu and
Yuanzhi Zhang and
Xueming Wei and
Hongwei Yue and
Jihai Duan},
title = {An all-digital frequency tunable {IR-UWB} transmitter with an approximate
15th derivative Gaussian pulse generator},
journal = {Integr.},
volume = {69},
pages = {301--308},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.07.002},
doi = {10.1016/J.VLSI.2019.07.002},
timestamp = {Sun, 26 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WeiCLXZWYD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WeiYLHYY19,
author = {Xing Wei and
Haigang Yang and
Wei Li and
Zhihong Huang and
Tao Yin and
Le Yu},
title = {A reconfigurable 4-GS/s power-efficient floating-point {FFT} processor
design and implementation based on single-sided binary-tree decomposition},
journal = {Integr.},
volume = {66},
pages = {164--172},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.02.008},
doi = {10.1016/J.VLSI.2019.02.008},
timestamp = {Tue, 02 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WeiYLHYY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WeissbrichGBNOV19,
author = {Moritz Wei{\ss}brich and
Lukas Gerlach and
Holger Blume and
Ardalan Najafi and
Alberto Garc{\'{\i}}a Ortiz and
Guillermo Pay{\'{a}} Vay{\'{a}}},
title = {{FLINT+:} {A} runtime-configurable emulation-based stochastic timing
analysis framework},
journal = {Integr.},
volume = {69},
pages = {120--137},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.002},
doi = {10.1016/J.VLSI.2019.01.002},
timestamp = {Tue, 01 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WeissbrichGBNOV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WenZZLW19,
author = {Boran Wen and
Qisheng Zhang and
Xiao Zhao and
Xiaolong Lv and
Yongqing Wang},
title = {Trade-offs among power consumption and other design parameters of
two-stage recycling folded cascode {OTA} that using embedded cascode
current buffer compensation technology},
journal = {Integr.},
volume = {68},
pages = {62--70},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.06.009},
doi = {10.1016/J.VLSI.2019.06.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WenZZLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WheeldonMSY19,
author = {Adrian Wheeldon and
Jordan Morris and
Danil Sokolov and
Alex Yakovlev},
title = {Self-timed, minimum latency circuits for the internet of things},
journal = {Integr.},
volume = {69},
pages = {138--146},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.013},
doi = {10.1016/J.VLSI.2019.01.013},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WheeldonMSY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WisniewskiBS19,
author = {Remigiusz Wisniewski and
Grzegorz Bazydlo and
Pawel Szczesniak},
title = {{SVM} algorithm oriented for implementation in a low-cost Xilinx {FPGA}},
journal = {Integr.},
volume = {64},
pages = {163--172},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.002},
doi = {10.1016/J.VLSI.2018.10.002},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WisniewskiBS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuH19,
author = {Jiming Xu and
Howard M. Heys},
title = {Kernel-based template attacks of cryptographic circuits using static
power},
journal = {Integr.},
volume = {66},
pages = {67--79},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.01.004},
doi = {10.1016/J.VLSI.2019.01.004},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/XuH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuMGMT19,
author = {Hesong Xu and
Nicola Massari and
Leonardo Gasparini and
Alessio Meneghetti and
Alessandro Tomasi},
title = {A SPAD-based random number generator pixel based on the arrival time
of photons},
journal = {Integr.},
volume = {64},
pages = {22--28},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.05.009},
doi = {10.1016/J.VLSI.2018.05.009},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/XuMGMT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuP19,
author = {Teng Xu and
Miodrag Potkonjak},
title = {Circuit power optimization using pipelining and dual-supply voltage
assignment},
journal = {Integr.},
volume = {65},
pages = {241--251},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.12.011},
doi = {10.1016/J.VLSI.2017.12.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/XuP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YadavTD19,
author = {Dev Narayan Yadav and
Phrangboklang Lyngton Thangkhiew and
Kamalika Datta},
title = {Look-ahead mapping of Boolean functions in memristive crossbar array},
journal = {Integr.},
volume = {64},
pages = {152--162},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.001},
doi = {10.1016/J.VLSI.2018.10.001},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YadavTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangABJ19,
author = {Xiaohan Yang and
Adedotun Adeyemo and
Anu Bala and
Abusaleh M. Jabir},
title = {Novel techniques for memristive multifunction logic design},
journal = {Integr.},
volume = {65},
pages = {219--230},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.09.005},
doi = {10.1016/J.VLSI.2017.09.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YangABJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YeZ19,
author = {Yaoyao Ye and
Zhe Zhang},
title = {A thermal-sensitive design of a 3D torus-based optical NoC architecture},
journal = {Integr.},
volume = {68},
pages = {22--29},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.05.007},
doi = {10.1016/J.VLSI.2019.05.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YeZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZamanSCM19,
author = {Monir Zaman and
Mustafa M. Shihab and
Ayse K. Coskun and
Yiorgos Makris},
title = {{CAPE:} {A} cross-layer framework for accurate microprocessor power
estimation},
journal = {Integr.},
volume = {68},
pages = {87--98},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.05.002},
doi = {10.1016/J.VLSI.2019.05.002},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZamanSCM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangKFMJ19,
author = {Jiangwei Zhang and
Donald Kline Jr. and
Liang Fang and
Rami G. Melhem and
Alex K. Jones},
title = {Yielding optimized dependability assurance through bit inversion},
journal = {Integr.},
volume = {64},
pages = {105--113},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.09.002},
doi = {10.1016/J.VLSI.2018.09.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangKFMJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhuoC19,
author = {Cheng Zhuo and
Baixin Chen},
title = {System-level design consideration and optimization of through-silicon-via
inductor},
journal = {Integr.},
volume = {65},
pages = {362--369},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.07.002},
doi = {10.1016/J.VLSI.2017.07.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhuoC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AbbasR18,
author = {Mohamed Abbas and
Ashraf Ramadan},
title = {Low-cost methodology for fault diagnosis and localization in pipelined
ADCs},
journal = {Integr.},
volume = {63},
pages = {64--73},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.007},
doi = {10.1016/J.VLSI.2018.05.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AbbasR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Abdel-MajeedD18,
author = {Mohammad Abdel{-}Majeed and
Waleed Dweik},
title = {Low overhead online periodic testing for GPGPUs},
journal = {Integr.},
volume = {62},
pages = {362--370},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.015},
doi = {10.1016/J.VLSI.2018.04.015},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Abdel-MajeedD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Aguilera-Galicia18,
author = {Cuauht{\'{e}}moc R. Aguilera{-}Galicia and
Omar Longoria{-}Gandara and
Luis Pizano{-}Escalante and
Javier V{\'{a}}zquez Castillo and
Manuel Salim Maza},
title = {On-chip implementation of a low-latency bit-accurate reciprocal square
root unit},
journal = {Integr.},
volume = {63},
pages = {9--17},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.016},
doi = {10.1016/J.VLSI.2018.04.016},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Aguilera-Galicia18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Ahmadi-FarsaniS18,
author = {J. Ahmadi{-}Farsani and
Hamed Sadjedi and
M. B. Ghaznavi{-}Ghoushchi},
title = {An ultra low-power current-mode clock and data recovery design with
input bit-rate adaptability for biomedical applications in {CMOS}
90{\unicode{8239}}nm},
journal = {Integr.},
volume = {62},
pages = {238--245},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.007},
doi = {10.1016/J.VLSI.2018.03.007},
timestamp = {Mon, 06 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Ahmadi-FarsaniS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AhmedVS18,
author = {Syed Ershad Ahmed and
Ch. Santosh Varma and
M. B. Srinivas},
title = {Improved designs of digit-by-digit decimal multiplier},
journal = {Integr.},
volume = {61},
pages = {150--159},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.12.001},
doi = {10.1016/J.VLSI.2017.12.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AhmedVS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AhyouneSCVLRF18,
author = {Saiyd Ahyoune and
Javier J. Sieiro and
Tom{\'{a}}s Carrasco Carrillo and
Neus Vidal and
Jos{\'{e}} Mar{\'{\i}}a L{\'{o}}pez{-}Villegas and
Elisenda Roca and
Francisco V. Fern{\'{a}}ndez},
title = {Quasi-static {PEEC} planar solver using a weighted combination of
2D and 3D analytical Green's functions and a predictive meshing generator},
journal = {Integr.},
volume = {63},
pages = {332--341},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.006},
doi = {10.1016/J.VLSI.2018.02.006},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AhyouneSCVLRF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ArastehMTNB18,
author = {Armineh Arasteh and
Mohammad Hossein Moaiyeri and
MohammadReza Taheri and
Keivan Navi and
Nader Bagherzadeh},
title = {An energy and area efficient 4: 2 compressor based on FinFETs},
journal = {Integr.},
volume = {60},
pages = {224--231},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.09.010},
doi = {10.1016/J.VLSI.2017.09.010},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ArastehMTNB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ArdakaniSR18,
author = {Amir Ardakani and
Shahriar B. Shokouhi and
Arash Reyhani{-}Masoleh},
title = {Improving performance of FPGA-based SR-latch {PUF} using Transient
Effect Ring Oscillator and programmable delay lines},
journal = {Integr.},
volume = {62},
pages = {371--381},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.017},
doi = {10.1016/J.VLSI.2018.04.017},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ArdakaniSR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ArshadRQ18,
author = {Sana Arshad and
Rashad Ramzan and
Qamar{-}ul{-}Wahab},
title = {50-830 MHz noise and distortion canceling {CMOS} low noise amplifier},
journal = {Integr.},
volume = {60},
pages = {63--73},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.07.006},
doi = {10.1016/J.VLSI.2017.07.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ArshadRQ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AsifHKA18,
author = {Shahzad Asif and
Md. Selim Hossain and
Yinan Kong and
Wadood Abdul},
title = {A Fully {RNS} based {ECC} Processor},
journal = {Integr.},
volume = {61},
pages = {138--149},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.11.010},
doi = {10.1016/J.VLSI.2017.11.010},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AsifHKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Asyaei18,
author = {Mohammad Asyaei},
title = {A new low-power dynamic circuit for wide fan-in gates},
journal = {Integr.},
volume = {60},
pages = {263--271},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.010},
doi = {10.1016/J.VLSI.2017.10.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Asyaei18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AttiaFIM18,
author = {Sameh Attia and
Hossam A. H. Fahmy and
Yehea Ismail and
Hassan Mostafa},
title = {Optimizing FPGA-based hard networks-on-chip by minimizing and sharing
resources},
journal = {Integr.},
volume = {63},
pages = {138--147},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.06.005},
doi = {10.1016/J.VLSI.2018.06.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AttiaFIM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BahryEH18,
author = {Mohamed Khairy Bahry and
Mohamed El{-}Nozahi and
Emad Hegazi},
title = {An all-digital low ripples capacitive {DC-DC} converter with load
tracking controller},
journal = {Integr.},
volume = {62},
pages = {123--131},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.007},
doi = {10.1016/J.VLSI.2018.02.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BahryEH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BalobasK18,
author = {Dimitrios Balobas and
Nikos Konofaos},
title = {High-performance and energy-efficient 64-bit incrementer/decrementer
using Multiple-Output Monotonic {CMOS}},
journal = {Integr.},
volume = {62},
pages = {270--281},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.013},
doi = {10.1016/J.VLSI.2018.03.013},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BalobasK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BambergNO18,
author = {Lennart Bamberg and
Amir Najafi and
Alberto Garc{\'{\i}}a Ortiz},
title = {Edge effects on the {TSV} array capacitances and their performance
influence},
journal = {Integr.},
volume = {61},
pages = {1--10},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.003},
doi = {10.1016/J.VLSI.2017.10.003},
timestamp = {Fri, 05 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BambergNO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BansalG18,
author = {Urvashi Bansal and
Maneesha Gupta},
title = {High bandwidth transimpedance amplifier using {FGMOS} for low voltage
operation},
journal = {Integr.},
volume = {60},
pages = {153--159},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.09.001},
doi = {10.1016/J.VLSI.2017.09.001},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BansalG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BasiriS18,
author = {M. Mohamed Asan Basiri and
Sandeep K. Shukla},
title = {Low power hardware implementations for network packet processing elements},
journal = {Integr.},
volume = {62},
pages = {170--181},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.011},
doi = {10.1016/J.VLSI.2018.02.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BasiriS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BayramC18,
author = {Ismail Bayram and
Yiran Chen},
title = {{NV-TCAM:} Alternative designs with {NVM} devices},
journal = {Integr.},
volume = {62},
pages = {114--122},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.003},
doi = {10.1016/J.VLSI.2018.02.003},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BayramC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BerrimaBS18,
author = {Safa Berrima and
Yves Blaqui{\`{e}}re and
Yvon Savaria},
title = {Diagnosis algorithms for a reconfigurable and defect tolerant {JTAG}
scan chain in large area integrated circuits},
journal = {Integr.},
volume = {62},
pages = {159--169},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.010},
doi = {10.1016/J.VLSI.2018.02.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BerrimaBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BhattacharyayRR18,
author = {Rupam Bhattacharya and
Pranab Roy and
Hafizur Rahaman},
title = {Homogeneous droplet routing in {DMFB:} An enhanced technique for high
performance bioassay implementation},
journal = {Integr.},
volume = {60},
pages = {74--91},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.08.001},
doi = {10.1016/J.VLSI.2017.08.001},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BhattacharyayRR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CalvilloPGH18,
author = {Jonathan Calvillo and
Ricardo P{\'{o}}voa and
Jorge Guilherme and
Nuno Horta},
title = {Second-order compensation {BGR} with low {TC} and high performance
for space applications},
journal = {Integr.},
volume = {63},
pages = {256--265},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.07.001},
doi = {10.1016/J.VLSI.2018.07.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CalvilloPGH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CapuaHFDPPAG18,
author = {Giulia Di Capua and
Nuno Horta and
Francisco V. Fern{\'{a}}ndez and
G{\"{u}}nhan D{\"{u}}ndar and
Salvatore Pennisi and
Gaetano Palumbo and
Massimo Alioto and
Gianluca Giustolisi},
title = {Guest Editorial Special Issue on Selected Papers from {PRIME} 2017
and {SMACD} 2017},
journal = {Integr.},
volume = {63},
pages = {273--274},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.09.005},
doi = {10.1016/J.VLSI.2018.09.005},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CapuaHFDPPAG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChatterjeeMC18,
author = {Navonil Chatterjee and
Priyajit Mukherjee and
Santanu Chattopadhyay},
title = {Reliability-aware application mapping onto mesh based Network-on-Chip},
journal = {Integr.},
volume = {62},
pages = {92--113},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.002},
doi = {10.1016/J.VLSI.2018.02.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChatterjeeMC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenLWSLMCWL18,
author = {Yiran Chen and
Hai (Helen) Li and
Chunpeng Wu and
Chang Song and
Sicheng Li and
Chuhan Min and
Hsin{-}Pai Cheng and
Wei Wen and
Xiaoxiao Liu},
title = {Neuromorphic computing's yesterday, today, and tomorrow - an evolutional
view},
journal = {Integr.},
volume = {61},
pages = {49--61},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.11.001},
doi = {10.1016/J.VLSI.2017.11.001},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChenLWSLMCWL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenW18,
author = {Jun{-}Da Chen and
Wen{-}Jun Wang},
title = {A 1.5{\unicode{8239}}{\(\sim\)}{\unicode{8239}}5{\unicode{8239}}GHz
{CMOS} broadband low-power high-efficiency power amplifier for wireless
communications},
journal = {Integr.},
volume = {63},
pages = {167--173},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.07.003},
doi = {10.1016/J.VLSI.2018.07.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChenW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenZS18,
author = {Baixin Chen and
Cheng Zhuo and
Yiyu Shi},
title = {A physics-aware methodology for equivalent circuit model extraction
of TSV-inductors},
journal = {Integr.},
volume = {63},
pages = {160--166},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.07.002},
doi = {10.1016/J.VLSI.2018.07.002},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChenZS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChoiJK18,
author = {Yongsuk Choi and
Gyunam Jeon and
Yong{-}Bin Kim},
title = {Transceiver design for {LVSTL} signal interface with a low power on-chip
self calibration scheme},
journal = {Integr.},
volume = {63},
pages = {148--159},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.06.006},
doi = {10.1016/J.VLSI.2018.06.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChoiJK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CocciaTMC18,
author = {Arianna Coccia and
Saheed Tijani and
Danilo Manstretta and
Rinaldo Castello},
title = {A {TVWS} receiver with balanced output self-calibrated {IIP2} {LNTA}
employing a low-noise current multiplier},
journal = {Integr.},
volume = {63},
pages = {283--290},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.011},
doi = {10.1016/J.VLSI.2018.04.011},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CocciaTMC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CorreaD18,
author = {Roberto Sanchez Correa and
Jean{-}Pierre David},
title = {Ultra-low latency communication channels for FPGA-based {HPC} cluster},
journal = {Integr.},
volume = {63},
pages = {41--55},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.005},
doi = {10.1016/J.VLSI.2018.05.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CorreaD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DanaieRK18,
author = {Mohammad Danaie and
Esmaeel Ranjbar and
Mojtaba Ahmadieh Khanesar},
title = {{MOSCAP} compensation of three-stage operational amplifiers: Sensitivity
and robustness, modeling and analysis},
journal = {Integr.},
volume = {62},
pages = {34--49},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.01.003},
doi = {10.1016/J.VLSI.2018.01.003},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DanaieRK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FangYSY18,
author = {Yun Fang and
Xiaopeng Yu and
Zheng Shi and
Kiat Seng Yeo},
title = {A 2.4{\unicode{8239}}mW 2.5{\unicode{8239}}GHz multi-phase clock generator
with duty cycle imbalance correction in 0.13{\unicode{8239}}{\(\mathrm{\mu}\)}m
{CMOS}},
journal = {Integr.},
volume = {63},
pages = {87--92},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.011},
doi = {10.1016/J.VLSI.2018.05.011},
timestamp = {Thu, 13 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FangYSY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GarlandoRTFSVG18,
author = {Umberto Garlando and
Fabrizio Riente and
Giovanna Turvani and
A. Ferrara and
Giulia Santoro and
Marco Vacca and
Mariagrazia Graziano},
title = {Architectural exploration of perpendicular Nano Magnetic Logic based
circuits},
journal = {Integr.},
volume = {63},
pages = {275--282},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.001},
doi = {10.1016/J.VLSI.2018.05.001},
timestamp = {Fri, 13 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GarlandoRTFSVG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GaurSG18,
author = {Hari Mohan Gaur and
Ashutosh Kumar Singh and
Umesh Ghanekar},
title = {Offline Testing of Reversible Logic Circuits: An Analysis},
journal = {Integr.},
volume = {62},
pages = {50--67},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.01.004},
doi = {10.1016/J.VLSI.2018.01.004},
timestamp = {Thu, 14 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GaurSG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GhorbaniG18,
author = {Alireza Ghorbani and
M. B. Ghaznavi{-}Ghoushchi},
title = {A low-area, 43.5{\%} PAE, 0.9 W, Class-E differential power amplifier
in 2.4 GHz for IoT applications},
journal = {Integr.},
volume = {61},
pages = {178--185},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.12.006},
doi = {10.1016/J.VLSI.2017.12.006},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GhorbaniG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GhoshBB18,
author = {Arindrajit Ghosh and
Uddalak Bhattacharya and
Swapna Banerjee},
title = {Contention free delayed keeper for high density large signal sensing
memory compiler},
journal = {Integr.},
volume = {62},
pages = {24--33},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.12.010},
doi = {10.1016/J.VLSI.2017.12.010},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GhoshBB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GlaserGKF18,
author = {Georg Gl{\"{a}}ser and
Martin Grabmann and
Gerrit Kropp and
Andreas Furtig},
title = {There is a limit to everything: Automating {AMS} operating condition
check generation on system-level},
journal = {Integr.},
volume = {63},
pages = {383--391},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.016},
doi = {10.1016/J.VLSI.2018.02.016},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GlaserGKF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GrecoPSRP18,
author = {Nunzio Greco and
Alessandro Parisi and
Nunzio Spina and
Egidio Ragonese and
Giuseppe Palmisano},
title = {Scalable lumped models of integrated transformers for galvanically
isolated power transfer systems},
journal = {Integr.},
volume = {63},
pages = {323--331},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.01.005},
doi = {10.1016/J.VLSI.2018.01.005},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GrecoPSRP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HaldHSLSB18,
author = {Axel Hald and
Pekka Herzogenrath and
J{\"{u}}rgen Scheible and
Jens Lienig and
Johannes Seelhorst and
Peter Brandl},
title = {Full custom {MEMS} design: {A} new method for the analysis of motion-dependent
parasitics},
journal = {Integr.},
volume = {63},
pages = {362--372},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.004},
doi = {10.1016/J.VLSI.2018.02.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HaldHSLSB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HanXJ18,
author = {Qiang Han and
Qiang Xu and
Wen{-}Ben Jone},
title = {{SERA:} statistical error rate analysis for profit-oriented performance
binning of resilient circuits},
journal = {Integr.},
volume = {60},
pages = {1--12},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.08.007},
doi = {10.1016/J.VLSI.2017.08.007},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HanXJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HassanMF18,
author = {Amr Hassan and
Hassan Mostafa and
Hossam A. H. Fahmy},
title = {NoC-DPR: {A} new simulation tool exploiting the Dynamic Partial Reconfiguration
{(DPR)} on Network-on-Chip (NoC) based {FPGA}},
journal = {Integr.},
volume = {63},
pages = {204--212},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.003},
doi = {10.1016/J.VLSI.2018.04.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HassanMF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HatiB18,
author = {Manas Kumar Hati and
Tarun Kanti Bhattacharyya},
title = {Phase noise analysis of proposed {PFD} and {CP} switching circuit
and its advantages over various {PFD/CP} switching circuits in phase-locked
loops},
journal = {Integr.},
volume = {63},
pages = {115--129},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.06.002},
doi = {10.1016/J.VLSI.2018.06.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HatiB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HayatiCZ18,
author = {Mohsen Hayati and
Sajad Cheraghaliei and
Sepehr Zarghami},
title = {Design of {UWB} low noise amplifier using noise-canceling and current-reused
techniques},
journal = {Integr.},
volume = {60},
pages = {232--239},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.002},
doi = {10.1016/J.VLSI.2017.10.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HayatiCZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HijaziGCV18,
author = {Zeinab Hijazi and
Marco Grassi and
Daniele D. Caviglia and
Maurizio Valle},
title = {Time-based calibration-less read-out circuit for interfacing wide
range {MOX} gas sensors},
journal = {Integr.},
volume = {63},
pages = {232--239},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.004},
doi = {10.1016/J.VLSI.2018.05.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HijaziGCV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HsiehLHS18,
author = {Jui{-}Hung Hsieh and
Rong{-}Choi Lee and
King{-}Chu Hung and
Meng{-}Ju Shih},
title = {Rapid and coding-efficient {SPIHT} algorithm for wavelet-based {ECG}
data compression},
journal = {Integr.},
volume = {60},
pages = {248--256},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.006},
doi = {10.1016/J.VLSI.2017.10.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HsiehLHS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HuangZLC18,
author = {Jinglei Huang and
Wei Zhong and
Zhigang Li and
Song Chen},
title = {Lagrangian relaxation-based routing path allocation for application-specific
network-on-chips},
journal = {Integr.},
volume = {61},
pages = {20--28},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.011},
doi = {10.1016/J.VLSI.2017.10.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HuangZLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/IbrahimPV18,
author = {Ali Ibrahim and
Luigi Pinna and
Maurizio Valle},
title = {Experimental characterization of dedicated front-end electronics for
piezoelectric tactile sensing arrays},
journal = {Integr.},
volume = {63},
pages = {266--272},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.07.007},
doi = {10.1016/J.VLSI.2018.07.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/IbrahimPV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/IshiguchiION18,
author = {Yoritaka Ishiguchi and
Daishi Isogai and
Takuma Osawa and
Shigetoshi Nakatake},
title = {Analog perceptron circuit with DAC-based multiplier},
journal = {Integr.},
volume = {63},
pages = {240--247},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.010},
doi = {10.1016/J.VLSI.2018.05.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/IshiguchiION18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JamshidiM18,
author = {Paria Jamshidi and
Mohammad Maymandi{-}Nejad},
title = {Analysis of the impact of interferers on VCO-based continuous time
delta-sigma modulators},
journal = {Integr.},
volume = {62},
pages = {132--141},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.008},
doi = {10.1016/J.VLSI.2018.02.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JamshidiM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KarimiRH18,
author = {Ahmad Karimi and
Abdalhossein Rezai and
Mohammad Mahdi Hajhashemkhani},
title = {A novel design for ultra-low power pulse-triggered D-Flip-Flop with
optimized leakage power},
journal = {Integr.},
volume = {60},
pages = {160--166},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.09.002},
doi = {10.1016/J.VLSI.2017.09.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KarimiRH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KazeminiaH18,
author = {Sarang Kazeminia and
Khayrollah Hadidi},
title = {A foreground-liked continuous-time offset cancellation strategy for
open-loop inter-stage amplifiers in high-resolution ADCs},
journal = {Integr.},
volume = {61},
pages = {88--100},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.11.005},
doi = {10.1016/J.VLSI.2017.11.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KazeminiaH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhalidHHA18,
author = {Faiq Khalid and
Syed Rafay Hasan and
Osman Hasan and
Falah R. Awwad},
title = {Runtime hardware Trojan monitors through modeling burst mode communication
using formal verification},
journal = {Integr.},
volume = {61},
pages = {62--76},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.11.003},
doi = {10.1016/J.VLSI.2017.11.003},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KhalidHHA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhalilVCB18,
author = {Ali Abou Khalil and
Maurizio Valle and
Hussein Chible and
Chiara Bartolozzi},
title = {{CMOS} event-driven tactile sensor circuit},
journal = {Integr.},
volume = {63},
pages = {315--322},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.006},
doi = {10.1016/J.VLSI.2018.04.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KhalilVCB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimS18,
author = {Sangmin Kim and
Youngsoo Shin},
title = {Module grouping to reduce the area of test wrappers in SoCs},
journal = {Integr.},
volume = {60},
pages = {39--47},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.09.006},
doi = {10.1016/J.VLSI.2017.09.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KimS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimTCS18,
author = {Taeyoung Kim and
Sheldon X.{-}D. Tan and
Chase Cook and
Zeyu Sun},
title = {Detection of counterfeited ICs via on-chip sensor and post-fabrication
authentication policy},
journal = {Integr.},
volume = {63},
pages = {31--40},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.002},
doi = {10.1016/J.VLSI.2018.05.002},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KimTCS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KirubaS18,
author = {M. Kiruba and
V. Sumathy},
title = {Register Pre-Allocation based Folded Discrete Tchebichef Transformation
Technique for Image Compression},
journal = {Integr.},
volume = {60},
pages = {13--24},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.07.003},
doi = {10.1016/J.VLSI.2017.07.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KirubaS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KoteKVJH18,
author = {Vlastimil Kote and
Adam Kubacak and
Patrik Vacula and
Jiri Jakovenko and
Miroslav Hus{\'{a}}k},
title = {Automated pre-placement phase as a part of robust analog-mixed signal
physical design flow},
journal = {Integr.},
volume = {63},
pages = {18--30},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.018},
doi = {10.1016/J.VLSI.2018.04.018},
timestamp = {Tue, 02 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KoteKVJH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KristofikM18,
author = {Stefan Kristof{\'{\i}}k and
Peter Mal{\'{\i}}k},
title = {Enhancement of fault collection for embedded {RAM} redundancy analysis
considering intersection and orphan faults},
journal = {Integr.},
volume = {62},
pages = {190--204},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.015},
doi = {10.1016/J.VLSI.2018.02.015},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KristofikM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarN18,
author = {Ankur Kumar and
Rajendra Kumar Nagaria},
title = {A new leakage-tolerant high speed comparator based domino gate for
wide fan-in {OR} logic for low power {VLSI} circuits},
journal = {Integr.},
volume = {63},
pages = {174--184},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.07.004},
doi = {10.1016/J.VLSI.2018.07.004},
timestamp = {Sat, 18 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KumarN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LacaitaBMS18,
author = {Niccolo Lacaita and
Matteo Bassi and
Andrea Mazzanti and
Francesco Svelto},
title = {A K-band low-noise bipolar class-C {VCO} for 5G backhaul systems in
55{\unicode{8239}}nm BiCMOS technology},
journal = {Integr.},
volume = {63},
pages = {299--305},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.009},
doi = {10.1016/J.VLSI.2018.04.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LacaitaBMS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LancasterK18,
author = {Austin Lancaster and
Manish Keswani},
title = {Integrated circuit packaging review with an emphasis on 3D packaging},
journal = {Integr.},
volume = {60},
pages = {204--212},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.09.008},
doi = {10.1016/J.VLSI.2017.09.008},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LancasterK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LateYA18,
author = {Even L{\aa}te and
Trond Ytterdal and
Snorre Aunet},
title = {A loadless 6T {SRAM} cell for sub- {\&} near- threshold operation
implemented in 28{\unicode{8239}}nm {FD-SOI} {CMOS} technology},
journal = {Integr.},
volume = {63},
pages = {56--63},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.006},
doi = {10.1016/J.VLSI.2018.05.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LateYA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LepercqBS18,
author = {Etienne Lepercq and
Yves Blaqui{\`{e}}re and
Yvon Savaria},
title = {A pattern-based routing algorithm for a novel electronic system prototyping
platform},
journal = {Integr.},
volume = {62},
pages = {224--237},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.005},
doi = {10.1016/J.VLSI.2018.03.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LepercqBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiCZ18,
author = {Xingquan Li and
Jianli Chen and
Wenxing Zhu},
title = {Discrete relaxation method for contact layer decomposition of {DSA}
with triple patterning},
journal = {Integr.},
volume = {61},
pages = {77--87},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.11.004},
doi = {10.1016/J.VLSI.2017.11.004},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiCZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiTLZ18,
author = {Yanbin Li and
Ming Tang and
Yuguang Li and
Huanguo Zhang},
title = {Several weaknesses of the implementation for the theoretically secure
masking schemes under {ISW} framework},
journal = {Integr.},
volume = {60},
pages = {92--98},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.08.002},
doi = {10.1016/J.VLSI.2017.08.002},
timestamp = {Mon, 16 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiTLZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiaoZ18,
author = {Tuotian Liao and
Lihong Zhang},
title = {Efficient parasitic-aware hybrid sizing methodology for analog and
{RF} integrated circuits},
journal = {Integr.},
volume = {62},
pages = {301--313},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.017},
doi = {10.1016/J.VLSI.2018.03.017},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiaoZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LimachiaTK18,
author = {Mitesh Limachia and
Rajesh Amratlal Thakker and
Nikhil Kothari},
title = {A near-threshold 10T differential {SRAM} cell with high read and write
margins for tri-gated FinFET technology},
journal = {Integr.},
volume = {61},
pages = {125--137},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.11.009},
doi = {10.1016/J.VLSI.2017.11.009},
timestamp = {Fri, 26 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LimachiaTK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LimachiaVTK18,
author = {Mitesh Limachia and
Dixit Vyas and
Rajesh Amratlal Thakker and
Nikhil Kothari},
title = {Hybrid offset compensated latch-type sense amplifier for tri-gated
FinFET technology},
journal = {Integr.},
volume = {62},
pages = {258--269},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.012},
doi = {10.1016/J.VLSI.2018.03.012},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LimachiaVTK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuHLG18,
author = {Chang Liu and
Xu He and
Bin Liang and
Yang Guo},
title = {Detailed placement for pulse quenching enhancement in anti-radiation
combinational circuit design},
journal = {Integr.},
volume = {62},
pages = {182--189},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.014},
doi = {10.1016/J.VLSI.2018.02.014},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiuHLG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LvZWJ18,
author = {Xiaolong Lv and
Xiao Zhao and
Yongqing Wang and
Dawei Jia},
title = {Super class {AB-AB} bulk-driven folded cascode {OTA}},
journal = {Integr.},
volume = {63},
pages = {196--203},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.07.009},
doi = {10.1016/J.VLSI.2018.07.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LvZWJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaSCVS18,
author = {Yufei Ma and
Naveen Suda and
Yu Cao and
Sarma B. K. Vrudhula and
Jae{-}sun Seo},
title = {{ALAMO:} {FPGA} acceleration of deep learning algorithms with a modularized
{RTL} compiler},
journal = {Integr.},
volume = {62},
pages = {14--23},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.12.009},
doi = {10.1016/J.VLSI.2017.12.009},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MaSCVS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MackoJC18,
author = {Dominik Macko and
Katar{\'{\i}}na Jelemensk{\'{a}} and
Pavel Cic{\'{a}}k},
title = {Simplifying low-power SoC top-down design using the system-level abstraction
and the increased automation},
journal = {Integr.},
volume = {63},
pages = {101--114},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.06.001},
doi = {10.1016/J.VLSI.2018.06.001},
timestamp = {Tue, 13 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MackoJC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MahapatraLS18,
author = {Anushree Mahapatra and
Yidi Liu and
Benjamin Carri{\'{o}}n Sch{\"{a}}fer},
title = {Accelerating cycle-accurate system-level simulations through behavioral
templates},
journal = {Integr.},
volume = {62},
pages = {282--291},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.014},
doi = {10.1016/J.VLSI.2018.03.014},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MahapatraLS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaheshwariBK18,
author = {Sachin Maheshwari and
Vivian A. Bartlett and
Izzet Kale},
title = {Energy efficient implementation of multi-phase quasi-adiabatic Cyclic
Redundancy Check in near field communication},
journal = {Integr.},
volume = {62},
pages = {341--352},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.002},
doi = {10.1016/J.VLSI.2018.04.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MaheshwariBK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MohammadjanyHN18,
author = {Armin Mohammadjany and
Ali Reza Hazeri and
Hossein Miar Naimi},
title = {Exact analyses for locking range in injection-locked frequency dividers},
journal = {Integr.},
volume = {63},
pages = {93--100},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.012},
doi = {10.1016/J.VLSI.2018.05.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MohammadjanyHN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MowlaviBSK18,
author = {Siavash Mowlavi and
Aram Baharmast and
Jafar Sobhi and
Ziaddin Daei Koozehkanani},
title = {A novel current-mode low-power adjustable wide input range four-quadrant
analog multiplier},
journal = {Integr.},
volume = {63},
pages = {130--137},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.06.003},
doi = {10.1016/J.VLSI.2018.06.003},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MowlaviBSK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MukherjeeDC18,
author = {Priyajit Mukherjee and
Sandeep D'Souza and
Santanu Chattopadhyay},
title = {Area Constrained Performance Optimized ASNoC Synthesis with Thermal-aware
White Space Allocation and Redistribution},
journal = {Integr.},
volume = {60},
pages = {167--189},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.09.004},
doi = {10.1016/J.VLSI.2017.09.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MukherjeeDC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NakhaeeKAPFD18,
author = {Farzaneh Nakhaee and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram and
Sied Mehdi Fakhraie and
Hamed Dorosti},
title = {Lifetime improvement by exploiting aggressive voltage scaling during
runtime of error-resilient applications},
journal = {Integr.},
volume = {61},
pages = {29--38},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.013},
doi = {10.1016/J.VLSI.2017.10.013},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NakhaeeKAPFD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NamC18,
author = {Minho Nam and
Kyoung{-}Rok Cho},
title = {Implementation of real-time image edge detector based on a bump circuit
and active pixels in a {CMOS} image sensor},
journal = {Integr.},
volume = {60},
pages = {56--62},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.07.005},
doi = {10.1016/J.VLSI.2017.07.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NamC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NedjahBM18,
author = {Nadia Nedjah and
Heloisa Dina Bezerra and
Luiza de Macedo Mourelle},
title = {Automatic generation of harmonious music using cellular automata based
hardware design},
journal = {Integr.},
volume = {62},
pages = {205--223},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.002},
doi = {10.1016/J.VLSI.2018.03.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NedjahBM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OparaKK18,
author = {Adam Opara and
Marcin Kubica and
Dariusz Kania},
title = {Strategy of logic synthesis using {MTBDD} dedicated to {FPGA}},
journal = {Integr.},
volume = {62},
pages = {142--158},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.009},
doi = {10.1016/J.VLSI.2018.02.009},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/OparaKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OuyangYXHL18,
author = {Yiming Ouyang and
Jianfeng Yang and
Kun Xing and
Zhengfeng Huang and
Huaguo Liang},
title = {An improved communication scheme for non-HOL-blocking wireless NoC},
journal = {Integr.},
volume = {60},
pages = {240--247},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.005},
doi = {10.1016/J.VLSI.2017.10.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/OuyangYXHL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OzbekADGBB18,
author = {Sefa {\"{O}}zbek and
Golzar Alavi and
Johannes Digel and
Markus Gr{\"{o}}zing and
Joachim N. Burghartz and
Manfred Berroth},
title = {3-Path SiGe BiCMOS power amplifier on thinned substrate for IoT applications},
journal = {Integr.},
volume = {63},
pages = {291--298},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.010},
doi = {10.1016/J.VLSI.2018.04.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/OzbekADGBB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PahujaTPS18,
author = {Hitesh Pahuja and
Mintu Tyagi and
Sudhakar Panday and
Balwinder Singh},
title = {A novel single-ended 9T FinFET sub-threshold {SRAM} cell with high
operating margins and low write power for low voltage operations},
journal = {Integr.},
volume = {60},
pages = {99--116},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.08.004},
doi = {10.1016/J.VLSI.2017.08.004},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PahujaTPS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PakFD18,
author = {Murat Pak and
Francisco V. Fern{\'{a}}ndez and
G{\"{u}}nhan D{\"{u}}ndar},
title = {A novel design methodology for the mixed-domain optimization of a
{MEMS} accelerometer},
journal = {Integr.},
volume = {62},
pages = {314--321},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.018},
doi = {10.1016/J.VLSI.2018.03.018},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PakFD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PanahiHN18,
author = {Mohammad Mehdi Panahi and
Omid Hashemipour and
Keivan Navi},
title = {A novel design of a ternary coded decimal adder/subtractor using reversible
ternary gates},
journal = {Integr.},
volume = {62},
pages = {353--361},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.014},
doi = {10.1016/J.VLSI.2018.04.014},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PanahiHN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PanarelloTGPD18,
author = {Saverio Panarello and
Claudia Triolo and
F. Garesci and
Salvatore Patan{\`{e}} and
R. Denaro},
title = {Improving ICs reliability with high speed thermal mapping},
journal = {Integr.},
volume = {63},
pages = {342--350},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.01.001},
doi = {10.1016/J.VLSI.2018.01.001},
timestamp = {Wed, 04 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PanarelloTGPD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PapistasP18,
author = {Ioannis A. Papistas and
Vasilis F. Pavlidis},
title = {Contactless Heterogeneous 3-D ICs for Smart Sensing Systems},
journal = {Integr.},
volume = {62},
pages = {329--340},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.001},
doi = {10.1016/J.VLSI.2018.04.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PapistasP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PassosMLRPCCHF18,
author = {F{\'{a}}bio Passos and
Ricardo Martins and
Nuno Louren{\c{c}}o and
Elisenda Roca and
Ricardo Povoa and
Ant{\'{o}}nio Canelas and
Rafael Castro{-}L{\'{o}}pez and
Nuno Horta and
Francisco V. Fern{\'{a}}ndez},
title = {Enhanced systematic design of a voltage controlled oscillator using
a two-step optimization methodology},
journal = {Integr.},
volume = {63},
pages = {351--361},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.02.005},
doi = {10.1016/J.VLSI.2018.02.005},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PassosMLRPCCHF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PearlsteinMA18,
author = {Larry Pearlstein and
Skyler Maxwell and
Alex Aved},
title = {Adaptive prediction resolution video coding for reduced {DRAM} bandwidth},
journal = {Integr.},
volume = {62},
pages = {382--394},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.019},
doi = {10.1016/J.VLSI.2018.04.019},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PearlsteinMA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PekcokgulerDTY18,
author = {Naci Pekcokguler and
G{\"{u}}nhan D{\"{u}}ndar and
Hamdi Torun and
Arda D. Yalcinkaya},
title = {A novel equivalent circuit model for split ring resonator with an
application of low phase noise reference oscillator},
journal = {Integr.},
volume = {61},
pages = {160--166},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.12.004},
doi = {10.1016/J.VLSI.2017.12.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PekcokgulerDTY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RadpourS18,
author = {Mohammad Radpour and
Sayed Masoud Sayedi},
title = {SystemC-AMS modeling of photodiode based on {PWL} technique to be
used in energy harvesting {CMOS} image sensor},
journal = {Integr.},
volume = {60},
pages = {48--55},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.08.006},
doi = {10.1016/J.VLSI.2017.08.006},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RadpourS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RastegarZR18,
author = {Habib Rastegar and
Saeid Zare and
Jee{-}Youl Ryu},
title = {A low-voltage low-power capacitive-feedback voltage controlled oscillator},
journal = {Integr.},
volume = {60},
pages = {257--262},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.008},
doi = {10.1016/J.VLSI.2017.10.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RastegarZR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RestaGMPMEB18,
author = {Federica Resta and
Simone Gerardin and
S. Mattiazzo and
Alessandro Paccagnella and
Marcello De Matteis and
Christian C. Enz and
Andrea Baschirotto},
title = {1GigaRad {TID} impact on 28{\unicode{8239}}nm {HEP} analog circuits},
journal = {Integr.},
volume = {63},
pages = {306--314},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.007},
doi = {10.1016/J.VLSI.2018.04.007},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RestaGMPMEB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RienteGVG18,
author = {Fabrizio Riente and
Andrea Giordano and
Marco Vacca and
Mariagrazia Graziano},
title = {Exploring N\({}^{\mbox{3}}\)ASIC technology for microwave imaging
architectures},
journal = {Integr.},
volume = {62},
pages = {395--405},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.003},
doi = {10.1016/J.VLSI.2018.05.003},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RienteGVG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RizzoCZ18,
author = {Roberto Giorgio Rizzo and
Andrea Calimera and
Jun Zhou},
title = {Approximate Error Detection-Correction for efficient Adaptive Voltage
Over-Scaling},
journal = {Integr.},
volume = {63},
pages = {220--231},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.008},
doi = {10.1016/J.VLSI.2018.04.008},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/RizzoCZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SadeghiN18,
author = {Mohammad Sadeghi and
Hooman Nikmehr},
title = {Aging mitigation of {L1} cache by exchanging instruction and data
caches},
journal = {Integr.},
volume = {62},
pages = {68--75},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.01.006},
doi = {10.1016/J.VLSI.2018.01.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SadeghiN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SaglamdemirDS18,
author = {Muharrem Orkun Saglamdemir and
G{\"{u}}nhan D{\"{u}}ndar and
Alper Sen},
title = {Analog behavioral equivalence boundary computation under the effect
of process variations},
journal = {Integr.},
volume = {61},
pages = {39--48},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.014},
doi = {10.1016/J.VLSI.2017.10.014},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SaglamdemirDS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SannenaD18,
author = {Govinda Sannena and
Bishnu Prasad Das},
title = {Metastability immune and area efficient error masking flip-flop for
timing error resilient designs},
journal = {Integr.},
volume = {61},
pages = {101--113},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.11.006},
doi = {10.1016/J.VLSI.2017.11.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SannenaD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShabanyPMMG18,
author = {Mahdi Shabany and
Dimpesh Patel and
Mario Milicevic and
Mojtaba Mahdavi and
P. Glenn Gulak},
title = {A 70{\unicode{8239}}pJ/b configurable 64-QAM soft {MIMO} detector},
journal = {Integr.},
volume = {63},
pages = {74--86},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.008},
doi = {10.1016/J.VLSI.2018.05.008},
timestamp = {Wed, 22 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShabanyPMMG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Shi18,
author = {Guoyong Shi},
title = {Toward automated reasoning for analog {IC} design by symbolic computation
- {A} survey},
journal = {Integr.},
volume = {60},
pages = {117--131},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.08.005},
doi = {10.1016/J.VLSI.2017.08.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Shi18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShihHC18,
author = {Xin{-}Yu Shih and
Po{-}Chun Huang and
Hong{-}Ru Chou},
title = {{VLSI} design and implementation of a reconfigurable hardware-friendly
Polar encoder architecture for emerging high-speed 5G system},
journal = {Integr.},
volume = {62},
pages = {292--300},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.015},
doi = {10.1016/J.VLSI.2018.03.015},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ShihHC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SinghJMYSJG18,
author = {Kunwar Singh and
Aman Jain and
Aviral Mittal and
Vinay Yadav and
Atul Anshuman Singh and
Anmoll Kumar Jain and
Maneesha Gupta},
title = {Optimum transistor sizing of {CMOS} logic circuits using logical effort
theory and evolutionary algorithms},
journal = {Integr.},
volume = {60},
pages = {25--38},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.08.003},
doi = {10.1016/J.VLSI.2017.08.003},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SinghJMYSJG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SinghRVSV18,
author = {Pooran Singh and
Bhupendra Singh Reniwal and
Vikas Vijayvargiya and
V. Sharma and
Santosh Kumar Vishvakarma},
title = {Ultra low power-high stability, positive feedback controlled {(PFC)}
10T {SRAM} cell for look up table {(LUT)} design},
journal = {Integr.},
volume = {62},
pages = {1--13},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.006},
doi = {10.1016/J.VLSI.2018.03.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SinghRVSV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SrinivasPK18,
author = {Nagapuri Srinivas and
Gayadhar Pradhan and
Puli Kishore Kumar},
title = {An efficient hardware architecture for detection of vowel-like regions
in speech signal},
journal = {Integr.},
volume = {63},
pages = {185--195},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.07.005},
doi = {10.1016/J.VLSI.2018.07.005},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SrinivasPK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/StradoliniTKDC18,
author = {Francesca Stradolini and
Abuduwaili Tuoheti and
Tugba Kilic and
Danilo Demarchi and
Sandro Carrara},
title = {Raspberry-Pi based system for propofol monitoring},
journal = {Integr.},
volume = {63},
pages = {213--219},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.04.004},
doi = {10.1016/J.VLSI.2018.04.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/StradoliniTKDC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TanAKSCH18,
author = {Sheldon X.{-}D. Tan and
Hussam Amrouch and
Taeyoung Kim and
Zeyu Sun and
Chase Cook and
J{\"{o}}rg Henkel},
title = {Recent advances in {EM} and {BTI} induced reliability modeling, analysis
and optimization (invited)},
journal = {Integr.},
volume = {60},
pages = {132--152},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.08.009},
doi = {10.1016/J.VLSI.2017.08.009},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TanAKSCH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TanR18,
author = {Tze Sin Tan and
Bakhtiar Affendi Rosdi},
title = {Hardware-assisted Verilog simulation system using an application specific
microprocessor},
journal = {Integr.},
volume = {62},
pages = {76--91},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.01.007},
doi = {10.1016/J.VLSI.2018.01.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TanR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TenaceC18,
author = {Valerio Tenace and
Andrea Calimera},
title = {Quasi-exact logic functions through classification trees},
journal = {Integr.},
volume = {63},
pages = {248--255},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.06.007},
doi = {10.1016/J.VLSI.2018.06.007},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TenaceC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TertelH18,
author = {Philipp Tertel and
Lars Hedrich},
title = {Real-time emulation of block-based analog circuits on an {FPGA}},
journal = {Integr.},
volume = {63},
pages = {373--382},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.01.008},
doi = {10.1016/J.VLSI.2018.01.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TertelH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TukelYO18,
author = {Mehmet T{\"{u}}kel and
Arda Yurdakul and
Berna {\"{O}}rs},
title = {Customizable embedded processor array for multimedia applications},
journal = {Integr.},
volume = {60},
pages = {213--223},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.09.009},
doi = {10.1016/J.VLSI.2017.09.009},
timestamp = {Tue, 16 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TukelYO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangS18,
author = {Aili Wang and
Chuanjin Richard Shi},
title = {A 10-bit 50-MS/s {SAR} {ADC} with 1 fJ/Conversion in 14{\unicode{8239}}nm
{SOI} FinFET {CMOS}},
journal = {Integr.},
volume = {62},
pages = {246--257},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.010},
doi = {10.1016/J.VLSI.2018.03.010},
timestamp = {Fri, 12 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangZCMLZ18,
author = {Nan Wang and
Wei Zhong and
Song Chen and
Zhiyuan Ma and
Xiaofeng Ling and
Yu Zhu},
title = {Power-gating-aware scheduling with effective hardware resources optimization},
journal = {Integr.},
volume = {61},
pages = {167--177},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.12.005},
doi = {10.1016/J.VLSI.2017.12.005},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangZCMLZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XiangP18,
author = {Yi Xiang and
Sudeep Pasricha},
title = {Mixed-criticality scheduling on heterogeneous multicore systems powered
by energy harvesting},
journal = {Integr.},
volume = {61},
pages = {114--124},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.11.007},
doi = {10.1016/J.VLSI.2017.11.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/XiangP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuPRF18,
author = {Kan Xu and
Ravi Patel and
Praveen Raghavan and
Eby G. Friedman},
title = {Exploratory design of on-chip power delivery for 14, 10, and 7 nm
and beyond FinFET ICs},
journal = {Integr.},
volume = {61},
pages = {11--19},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.007},
doi = {10.1016/J.VLSI.2017.10.007},
timestamp = {Mon, 07 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/XuPRF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YingTT18,
author = {Jen{-}Cheng Ying and
Wang{-}Dauh Tseng and
Wen{-}Jiin Tsai},
title = {Asymmetry dual-LFSR reseeding for low power {BIST}},
journal = {Integr.},
volume = {60},
pages = {272--276},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.10.012},
doi = {10.1016/J.VLSI.2017.10.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YingTT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangS18,
author = {Ailin Zhang and
Guoyong Shi},
title = {A fast symbolic {SNR} computation method and its Verilog-A implementation
for Sigma-Delta modulator design optimization},
journal = {Integr.},
volume = {60},
pages = {190--203},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.09.007},
doi = {10.1016/J.VLSI.2017.09.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhaoWD18,
author = {Xiao Zhao and
Yongqing Wang and
Liyuan Dong},
title = {Super current recycling folded cascode amplifier with ultra-high current
efficiency},
journal = {Integr.},
volume = {62},
pages = {322--328},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.019},
doi = {10.1016/J.VLSI.2018.03.019},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhaoWD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhengLYWT18,
author = {Desheng Zheng and
Xiaoyu Li and
Guowu Yang and
Hai Wang and
Lulu Tian},
title = {An assertion graph based abstraction algorithm in {GSTE} and Its application},
journal = {Integr.},
volume = {63},
pages = {1--8},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.03.009},
doi = {10.1016/J.VLSI.2018.03.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhengLYWT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AcciaritoCCNFKR17,
author = {Simone Acciarito and
Gian Carlo Cardarilli and
Alessandro Cristini and
Luca Di Nunzio and
Rocco Fazzolari and
Gaurav Mani Khanal and
Marco Re and
Gianluca Susi},
title = {Hardware design of {LIF} with Latency neuron model with memristive
{STDP} synapses},
journal = {Integr.},
volume = {59},
pages = {81--89},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.05.006},
doi = {10.1016/J.VLSI.2017.05.006},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AcciaritoCCNFKR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AfacanDPYB17,
author = {Engin Afacan and
G{\"{u}}nhan D{\"{u}}ndar and
Ali Emre Pusane and
Mustafa Berke Yelten and
I. Faik Baskaya},
title = {Aging signature properties and an efficient signature determination
tool for online monitoring},
journal = {Integr.},
volume = {58},
pages = {496--503},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.002},
doi = {10.1016/J.VLSI.2017.03.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AfacanDPYB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AhmadyanNV17,
author = {Seyed Nematollah Ahmadyan and
Suriyaprakash Natarajan and
Shobha Vasudevan},
title = {A novel test compression algorithm for analog circuits to decrease
production costs},
journal = {Integr.},
volume = {58},
pages = {538--548},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.010},
doi = {10.1016/J.VLSI.2016.10.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AhmadyanNV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BabuL17,
author = {Gunti Nagendra Babu and
Karthikeyan Lingasubramanian},
title = {Effective usage of redundancy to aid neutralization of hardware Trojans
in Integrated Circuits},
journal = {Integr.},
volume = {59},
pages = {233--242},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.002},
doi = {10.1016/J.VLSI.2017.06.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BabuL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BahadoriKAAS17,
author = {Milad Bahadori and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Yasmin Afsharnezhad and
Elham Zahraie Salehi},
title = {{CL-CPA:} {A} hybrid carry-lookahead/carry-propagate adder for low-power
or high-performance operation mode},
journal = {Integr.},
volume = {57},
pages = {62--68},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.009},
doi = {10.1016/J.VLSI.2016.11.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BahadoriKAAS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BalciogluD17,
author = {Yal{\c{c}}in Balcioglu and
G{\"{u}}nhan D{\"{u}}ndar},
title = {A standard cell phase locked loop design, analysis and high-level
synthesis tool (CellPLL)},
journal = {Integr.},
volume = {58},
pages = {142--154},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.04.001},
doi = {10.1016/J.VLSI.2017.04.001},
timestamp = {Mon, 24 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BalciogluD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BaltaciL17,
author = {Can Baltaci and
Yusuf Leblebici},
title = {Thermal aware design and comparative analysis of a high performance
64-bit adder in {FD-SOI} and bulk {CMOS} technologies},
journal = {Integr.},
volume = {58},
pages = {421--429},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.001},
doi = {10.1016/J.VLSI.2017.03.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BaltaciL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Bandala-Hernandez17,
author = {H. C. Bandala{-}Hernandez and
Alejandro D{\'{\i}}az{-}S{\'{a}}nchez and
Jos{\'{e}} Miguel Rocha{-}P{\'{e}}rez and
Jaime Ram{\'{\i}}rez{-}Angulo and
I. Y. L{\'{o}}pez{-}Ortega and
Javier Lemus{-}L{\'{o}}pez and
Jes{\'{u}}s Ezequiel Molinar{-}Sol{\'{\i}}s},
title = {{CMOS} Analog Rank Order Filters using positive feedback comparators},
journal = {Integr.},
volume = {58},
pages = {111--115},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.005},
doi = {10.1016/J.VLSI.2017.02.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Bandala-Hernandez17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BasiriS17,
author = {M. Mohamed Asan Basiri and
Sandeep K. Shukla},
title = {Flexible {VLSI} architectures for Galois field multipliers},
journal = {Integr.},
volume = {59},
pages = {109--124},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.009},
doi = {10.1016/J.VLSI.2017.06.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BasiriS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BelabadMS17,
author = {Ahmad Rahati Belabad and
Seyed Ahmad Motamedi and
Saeed Sharifian},
title = {An adaptive digital predistortion for compensating nonlinear distortions
in {RF} power amplifier with memory effects},
journal = {Integr.},
volume = {57},
pages = {184--191},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.01.001},
doi = {10.1016/J.VLSI.2017.01.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BelabadMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BernardiniR17,
author = {Riccardo Bernardini and
Roberto Rinaldo},
title = {A very stable diode-based physically unclonable constant},
journal = {Integr.},
volume = {59},
pages = {179--189},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.010},
doi = {10.1016/J.VLSI.2017.06.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BernardiniR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BiswasCPD17,
author = {Achira Pal and
Atal Chaudhuri and
Rajat Kumar Pal and
Alak Kumar Datta},
title = {Hardness of crosstalk minimization in two-layer channel routing},
journal = {Integr.},
volume = {56},
pages = {139--147},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.001},
doi = {10.1016/J.VLSI.2016.10.001},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BiswasCPD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CampbellZC17,
author = {Keith A. Campbell and
Wei Zuo and
Deming Chen},
title = {New advances of high-level synthesis for efficient and reliable hardware
design},
journal = {Integr.},
volume = {58},
pages = {189--214},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.006},
doi = {10.1016/J.VLSI.2016.11.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CampbellZC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CapuaFS17,
author = {Giulia Di Capua and
Nicola Femia and
Kateryna Stoyka},
title = {A generalized numerical method for ferrite inductors analysis in high
current ripple operation},
journal = {Integr.},
volume = {58},
pages = {473--484},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.01.008},
doi = {10.1016/J.VLSI.2017.01.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CapuaFS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CasciolaLDPMA17,
author = {Maura Casciola and
Micaela Liberti and
Agnese Denzi and
Alessandra Paffi and
Caterina Merla and
Francesca Apollonio},
title = {A computational design of a versatile microchamber for in vitro nanosecond
pulsed electric fields experiments},
journal = {Integr.},
volume = {58},
pages = {446--453},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.005},
doi = {10.1016/J.VLSI.2017.03.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CasciolaLDPMA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChanKL17,
author = {Wei{-}Ting Jonas Chan and
Andrew B. Kahng and
Jiajia Li},
title = {Revisiting 3DIC benefit with multiple tiers},
journal = {Integr.},
volume = {58},
pages = {226--235},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.01.004},
doi = {10.1016/J.VLSI.2017.01.004},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChanKL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CharitopoulosKP17,
author = {George Charitopoulos and
Iosif Koidis and
Kyprianos Papadimitriou and
Dionisios N. Pnevmatikatos},
title = {Run-time management of systems with partially reconfigurable FPGAs},
journal = {Integr.},
volume = {57},
pages = {34--44},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.008},
doi = {10.1016/J.VLSI.2016.11.008},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CharitopoulosKP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenGZW17,
author = {Jun Chen and
Benqing Guo and
Boyang Zhang and
Guangjun Wen},
title = {An inductorless wideband common-gate {LNA} with dual capacitor cross-coupled
feedback and negative impedance techniques},
journal = {Integr.},
volume = {56},
pages = {53--60},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.09.006},
doi = {10.1016/J.VLSI.2016.09.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChenGZW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenLZZ17,
author = {Jianli Chen and
Yan Liu and
Ziran Zhu and
Wenxing Zhu},
title = {An adaptive hybrid memetic algorithm for thermal-aware non-slicing
{VLSI} floorplanning},
journal = {Integr.},
volume = {58},
pages = {245--252},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.006},
doi = {10.1016/J.VLSI.2017.03.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChenLZZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenPYL17,
author = {Hongmei Chen and
Yunsheng Pan and
Yongsheng Yin and
Fujiang Lin},
title = {All-digital background calibration technique for timing mismatch of
time-interleaved ADCs},
journal = {Integr.},
volume = {57},
pages = {45--51},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.003},
doi = {10.1016/J.VLSI.2016.11.003},
timestamp = {Mon, 06 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChenPYL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Cruz-BlasTML17,
author = {Carlos Aristoteles De la Cruz{-}Blas and
G. Thomas{-}Erviti and
Jos{\'{e}} Mar{\'{\i}}a Algueta{-}Miguel and
Antonio J. L{\'{o}}pez{-}Mart{\'{\i}}n},
title = {{CMOS} analogue current-mode multiplier/divider circuit operating
in triode-saturation with bulk-driven techniques},
journal = {Integr.},
volume = {59},
pages = {243--246},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.001},
doi = {10.1016/J.VLSI.2017.06.001},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Cruz-BlasTML17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CuiCWZNP17,
author = {Tiansong Cui and
Shuang Chen and
Yanzhi Wang and
Qi Zhu and
Shahin Nazarian and
Massoud Pedram},
title = {An optimal energy co-scheduling framework for smart buildings},
journal = {Integr.},
volume = {58},
pages = {528--537},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.009},
doi = {10.1016/J.VLSI.2016.10.009},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CuiCWZNP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CuiLLQ17,
author = {Aijiao Cui and
Yanhui Luo and
Huawei Li and
Gang Qu},
title = {Why current secure scan designs fail and how to fix them?},
journal = {Integr.},
volume = {56},
pages = {105--114},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.011},
doi = {10.1016/J.VLSI.2016.10.011},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CuiLLQ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DaliriMNB17,
author = {Mahya Sam Daliri and
Reza Faghih Mirzaee and
Keivan Navi and
Nader Bagherzadeh},
title = {High-performance ternary operators for scrambling},
journal = {Integr.},
volume = {59},
pages = {1--9},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.010},
doi = {10.1016/J.VLSI.2017.03.010},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DaliriMNB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DamghanianA17,
author = {Masumeh Damghanian and
Seyed Javad Azhari},
title = {A low-power 6-bit {MOS} {CML} flash {ADC} with a novel multi-segment
encoder for {UWB} applications},
journal = {Integr.},
volume = {57},
pages = {158--168},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.01.006},
doi = {10.1016/J.VLSI.2017.01.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DamghanianA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DebWKSD17,
author = {Arighna Deb and
Robert Wille and
Oliver Kesz{\"{o}}cze and
Saeideh Shirinzadeh and
Rolf Drechsler},
title = {Synthesis of optical circuits using binary decision diagrams},
journal = {Integr.},
volume = {59},
pages = {42--51},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.05.001},
doi = {10.1016/J.VLSI.2017.05.001},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DebWKSD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DehbashianM17,
author = {Maryam Dehbashian and
Mohammad Maymandi{-}Nejad},
title = {A new hybrid algorithm for analog ICs optimization based on the shrinking
circles technique},
journal = {Integr.},
volume = {56},
pages = {148--166},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.09.009},
doi = {10.1016/J.VLSI.2016.09.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DehbashianM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DehbashianM17a,
author = {Maryam Dehbashian and
Mohammad Maymandi{-}Nejad},
title = {Co-AGSA: An efficient self-adaptive approach for constrained optimization
of analog {IC} based on the shrinking circles technique},
journal = {Integr.},
volume = {59},
pages = {218--232},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.003},
doi = {10.1016/J.VLSI.2017.06.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DehbashianM17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DengZWJ17,
author = {Libao Deng and
Baoquan Zhang and
Sha Wang and
Chengyu Jin},
title = {{IPRM:} {IP} core resource multiplexing of core wrapper design for
reducing test application time in DVFS-based multicore SoCs},
journal = {Integr.},
volume = {57},
pages = {132--146},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.011},
doi = {10.1016/J.VLSI.2016.12.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DengZWJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DiBianoM17,
author = {Robert DiBiano and
Supratik Mukhopadhyay},
title = {Automated diagnostics for manufacturing machinery based on well-regularized
deep neural networks},
journal = {Integr.},
volume = {58},
pages = {303--310},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.012},
doi = {10.1016/J.VLSI.2017.03.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DiBianoM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/EkenBZYWLC17,
author = {Enes Eken and
Ismail Bayram and
Yaojun Zhang and
Bonan Yan and
Wenqing Wu and
Hai (Helen) Li and
Yiran Chen},
title = {Giant Spin-Hall assisted {STT-RAM} and logic design},
journal = {Integr.},
volume = {58},
pages = {253--261},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.04.002},
doi = {10.1016/J.VLSI.2017.04.002},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/EkenBZYWLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/El-Maleh17,
author = {Aiman H. El{-}Maleh},
title = {A probabilistic pairwise swap search state assignment algorithm for
sequential circuit optimization},
journal = {Integr.},
volume = {56},
pages = {32--43},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.08.001},
doi = {10.1016/J.VLSI.2016.08.001},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/El-Maleh17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/EwetzK17,
author = {Rickard Ewetz and
Cheng{-}Kok Koh},
title = {Fast clock scheduling and an application to clock tree synthesis},
journal = {Integr.},
volume = {56},
pages = {115--127},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.012},
doi = {10.1016/J.VLSI.2016.10.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/EwetzK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FengYC17,
author = {Gan Feng and
Lan Yao and
Song Chen},
title = {AutoNFT: Architecture synthesis for hardware {DFT} of length-of-coprime-number
products},
journal = {Integr.},
volume = {58},
pages = {339--347},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.011},
doi = {10.1016/J.VLSI.2017.03.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FengYC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FreyY17,
author = {Jonathan Frey and
Qiaoyan Yu},
title = {A hardened network-on-chip design using runtime hardware Trojan mitigation
methods},
journal = {Integr.},
volume = {56},
pages = {15--31},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.06.008},
doi = {10.1016/J.VLSI.2016.06.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FreyY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GanjikuntaS17,
author = {Ganesh Kumar Ganjikunta and
Subhendu Kumar Sahoo},
title = {An area-efficient and low-power 64-point pipeline Fast Fourier Transform
for {OFDM} applications},
journal = {Integr.},
volume = {57},
pages = {125--131},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.002},
doi = {10.1016/J.VLSI.2016.12.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GanjikuntaS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GhoshalMS17,
author = {Bibhas Ghoshal and
Chittaranjan Mandal and
Indranil Sengupta},
title = {Refresh re-use based transparent test for detection of in-field permanent
faults in DRAMs},
journal = {Integr.},
volume = {59},
pages = {168--178},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.011},
doi = {10.1016/J.VLSI.2017.06.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GhoshalMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GohCLL17,
author = {Szu Huat Goh and
Y. H. Chan and
Zhao Lin and
Jeffrey Lam},
title = {Concurrent built-in self-testing under the constraint of shared test
resources and its test time reduction},
journal = {Integr.},
volume = {59},
pages = {198--205},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.006},
doi = {10.1016/J.VLSI.2017.06.006},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GohCLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GomezRR17,
author = {H{\'{e}}ctor G{\'{o}}mez and
{\'{O}}scar Reyes and
Elkim Roa},
title = {A 65 nm {CMOS} key establishment core based on tree parity machines},
journal = {Integr.},
volume = {58},
pages = {430--437},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.01.010},
doi = {10.1016/J.VLSI.2017.01.010},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/GomezRR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuoS17,
author = {Xinfei Guo and
Mircea R. Stan},
title = {Implications of accelerated self-healing as a key design knob for
cross-layer resilience},
journal = {Integr.},
volume = {56},
pages = {167--180},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.008},
doi = {10.1016/J.VLSI.2016.10.008},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GuoS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Hajduk17,
author = {Zbigniew Hajduk},
title = {Simple method of asynchronous circuits implementation in commercial
FPGAs},
journal = {Integr.},
volume = {59},
pages = {31--41},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.05.002},
doi = {10.1016/J.VLSI.2017.05.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Hajduk17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HamadehCT17,
author = {Hala Hamadeh and
Soma Chaudhuri and
Akhilesh Tyagi},
title = {Area, energy, and time assessment for a distributed {TPM} for distributed
trust in IoT clusters},
journal = {Integr.},
volume = {58},
pages = {267--273},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.005},
doi = {10.1016/J.VLSI.2016.12.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HamadehCT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HeXWW17,
author = {Jie He and
Liyuan Xu and
Peng Wang and
Qin Wang},
title = {A high precise E-nose for daily indoor air quality monitoring in living
environment},
journal = {Integr.},
volume = {58},
pages = {286--294},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.010},
doi = {10.1016/J.VLSI.2016.12.010},
timestamp = {Tue, 20 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HeXWW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HemmatKAP17,
author = {Maede Hemmat and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {Hybrid {TFET-MOSFET} circuit: {A} solution to design soft-error resilient
ultra-low power digital circuit},
journal = {Integr.},
volume = {57},
pages = {11--19},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.001},
doi = {10.1016/J.VLSI.2016.11.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HemmatKAP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HoAK17,
author = {Patrick W. C. Ho and
Haider Abbas F. Almurib and
T. Nandha Kumar},
title = {Configurable memristive logic block for memristive-based {FPGA} architectures},
journal = {Integr.},
volume = {56},
pages = {61--69},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.09.003},
doi = {10.1016/J.VLSI.2016.09.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HoAK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HoT17,
author = {Tsung{-}Yi Ho and
Baris Taskin},
title = {Special issue on {IEEE/ACM} System Level Interconnect Prediction {(SLIP)}
Workshop 2016},
journal = {Integr.},
volume = {58},
pages = {225},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.05.003},
doi = {10.1016/J.VLSI.2017.05.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HoT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HortaBFDGF17,
author = {Nuno Horta and
Andrea Baschirotto and
Francisco V. Fern{\'{a}}ndez and
G{\"{u}}nhan D{\"{u}}ndar and
Jo{\~{a}}o Goes and
Jorge Fernandes},
title = {Introduction to the special issue on {PRIME} 2016 and {SMACD} 2016},
journal = {Integr.},
volume = {58},
pages = {411--412},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.015},
doi = {10.1016/J.VLSI.2017.03.015},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HortaBFDGF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HsiehHW17,
author = {Jui{-}Hung Hsieh and
Jian{-}Hao Huang and
Hung{-}Ren Wang},
title = {DVFS-aware motion estimation design scheme based on bandwidth-rate-distortion
optimization in application processor systems},
journal = {Integr.},
volume = {57},
pages = {74--80},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.004},
doi = {10.1016/J.VLSI.2016.12.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HsiehHW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HsuHL17,
author = {Chih{-}Cheng Hsu and
Masanori Hashimoto and
Mark Po{-}Hung Lin},
title = {Minimizing detection-to-boosting latency toward low-power error-resilient
circuits},
journal = {Integr.},
volume = {58},
pages = {236--244},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.01.002},
doi = {10.1016/J.VLSI.2017.01.002},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HsuHL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HuangSKT17,
author = {Xin Huang and
Valeriy Sukharev and
Taeyoung Kim and
Sheldon X.{-}D. Tan},
title = {Dynamic electromigration modeling for transient stress evolution and
recovery under time-dependent current and temperature stressing},
journal = {Integr.},
volume = {58},
pages = {518--527},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.007},
doi = {10.1016/J.VLSI.2016.10.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HuangSKT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/IottiBMS17,
author = {Lorenzo Iotti and
Matteo Bassi and
Andrea Mazzanti and
Francesco Svelto},
title = {Design of low-power wideband frequency quadruplers based on transformer-coupled
resonators for E-Band backhaul applications},
journal = {Integr.},
volume = {58},
pages = {413--420},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.003},
doi = {10.1016/J.VLSI.2017.03.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/IottiBMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Jin17,
author = {Jie Jin},
title = {Resonant amplifier-based sub-harmonic mixer for zero-IF transceiver
applications},
journal = {Integr.},
volume = {57},
pages = {69--73},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.012},
doi = {10.1016/J.VLSI.2016.11.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Jin17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JinHHM17,
author = {Wei Jin and
Guanghui He and
Weifeng He and
Zhigang Mao},
title = {A 12-bit 4928 {\texttimes} 3264 pixel {CMOS} image signal processor
for digital still cameras},
journal = {Integr.},
volume = {59},
pages = {206--217},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.005},
doi = {10.1016/J.VLSI.2017.06.005},
timestamp = {Thu, 15 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JinHHM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JinHJHZSCJ17,
author = {Wei Jin and
Weifeng He and
Jianfei Jiang and
Haichao Huang and
Xuejun Zhao and
Yanan Sun and
Xin Chen and
Naifeng Jing},
title = {A 0.33 {V} 2.5 {\(\mu\)}W cross-point data-aware write structure,
read-half-select disturb-free sub-threshold {SRAM} in 130 nm {CMOS}},
journal = {Integr.},
volume = {58},
pages = {27--34},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.001},
doi = {10.1016/J.VLSI.2017.02.001},
timestamp = {Sun, 23 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/JinHJHZSCJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JooK17,
author = {Deokjin Joo and
Taewhan Kim},
title = {Clock buffer polarity assignment under useful skew constraints},
journal = {Integr.},
volume = {57},
pages = {52--61},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.007},
doi = {10.1016/J.VLSI.2016.11.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JooK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KaboliGA17,
author = {Milad Kaboli and
Behzad Ghanavati and
Majid Akhlaghi},
title = {A new {CMOS} pseudo approximation exponential function generator by
modified particle swarm optimization algorithm},
journal = {Integr.},
volume = {56},
pages = {70--76},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.003},
doi = {10.1016/J.VLSI.2016.10.003},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KaboliGA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KakacakGCGU17,
author = {Ahmet Kakacak and
Aydin Emre Guzel and
Ozan Cihangir and
Sezer G{\"{o}}ren and
H. Fatih Ugurdag},
title = {Fast Multiplier Generator for FPGAs with {LUT} based Partial Product
Generation and Column/row Compression},
journal = {Integr.},
volume = {57},
pages = {147--157},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.012},
doi = {10.1016/J.VLSI.2016.12.012},
timestamp = {Tue, 16 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KakacakGCGU17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KarmakarC17,
author = {Rajit Karmakar and
Santanu Chattopadhyay},
title = {Temperature and data size trade-off in dictionary based test data
compression},
journal = {Integr.},
volume = {57},
pages = {20--33},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.002},
doi = {10.1016/J.VLSI.2016.11.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KarmakarC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhodabandelooKJ17,
author = {Behnam Khodabandeloo and
Ahmad Khonsari and
Masoomeh Jasemi and
Golnaz Taheri},
title = {A fast temperature-aware fixed-outline floorplanning framework using
convex optimization},
journal = {Integr.},
volume = {58},
pages = {101--110},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.01.007},
doi = {10.1016/J.VLSI.2017.01.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KhodabandelooKJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KhoshaviADKOT17,
author = {Navid Khoshavi and
Rizwan A. Ashraf and
Ronald F. DeMara and
Saman Kiamehr and
Fabian Oboril and
Mehdi Baradaran Tahoori},
title = {Contemporary {CMOS} aging mitigation techniques: Survey, taxonomy,
and methods},
journal = {Integr.},
volume = {59},
pages = {10--22},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.013},
doi = {10.1016/J.VLSI.2017.03.013},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KhoshaviADKOT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimK17,
author = {Joohan Kim and
Taewhan Kim},
title = {Boundary optimization of buffered clock trees for low power},
journal = {Integr.},
volume = {56},
pages = {86--95},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.004},
doi = {10.1016/J.VLSI.2016.10.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KimK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimM17,
author = {Jaeyoung Kim and
Pinaki Mazumder},
title = {A robust 12T {SRAM} cell with improved write margin for ultra-low
power applications in 40 nm {CMOS}},
journal = {Integr.},
volume = {57},
pages = {1--10},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.09.008},
doi = {10.1016/J.VLSI.2016.09.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KimM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KlausSPFS17,
author = {Jenny Klaus and
Eric Schaefer and
Roman Paris and
Astrid Frank and
Ralf Sommer},
title = {A contribution towards model-based design of application-specific
{MEMS}},
journal = {Integr.},
volume = {58},
pages = {454--462},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.014},
doi = {10.1016/J.VLSI.2017.03.014},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KlausSPFS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KostrzewaSEE17,
author = {Adam Kostrzewa and
Selma Saidi and
Leonardo Ecco and
Rolf Ernst},
title = {Ensuring safety and efficiency in networks-on-chip},
journal = {Integr.},
volume = {58},
pages = {571--582},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.015},
doi = {10.1016/J.VLSI.2016.10.015},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KostrzewaSEE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KouranyGHI17,
author = {Taher Kourany and
Maged Ghoneima and
Emad Hegazi and
Yehea Ismail},
title = {{PASSIOT:} {A} Pareto-optimal multi-objective optimization approach
for synthesis of analog circuits using Sobol' indices-based engine},
journal = {Integr.},
volume = {58},
pages = {9--21},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.006},
doi = {10.1016/J.VLSI.2016.12.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KouranyGHI17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KoutrasMDSS17,
author = {Ioannis Koutras and
Konstantinos Maragos and
Dionysios Diamantopoulos and
Kostas Siozios and
Dimitrios Soudris},
title = {On supporting rapid prototyping of embedded systems with reconfigurable
architectures},
journal = {Integr.},
volume = {58},
pages = {91--100},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.007},
doi = {10.1016/J.VLSI.2017.02.007},
timestamp = {Fri, 02 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KoutrasMDSS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarRSM17,
author = {K. Sudeendra Kumar and
G. Hanumanta Rao and
Sauvagya Ranjan Sahoo and
Kamala Kanta Mahapatra},
title = {Secure split test techniques to prevent {IC} piracy for IoT devices},
journal = {Integr.},
volume = {58},
pages = {390--400},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.09.004},
doi = {10.1016/J.VLSI.2016.09.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KumarRSM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarTMP17,
author = {S. Dinesh Kumar and
Himanshu Thapliyal and
Azhar Mohammad and
Kalyan S. Perumalla},
title = {Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient
and secure hardware},
journal = {Integr.},
volume = {58},
pages = {369--377},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.08.007},
doi = {10.1016/J.VLSI.2016.08.007},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KumarTMP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LahiouelAZT17,
author = {Ons Lahiouel and
Henda Aridhi and
Mohamed H. Zaki and
Sofi{\`{e}}ne Tahar},
title = {Exploiting bounds optimization for the semi-formal verification of
analog circuits},
journal = {Integr.},
volume = {59},
pages = {135--147},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.008},
doi = {10.1016/J.VLSI.2017.06.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LahiouelAZT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Lemus-LopezDRMR17,
author = {Javier Lemus{-}L{\'{o}}pez and
Alejandro D{\'{\i}}az{-}S{\'{a}}nchez and
Jos{\'{e}} Miguel Rocha{-}P{\'{e}}rez and
Carlos Mu{\~{n}}iz{-}Montero and
Jaime Ram{\'{\i}}rez{-}Angulo},
title = {High gain amplifier with feedforward compensation based on quasi-floating
gate transistors},
journal = {Integr.},
volume = {59},
pages = {75--80},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.05.007},
doi = {10.1016/J.VLSI.2017.05.007},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Lemus-LopezDRMR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiXLHCY17,
author = {Zongwei Li and
Xingyin Xiong and
Xiong Liu and
Kedu Han and
Ning Cong and
Changchun Yang},
title = {Design of a high precision digital interface circuit for capacitive
{MEMS} accelerometers with floating point {ADC}},
journal = {Integr.},
volume = {59},
pages = {247--254},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.05.008},
doi = {10.1016/J.VLSI.2017.05.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiXLHCY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LinYZLAP17,
author = {Yibo Lin and
Bei Yu and
Yi Zou and
Zhuo Li and
Charles J. Alpert and
David Z. Pan},
title = {Stitch aware detailed placement for multiple E-beam lithography},
journal = {Integr.},
volume = {58},
pages = {47--54},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.004},
doi = {10.1016/J.VLSI.2017.02.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LinYZLAP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuGPH17,
author = {Tao Liu and
Hui Guo and
Sri Parameswaran and
Xiaobo Sharon Hu},
title = {iCETD: An improved tag generation design for memory data authentication
in embedded processor systems},
journal = {Integr.},
volume = {56},
pages = {96--104},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.006},
doi = {10.1016/J.VLSI.2016.10.006},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiuGPH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MajumderMB17,
author = {Alak Majumder and
Abir J. Mondal and
Bidyut K. Bhattacharyya},
title = {Threshold adjustment of receiver chip to achieve a data rate {\textgreater}66
Gbit/sec in point to point interconnect},
journal = {Integr.},
volume = {58},
pages = {348--355},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.004},
doi = {10.1016/J.VLSI.2016.11.004},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MajumderMB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MartinsLCH17,
author = {Ricardo Martins and
Nuno Louren{\c{c}}o and
Ant{\'{o}}nio Canelas and
Nuno Horta},
title = {Stochastic-based placement template generator for analog {IC} layout-aware
synthesis},
journal = {Integr.},
volume = {58},
pages = {485--495},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.012},
doi = {10.1016/J.VLSI.2017.02.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MartinsLCH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MeadeZJ17,
author = {Travis Meade and
Shaojie Zhang and
Yier Jin},
title = {{IP} protection through gate-level netlist security enhancement},
journal = {Integr.},
volume = {58},
pages = {563--570},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.014},
doi = {10.1016/J.VLSI.2016.10.014},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MeadeZJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MitraN17,
author = {Jubin Mitra and
Tapan Kumar Nayak},
title = {Reconfigurable very high throughput low latency {VLSI} {(FPGA)} design
architecture of {CRC} 32},
journal = {Integr.},
volume = {56},
pages = {1--14},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.09.005},
doi = {10.1016/J.VLSI.2016.09.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MitraN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MohantySHG17,
author = {Saraju P. Mohanty and
Ashok Srivastava and
Shiyan Hu and
Prasun Ghosal},
title = {Guest editorial - Special issue on hardware assisted techniques for
IoT and bigdata applications},
journal = {Integr.},
volume = {58},
pages = {263--266},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.05.004},
doi = {10.1016/J.VLSI.2017.05.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MohantySHG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MomenYKS17,
author = {Hadi Ghasemzadeh Momen and
Metin Yazgi and
Ramazan K{\"{o}}pr{\"{u}} and
Ali Naderi Saatlo},
title = {Low-loss active inductor with independently adjustable self-resonance
frequency and quality factor parameters},
journal = {Integr.},
volume = {58},
pages = {22--26},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.014},
doi = {10.1016/J.VLSI.2016.12.014},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MomenYKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MondalMB17,
author = {Abir J. Mondal and
Alak Majumder and
Bidyut K. Bhattacharyya},
title = {A mathematical formulation to design and implementation of a low voltage
swing transceiver circuit},
journal = {Integr.},
volume = {58},
pages = {356--368},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.013},
doi = {10.1016/J.VLSI.2016.11.013},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MondalMB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MoonK17,
author = {Hyoungseok Moon and
Taewhan Kim},
title = {Loosely coupled multi-bit flip-flop allocation for power reduction},
journal = {Integr.},
volume = {58},
pages = {125--133},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.006},
doi = {10.1016/J.VLSI.2017.02.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MoonK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MossaHE17,
author = {Siraj Fulum Mossa and
Syed Rafay Hasan and
Omar S. Elkeelany},
title = {Self-triggering hardware trojan: Due to {NBTI} related aging in 3-D
ICs},
journal = {Integr.},
volume = {58},
pages = {116--124},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.013},
doi = {10.1016/J.VLSI.2016.12.013},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MossaHE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MossaHE17a,
author = {Siraj Fulum Mossa and
Syed Rafay Hasan and
Omar S. Elkeelany},
title = {Hardware trojans in 3-D ICs due to {NBTI} effects and countermeasure},
journal = {Integr.},
volume = {59},
pages = {64--74},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.009},
doi = {10.1016/J.VLSI.2017.03.009},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MossaHE17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MukherjeeC17,
author = {Priyajit Mukherjee and
Santanu Chattopadhyay},
title = {Low Power Low Latency Floorplan-aware Path Synthesis in Application-Specific
Network-on-Chip Design},
journal = {Integr.},
volume = {58},
pages = {167--188},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.010},
doi = {10.1016/J.VLSI.2017.02.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MukherjeeC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MukherjeePS17,
author = {Subhamita Mukherjee and
Indrajit Pan and
Tuhina Samanta},
title = {Pareto optimization technique in actuation control for error minimization
and reliability analysis in an operational pin-constrained digital
microfluidic biochip},
journal = {Integr.},
volume = {59},
pages = {125--134},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.07.004},
doi = {10.1016/J.VLSI.2017.07.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MukherjeePS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NaeiniDOYI17,
author = {Mahshid Mojtabavi Naeini and
Sreedharan Baskara Dass and
Chia Yee Ooi and
Tomokazu Yoneda and
Michiko Inoue},
title = {An integrated {DFT} solution for power reduction in scan test applications
by low power gating scan cell},
journal = {Integr.},
volume = {57},
pages = {108--124},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.009},
doi = {10.1016/J.VLSI.2016.12.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NaeiniDOYI17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NandanKM17,
author = {Durgesh Nandan and
Jitendra Kanungo and
Anurag Mahajan},
title = {An efficient {VLSI} architecture design for logarithmic multiplication
by using the improved operand decomposition},
journal = {Integr.},
volume = {58},
pages = {134--141},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.003},
doi = {10.1016/J.VLSI.2017.02.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NandanKM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NikolovL17,
author = {Dimitar Nikolov and
Erik Larsson},
title = {Clustered checkpointing: Maximizing the level of confidence for non-equidistant
checkpointing},
journal = {Integr.},
volume = {58},
pages = {549--562},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.013},
doi = {10.1016/J.VLSI.2016.10.013},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NikolovL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OlumodejiG17,
author = {Olufemi Akindele Olumodeji and
Massimo Gottardi},
title = {Arduino-controlled {HP} memristor emulator for memristor circuit applications},
journal = {Integr.},
volume = {58},
pages = {438--445},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.004},
doi = {10.1016/J.VLSI.2017.03.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/OlumodejiG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Papakonstantinou17,
author = {George K. Papakonstantinou},
title = {Exclusive or Sum of Complex Terms expressions minimization},
journal = {Integr.},
volume = {56},
pages = {44--52},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.08.005},
doi = {10.1016/J.VLSI.2016.08.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Papakonstantinou17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PassosRCF17,
author = {F{\'{a}}bio Passos and
Elisenda Roca and
Rafael Castro{-}L{\'{o}}pez and
Francisco V. Fern{\'{a}}ndez},
title = {An inductor modeling and optimization toolbox for {RF} circuit design},
journal = {Integr.},
volume = {58},
pages = {463--472},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.01.009},
doi = {10.1016/J.VLSI.2017.01.009},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PassosRCF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PhamAL17,
author = {Huyen Thi Pham and
Sabooh Ajaz and
Hanho Lee},
title = {High-throughput partial-parallel block-layered decoding architecture
for nonbinary {LDPC} codes},
journal = {Integr.},
volume = {59},
pages = {52--63},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.05.005},
doi = {10.1016/J.VLSI.2017.05.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PhamAL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/QuiHL17,
author = {Nguyen Cao Qui and
Si{-}Rong He and
Chien{-}Nan Jimmy Liu},
title = {Cluster-based delta-QMC technique for fast yield analysis},
journal = {Integr.},
volume = {58},
pages = {64--73},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.011},
doi = {10.1016/J.VLSI.2017.02.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/QuiHL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RahmanikiaANM17,
author = {Navid Rahmanikia and
Amirali Amiri and
Hamid Noori and
Farhad Mehdipour},
title = {Performance evaluation metrics for ring-oscillator-based temperature
sensors on FPGAs: {A} quality factor},
journal = {Integr.},
volume = {57},
pages = {81--100},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.007},
doi = {10.1016/J.VLSI.2016.12.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RahmanikiaANM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RayT17,
author = {Niranjan Kumar Ray and
Ashok Kumar Turuk},
title = {A framework for post-disaster communication using wireless ad hoc
networks},
journal = {Integr.},
volume = {58},
pages = {274--285},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.011},
doi = {10.1016/J.VLSI.2016.11.011},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RayT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SahooKM17,
author = {Sauvagya Ranjan Sahoo and
K. Sudeendra Kumar and
Kamalakanta Mahapatra},
title = {A novel current controlled configurable {RO} {PUF} with improved security
metrics},
journal = {Integr.},
volume = {58},
pages = {401--410},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.005},
doi = {10.1016/J.VLSI.2016.11.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SahooKM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SchmidtZTZ17,
author = {Bernhard Schmidt and
Daniel Ziener and
J{\"{u}}rgen Teich and
Christian Z{\"{o}}llner},
title = {Optimizing scrubbing by netlist analysis for {FPGA} configuration
bit classification and floorplanning},
journal = {Integr.},
volume = {59},
pages = {98--108},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.012},
doi = {10.1016/J.VLSI.2017.06.012},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SchmidtZTZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SenguptaRB17,
author = {Anirban Sengupta and
Dipanjan Roy and
Saumya Bhadauria},
title = {Low cost optimized Trojan secured schedule at behavioral level for
single {\&} Nested loop control data flow graphs (Invited Paper)},
journal = {Integr.},
volume = {58},
pages = {378--389},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.09.007},
doi = {10.1016/J.VLSI.2016.09.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SenguptaRB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SethiHH17,
author = {Muhammad Athar Javed Sethi and
Fawnizu Azmadi Hussin and
Nor Hisham Hamid},
title = {Bio-inspired fault tolerant network on chip},
journal = {Integr.},
volume = {58},
pages = {155--166},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.04.004},
doi = {10.1016/J.VLSI.2017.04.004},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SethiHH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShahghasemiY17,
author = {Mohsen Shahghasemi and
Mohammad Yavari},
title = {{MASH} {\(\Sigma\)}{\(\Delta\)} modulators with a noise-shaped two-step
{ADC} in the second stage},
journal = {Integr.},
volume = {56},
pages = {77--85},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.002},
doi = {10.1016/J.VLSI.2016.10.002},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShahghasemiY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SheikhE17,
author = {Ahmad T. Sheikh and
Aiman H. El{-}Maleh},
title = {An integrated fault tolerance technique for combinational circuits
based on implications and transistor sizing},
journal = {Integr.},
volume = {58},
pages = {35--46},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.01.005},
doi = {10.1016/J.VLSI.2017.01.005},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SheikhE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShiALY17,
author = {Weijing Shi and
Mohamed Baker Alawieh and
Xin Li and
Huafeng Yu},
title = {Algorithm and hardware implementation for visual perception system
in autonomous vehicle: {A} survey},
journal = {Integr.},
volume = {59},
pages = {148--156},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.07.007},
doi = {10.1016/J.VLSI.2017.07.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShiALY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SinghSDM17,
author = {Wazir Singh and
Ankita Shukla and
Sujay Deb and
Angshul Majumdar},
title = {Energy efficient {EEG} acquisition and reconstruction for a Wireless
Body Area Network},
journal = {Integr.},
volume = {58},
pages = {295--302},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.08.006},
doi = {10.1016/J.VLSI.2016.08.006},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SinghSDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SivanandanMDNN17,
author = {Nalesh Sivanandan and
Kavitha T. Madhu and
Saptarsi Das and
S. K. Nandy and
Ranjani Narayan},
title = {Energy aware synthesis of application kernels through composition
of data-paths on a {CGRA}},
journal = {Integr.},
volume = {58},
pages = {320--328},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.009},
doi = {10.1016/J.VLSI.2017.02.009},
timestamp = {Tue, 27 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SivanandanMDNN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SorkhabiZ17,
author = {Samin Ebrahim Sorkhabi and
Lihong Zhang},
title = {Automated topology synthesis of analog and {RF} integrated circuits:
{A} survey},
journal = {Integr.},
volume = {56},
pages = {128--138},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.017},
doi = {10.1016/J.VLSI.2016.10.017},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SorkhabiZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/StillmakerB17,
author = {Aaron Stillmaker and
Bevan M. Baas},
title = {Scaling equations for the accurate prediction of {CMOS} device performance
from 180 nm to 7 nm},
journal = {Integr.},
volume = {58},
pages = {74--81},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.002},
doi = {10.1016/J.VLSI.2017.02.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/StillmakerB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TangPLWW17,
author = {He Tang and
Yong Peng and
Xiang Lu and
Albert Z. Wang and
Hai Wang},
title = {A quantitative design methodology for high-speed interpolation/averaging
ADCs},
journal = {Integr.},
volume = {58},
pages = {215--224},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.008},
doi = {10.1016/J.VLSI.2017.03.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TangPLWW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TonkA17,
author = {Anu Tonk and
Neelofer Afzal},
title = {On advance towards sub-sampling technique in phase locked loops -
{A} review},
journal = {Integr.},
volume = {59},
pages = {90--97},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.004},
doi = {10.1016/J.VLSI.2017.06.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TonkA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TsimposDVS17,
author = {Andreas Tsimpos and
Andreas Christos Demartinos and
Spyridon Vlassis and
George Souliotis},
title = {Jitter tolerance calibration for high-speed serial interfaces},
journal = {Integr.},
volume = {57},
pages = {101--107},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.008},
doi = {10.1016/J.VLSI.2016.12.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TsimposDVS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TuriD17,
author = {Michael A. Turi and
Jos{\'{e}} G. Delgado{-}Frias},
title = {Full-V\({}_{\mbox{DD}}\) and near-threshold performance of 8T FinFET
{SRAM} cells},
journal = {Integr.},
volume = {57},
pages = {169--183},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.003},
doi = {10.1016/J.VLSI.2016.12.003},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TuriD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VenkatesanPT17,
author = {Varun Venkatesan and
Swamy D. Ponpandi and
Akhilesh Tyagi},
title = {Shaping data for application performance and energy optimization in
dynamic data view framework},
journal = {Integr.},
volume = {58},
pages = {311--319},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.12.001},
doi = {10.1016/J.VLSI.2016.12.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/VenkatesanPT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangCJGM17,
author = {Qin Wang and
Zhenyang Chen and
Jianfei Jiang and
Zheng Guo and
Zhigang Mao},
title = {Dynamic data split: {A} crosstalk suppression scheme in TSV-based
3D {IC}},
journal = {Integr.},
volume = {59},
pages = {23--30},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.04.003},
doi = {10.1016/J.VLSI.2017.04.003},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangCJGM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangMLCW17,
author = {Lu Wang and
Sheng Ma and
Chen Li and
Wei Chen and
Zhiying Wang},
title = {A high performance reliable NoC router},
journal = {Integr.},
volume = {58},
pages = {583--592},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.016},
doi = {10.1016/J.VLSI.2016.10.016},
timestamp = {Mon, 12 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangMLCW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WuMWZUS17,
author = {Po{-}Yi Wu and
Wai{-}Kei Mak and
Ting{-}Chi Wang and
Cheng Zhuo and
Kassan Unda and
Yiyu Shi},
title = {A routing framework for technology migration with bump encroachment},
journal = {Integr.},
volume = {58},
pages = {1--8},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.01.003},
doi = {10.1016/J.VLSI.2017.01.003},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WuMWZUS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XuC17,
author = {Qi Xu and
Song Chen},
title = {Fast thermal analysis for fixed-outline 3D floorplanning},
journal = {Integr.},
volume = {59},
pages = {157--167},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.013},
doi = {10.1016/J.VLSI.2017.06.013},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/XuC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XueY17,
author = {Yuan Xue and
Chengmo Yang},
title = {Path reuse-aware routing for non-volatile memory based FPGAs},
journal = {Integr.},
volume = {58},
pages = {505--517},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.005},
doi = {10.1016/J.VLSI.2016.10.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/XueY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangDUNSMG17,
author = {Y. Zhang and
Rostislav (Reuven) Dobkin and
Aharon Unikovski and
Danniel Nahmanny and
Goel Samuel and
Michael Moyal and
Ran Ginosar},
title = {A 1.4{\texttimes}FO4 self-clocked asynchronous serial link in 0.18
{\(\mathrm{\mu}\)}m for intrachip communication},
journal = {Integr.},
volume = {59},
pages = {190--197},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.007},
doi = {10.1016/J.VLSI.2017.06.007},
timestamp = {Mon, 01 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangDUNSMG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangF17,
author = {Jiajun Zhang and
Haining Fan},
title = {Low space complexity CRT-based bit-parallel \emph{GF}(2\({}^{\mbox{n}}\))
polynomial basis multipliers for irreducible trinomials},
journal = {Integr.},
volume = {58},
pages = {55--63},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.008},
doi = {10.1016/J.VLSI.2017.02.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhaoSPCM17,
author = {Zhou Zhao and
Ashok Srivastava and
Lu Peng and
Shaoming Chen and
Saraju P. Mohanty},
title = {A novel switchable pin method for regulating power in chip-multiprocessor},
journal = {Integr.},
volume = {58},
pages = {329--338},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.010},
doi = {10.1016/J.VLSI.2016.11.010},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhaoSPCM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhongHCSW17,
author = {Hengfei Zhong and
Zhuoquan Huang and
Dihu Chen and
Tao Su and
Zixin Wang},
title = {A mechanism for detecting on-chip radio frequency interference of
field-programmable gate array},
journal = {Integr.},
volume = {58},
pages = {82--90},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.03.007},
doi = {10.1016/J.VLSI.2017.03.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhongHCSW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AfacanBDPB16,
author = {Engin Afacan and
G{\"{o}}nen{\c{c}} Berkol and
G{\"{u}}nhan D{\"{u}}ndar and
Ali Emre Pusane and
I. Faik Baskaya},
title = {A lifetime-aware analog circuit sizing tool},
journal = {Integr.},
volume = {55},
pages = {349--356},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.05.004},
doi = {10.1016/J.VLSI.2016.05.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AfacanBDPB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AlbeckW16,
author = {Amir Albeck and
Shmuel Wimer},
title = {Energy efficient computing by multi-mode addition},
journal = {Integr.},
volume = {55},
pages = {176--182},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.06.002},
doi = {10.1016/J.VLSI.2016.06.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AlbeckW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BahadoriKAP16,
author = {Milad Bahadori and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {A comparative study on performance and reliability of 32-bit binary
adders},
journal = {Integr.},
volume = {53},
pages = {54--67},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.12.002},
doi = {10.1016/J.VLSI.2015.12.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BahadoriKAP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Balasubramanian16,
author = {P. Balasubramanian},
title = {Comments on "Dual-rail asynchronous logic multi-level implementation"},
journal = {Integr.},
volume = {52},
pages = {34--40},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.08.001},
doi = {10.1016/J.VLSI.2015.08.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Balasubramanian16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Bandala-Hernandez16,
author = {H. C. Bandala{-}Hernandez and
Jos{\'{e}} Miguel Rocha{-}P{\'{e}}rez and
Alejandro D{\'{\i}}az{-}S{\'{a}}nchez and
Javier Lemus{-}L{\'{o}}pez and
H{\'{e}}ctor V{\'{a}}zquez{-}Leal and
Alejandra D{\'{\i}}az{-}Armendariz and
Jaime Ram{\'{\i}}rez{-}Angulo},
title = {Weighted median filters: An analog implementation},
journal = {Integr.},
volume = {55},
pages = {227--231},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.07.003},
doi = {10.1016/J.VLSI.2016.07.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Bandala-Hernandez16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BasiriM16,
author = {M. Mohamed Asan Basiri and
Sk. Noor Mahammad},
title = {Multi-mode parallel and folded {VLSI} architectures for 1D-fast Fourier
transform},
journal = {Integr.},
volume = {55},
pages = {43--56},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.02.007},
doi = {10.1016/J.VLSI.2016.02.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BasiriM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BastosOGOS16,
author = {Ivan Bastos and
Lu{\'{\i}}s Bica Oliveira and
Jo{\~{a}}o Goes and
Jo{\~{a}}o Pedro Oliveira and
Manuel Medeiros Silva},
title = {Noise canceling {LNA} with gain enhancement by using double feedback},
journal = {Integr.},
volume = {52},
pages = {309--315},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.003},
doi = {10.1016/J.VLSI.2015.07.003},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BastosOGOS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BernardeschiCDS16,
author = {Cinzia Bernardeschi and
Luca Cassano and
Andrea Domenici and
Luca Sterpone},
title = {UA\({}^{\mbox{2}}\)TPG: An untestability analyzer and test pattern
generator for SEUs in the configuration memory of SRAM-based FPGAs},
journal = {Integr.},
volume = {55},
pages = {85--97},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.03.004},
doi = {10.1016/J.VLSI.2016.03.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BernardeschiCDS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BrennaBBL16,
author = {Stefano Brenna and
Andrea Bonetti and
Andrea Bonfanti and
Andrea L. Lacaita},
title = {An efficient tool for the assisted design of {SAR} ADCs capacitive
DACs},
journal = {Integr.},
volume = {53},
pages = {88--99},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.12.005},
doi = {10.1016/J.VLSI.2015.12.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BrennaBBL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CapuaFL16,
author = {Giulia Di Capua and
Nicola Femia and
Gianpaolo Lisi},
title = {Impact of losses and mismatches on power and efficiency of Wireless
Power Transfer Systems with controlled secondary-side rectifier},
journal = {Integr.},
volume = {55},
pages = {384--392},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.04.005},
doi = {10.1016/J.VLSI.2016.04.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CapuaFL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CasaleiroOF16,
author = {Jo{\~{a}}o Casaleiro and
Lu{\'{\i}}s B. Oliveira and
Igor M. Filanovsky},
title = {A quadrature RC-oscillator with capacitive coupling},
journal = {Integr.},
volume = {52},
pages = {260--271},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.06.006},
doi = {10.1016/J.VLSI.2015.06.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CasaleiroOF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChoL16,
author = {Geunho Cho and
Fabrizio Lombardi},
title = {Design and process variation analysis of CNTFET-based ternary memory
cells},
journal = {Integr.},
volume = {54},
pages = {97--108},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.02.003},
doi = {10.1016/J.VLSI.2016.02.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChoL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChuXW16,
author = {Zhufei Chu and
Yinshui Xia and
Lun{-}Yao Wang},
title = {Multi-supply voltage {(MSV)} driven SoC floorplanning for fast design
convergence},
journal = {Integr.},
volume = {52},
pages = {335--346},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.09.002},
doi = {10.1016/J.VLSI.2015.09.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChuXW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CilardoF16,
author = {Alessandro Cilardo and
Edoardo Fusella},
title = {Design automation for application-specific on-chip interconnects:
{A} survey},
journal = {Integr.},
volume = {52},
pages = {102--121},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.017},
doi = {10.1016/J.VLSI.2015.07.017},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CilardoF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CoyetteEDVG16,
author = {Anthony Coyette and
Baris Esen and
Wim Dobbelaere and
Ronny Vanhooren and
Georges G. E. Gielen},
title = {Automatic generation of test infrastructures for analog integrated
circuits by controllability and observability co-optimization},
journal = {Integr.},
volume = {55},
pages = {393--400},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.05.001},
doi = {10.1016/J.VLSI.2016.05.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CoyetteEDVG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DundarHF16,
author = {G{\"{u}}nhan D{\"{u}}ndar and
Nuno Horta and
Francisco V. Fern{\'{a}}ndez},
title = {Introduction to the special issue on {SMACD} 2015},
journal = {Integr.},
volume = {55},
pages = {293--294},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.09.001},
doi = {10.1016/J.VLSI.2016.09.001},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DundarHF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ElabdK16,
author = {Salma Elabd and
Waleed Khalil},
title = {Impact of technology scaling on the tuning range and phase noise of
mm-wave {CMOS} LC-VCOs},
journal = {Integr.},
volume = {52},
pages = {195--207},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.06.008},
doi = {10.1016/J.VLSI.2015.06.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ElabdK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ElrabaaAAEBA16,
author = {Muhammad E. S. Elrabaa and
Amran Al{-}Aghbari and
Mohammed Alasli and
Aiman El{-}Maleh and
Abdelhafid Bouhraoua and
Mohammad R. Alshayeb},
title = {A low-cost platform for the prototyping and characterization of digital
circuit IPs},
journal = {Integr.},
volume = {54},
pages = {1--9},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.01.005},
doi = {10.1016/J.VLSI.2016.01.005},
timestamp = {Sat, 11 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ElrabaaAAEBA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/EshghabadiBNMM16,
author = {Farshad Eshghabadi and
Fatemeh Banitorfian and
Norlaili Mohd Noh and
Mohd Tafir Mustaffa and
Asrulnizam Bin Abd Manaf},
title = {Post-process die-level electromagnetic field analysis on microwave
{CMOS} low-noise amplifier for first-pass silicon fabrication success},
journal = {Integr.},
volume = {52},
pages = {217--227},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.03.001},
doi = {10.1016/J.VLSI.2015.03.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/EshghabadiBNMM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Ezz-EldinEH16,
author = {Rabab Ezz{-}Eldin and
Magdy A. El{-}Moursy and
Hesham F. A. Hamed},
title = {Corrigendum to "High throughput asynchronous NoC design under high
process variation" [Integr. {VLSI} J. {(2015)} 1-13]},
journal = {Integr.},
volume = {52},
pages = {334},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.11.002},
doi = {10.1016/J.VLSI.2015.11.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Ezz-EldinEH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Fatemi-Behbahani16,
author = {Esmaeil Fatemi{-}Behbahani and
Ebrahim Farshidi and
Karim Ansari{-}Asl},
title = {A new approach to analysis of residue probability density function
in pipelined ADCs},
journal = {Integr.},
volume = {52},
pages = {51--61},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.08.003},
doi = {10.1016/J.VLSI.2015.08.003},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Fatemi-Behbahani16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FiorelliP16,
author = {Rafaella Fiorelli and
Eduardo J. Peral{\'{\i}}as},
title = {Semi-empirical {RF} {MOST} model for {CMOS} 65 nm technologies: Theory,
extraction method and validation},
journal = {Integr.},
volume = {52},
pages = {228--236},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.018},
doi = {10.1016/J.VLSI.2015.07.018},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FiorelliP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FunkeHS16,
author = {Julia Funke and
Stefan Hougardy and
Jan Schneider},
title = {An exact algorithm for wirelength optimal placements in {VLSI} design},
journal = {Integr.},
volume = {52},
pages = {355--366},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.001},
doi = {10.1016/J.VLSI.2015.07.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FunkeHS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GaoKARA16,
author = {Yansong Gao and
Omid Kavehei and
Said F. Al{-}Sarawi and
Damith Chinthana Ranasinghe and
Derek Abbott},
title = {Read operation performance of large selectorless cross-point array
with self-rectifying memristive device},
journal = {Integr.},
volume = {54},
pages = {56--64},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.02.002},
doi = {10.1016/J.VLSI.2016.02.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GaoKARA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GengLLLCGS16,
author = {Hui Geng and
Jianming Liu and
Jinglan Liu and
Pei{-}Wen Luo and
Liang{-}Chia Cheng and
Steven L. Grant and
Yiyu Shi},
title = {Selective body biasing for post-silicon tuning of sub-threshold designs:
{A} semi-infinite programming approach with Incremental Hypercubic
Sampling},
journal = {Integr.},
volume = {55},
pages = {465--473},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.05.007},
doi = {10.1016/J.VLSI.2016.05.007},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GengLLLCGS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GhonoodiNG16,
author = {Hojat Ghonoodi and
Hossein Miar Naimi and
Mohammad Gholami},
title = {Analysis of frequency and amplitude in {CMOS} differential ring oscillators},
journal = {Integr.},
volume = {52},
pages = {253--259},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.004},
doi = {10.1016/J.VLSI.2015.07.004},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GhonoodiNG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Gomez-PauBF16,
author = {{\'{A}}lvaro G{\'{o}}mez{-}Pau and
Luz Balado and
Joan Figueras},
title = {Indirect test of {M-S} circuits using multiple specification band
guarding},
journal = {Integr.},
volume = {55},
pages = {415--424},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.04.007},
doi = {10.1016/J.VLSI.2016.04.007},
timestamp = {Thu, 16 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Gomez-PauBF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Gonzalez-DiazSM16,
author = {Victor R. Gonzalez{-}Diaz and
Luis Abraham S{\'{a}}nchez{-}Gaspariano and
Carlos Mu{\~{n}}iz{-}Montero and
Jose J. Alvarado{-}Pulido},
title = {Improving linearity in {MOS} varactor based VCOs by means of the output
quiescent bias point},
journal = {Integr.},
volume = {55},
pages = {274--280},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.08.003},
doi = {10.1016/J.VLSI.2016.08.003},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Gonzalez-DiazSM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HaghbayanA16,
author = {Mohammad Hashem Haghbayan and
Bijan Alizadeh},
title = {A dynamic specification to automatically debug and correct various
divider circuits},
journal = {Integr.},
volume = {53},
pages = {100--114},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.12.004},
doi = {10.1016/J.VLSI.2015.12.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HaghbayanA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HasanGH16,
author = {Syed Rafay Hasan and
Waqas Gul and
Osman Hasan},
title = {Clock domain crossing {(CDC)} in 3D-SICs: Semi {QDI} asynchronous
vs loosely synchronous},
journal = {Integr.},
volume = {52},
pages = {367--380},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.05.002},
doi = {10.1016/J.VLSI.2015.05.002},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HasanGH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HassanliSDJW16,
author = {Kourosh Hassanli and
Sayed Masoud Sayedi and
Rasoul Dehghani and
Armin Jalili and
J. Jacob Wikner},
title = {A low-power wide tuning-range {CMOS} current-controlled oscillator},
journal = {Integr.},
volume = {55},
pages = {57--66},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.03.001},
doi = {10.1016/J.VLSI.2016.03.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HassanliSDJW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HeTZLWS16,
author = {Kai He and
Sheldon X.{-}D. Tan and
Hengyang Zhao and
Xuexin Liu and
Hai Wang and
Guoyong Shi},
title = {Parallel {GMRES} solver for fast analysis of large linear dynamic
systems on {GPU} platforms},
journal = {Integr.},
volume = {52},
pages = {10--22},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.005},
doi = {10.1016/J.VLSI.2015.07.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HeTZLWS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HojatiY16,
author = {Zeinab Hojati and
Mohammad Yavari},
title = {An NTF-enhanced incremental {\(\Sigma\)}{\(\Delta\)} modulator using
a {SAR} quantizer},
journal = {Integr.},
volume = {55},
pages = {212--219},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.06.006},
doi = {10.1016/J.VLSI.2016.06.006},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HojatiY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HuangLFYSZ16,
author = {Qicheng Huang and
Xiao Li and
Chenlei Fang and
Fan Yang and
Yangfeng Su and
Xuan Zeng},
title = {An aggregating based model order reduction method for power grids},
journal = {Integr.},
volume = {55},
pages = {449--454},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.04.010},
doi = {10.1016/J.VLSI.2016.04.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HuangLFYSZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HuangSCCKT16,
author = {Xin Huang and
Valeriy Sukharev and
Jun{-}Ho Choy and
Marko Chew and
Taeyoung Kim and
Sheldon X.{-}D. Tan},
title = {Electromigration assessment for power grid networks considering temperature
and thermal stress effects},
journal = {Integr.},
volume = {55},
pages = {307--315},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.04.001},
doi = {10.1016/J.VLSI.2016.04.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HuangSCCKT16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HussainVBS16,
author = {Wasim Hussain and
Olivier Valorge and
Yves Blaqui{\`{e}}re and
Yvon Savaria},
title = {A novel spatially configurable differential interface for an electronic
system prototyping platform},
journal = {Integr.},
volume = {55},
pages = {129--137},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.04.008},
doi = {10.1016/J.VLSI.2016.04.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HussainVBS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JiaoD16,
author = {Fanshu Jiao and
Alex Doboli},
title = {Causal reasoning mining approach to analog circuit verification},
journal = {Integr.},
volume = {55},
pages = {376--383},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.04.002},
doi = {10.1016/J.VLSI.2016.04.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JiaoD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JiaoQK16,
author = {Hailong Jiao and
Yongmin Qiu and
Volkan Kursun},
title = {Variability-aware 7T {SRAM} circuit with low leakage high data stability
{SLEEP} mode},
journal = {Integr.},
volume = {53},
pages = {68--79},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.12.003},
doi = {10.1016/J.VLSI.2015.12.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JiaoQK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JunsangsriHL16,
author = {Pilin Junsangsri and
Jie Han and
Fabrizio Lombardi},
title = {Design of a hybrid non-volatile {SRAM} cell for concurrent {SEU} detection
and correction},
journal = {Integr.},
volume = {52},
pages = {156--167},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.09.005},
doi = {10.1016/J.VLSI.2015.09.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JunsangsriHL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KamranN16,
author = {Arezoo Kamran and
Zainalabedin Navabi},
title = {Stochastic testing of processing cores in a many-core architecture},
journal = {Integr.},
volume = {55},
pages = {183--193},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.06.005},
doi = {10.1016/J.VLSI.2016.06.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KamranN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KarimlouJS16,
author = {Atiyeh Karimlou and
Roya Jafarnejad and
Jafar Sobhi},
title = {An Inductor-less Sub-mW Low Noise Amplifier for Wireless Sensor Network
Applications},
journal = {Integr.},
volume = {52},
pages = {316--322},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.009},
doi = {10.1016/J.VLSI.2015.07.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KarimlouJS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KchaouGKPFF16,
author = {O. Bellaaj Kchaou and
Amel Garbaya and
Mouna Kotti and
Pedro Pereira and
Mourad Fakhfakh and
M. Helena Fino},
title = {Sensitivity aware {NSGA-II} based Pareto front generation for the
optimal sizing of analog circuits},
journal = {Integr.},
volume = {55},
pages = {220--226},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.07.001},
doi = {10.1016/J.VLSI.2016.07.001},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KchaouGKPFF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimJK16,
author = {Juyeon Kim and
Deokjin Joo and
Taewhan Kim},
title = {Optimal utilization of adjustable delay clock buffers for timing correction
in designs with multiple power modes},
journal = {Integr.},
volume = {52},
pages = {91--101},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.08.005},
doi = {10.1016/J.VLSI.2015.08.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KimJK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimPKS16,
author = {Sangmin Kim and
Seungwhun Paik and
Seokhyeong Kang and
Youngsoo Shin},
title = {Wakeup scheduling and its buffered tree synthesis for power gating
circuits},
journal = {Integr.},
volume = {53},
pages = {157--170},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.12.008},
doi = {10.1016/J.VLSI.2015.12.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KimPKS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KomurcuPD16,
author = {Giray K{\"{o}}m{\"{u}}rc{\"{u}} and
Ali Emre Pusane and
G{\"{u}}nhan D{\"{u}}ndar},
title = {Effects of aging and compensation mechanisms in ordering based RO-PUFs},
journal = {Integr.},
volume = {52},
pages = {71--76},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.08.004},
doi = {10.1016/J.VLSI.2015.08.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KomurcuPD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KuangY16,
author = {Jian Kuang and
Evangeline F. Y. Young},
title = {Row-structure stencil planning approaches for E-beam lithography with
overlapped characters},
journal = {Integr.},
volume = {55},
pages = {232--245},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.07.002},
doi = {10.1016/J.VLSI.2016.07.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KuangY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KumarAL16,
author = {T. Nandha Kumar and
Haider A. F. Almurib and
Fabrizio Lombardi},
title = {Design of a memristor-based look-up table {(LUT)} for low-energy operation
of FPGAs},
journal = {Integr.},
volume = {55},
pages = {1--11},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.02.005},
doi = {10.1016/J.VLSI.2016.02.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KumarAL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LegerB16,
author = {Gildas L{\'{e}}ger and
Manuel J. Barrag{\'{a}}n},
title = {Brownian distance correlation-directed search: {A} fast feature selection
technique for alternate test},
journal = {Integr.},
volume = {55},
pages = {401--414},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.05.003},
doi = {10.1016/J.VLSI.2016.05.003},
timestamp = {Wed, 28 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LegerB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiC16,
author = {Yin Li and
Yi{-}yang Chen},
title = {New bit-parallel Montgomery multiplier for trinomials using squaring
operation},
journal = {Integr.},
volume = {52},
pages = {142--155},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.09.007},
doi = {10.1016/J.VLSI.2015.09.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiLZ16,
author = {He Li and
Qiang Liu and
Jiliang Zhang},
title = {A survey of hardware Trojan threat and defense},
journal = {Integr.},
volume = {55},
pages = {426--437},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.01.004},
doi = {10.1016/J.VLSI.2016.01.004},
timestamp = {Mon, 06 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiLZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiTW16,
author = {Xin Li and
Sheldon X.{-}D. Tan and
Yu Wang},
title = {Editorial: Special Issue on The 14th International Conference on Computer-Aided
Design and Computer Graphics (CAD/Graphics 2015)},
journal = {Integr.},
volume = {55},
pages = {425},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.09.002},
doi = {10.1016/J.VLSI.2016.09.002},
timestamp = {Thu, 22 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiTW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LicciardoBPB16,
author = {Gian Domenico Licciardo and
Thomas Boesch and
Danilo Pau and
Luigi Di Benedetto},
title = {Frame buffer-less stream processor for accurate real-time interest
point detection},
journal = {Integr.},
volume = {54},
pages = {10--23},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.12.010},
doi = {10.1016/J.VLSI.2015.12.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LicciardoBPB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuPW16,
author = {Renzhi Liu and
Lawrence T. Pileggi and
Jeffrey A. Weldon},
title = {A wideband {RF} receiver with extended statistical element selection
based harmonic rejection calibration},
journal = {Integr.},
volume = {52},
pages = {185--194},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.06.001},
doi = {10.1016/J.VLSI.2015.06.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiuPW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuQ16,
author = {Bao Liu and
Gang Qu},
title = {{VLSI} supply chain security risks and mitigation techniques: {A}
survey},
journal = {Integr.},
volume = {55},
pages = {438--448},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.03.002},
doi = {10.1016/J.VLSI.2016.03.002},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiuQ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LourencoMCPH16,
author = {Nuno Louren{\c{c}}o and
Ricardo Martins and
Ant{\'{o}}nio Canelas and
Ricardo Povoa and
Nuno Horta},
title = {{AIDA:} Layout-aware analog circuit-level sizing with in-loop layout
generation},
journal = {Integr.},
volume = {55},
pages = {316--329},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.04.009},
doi = {10.1016/J.VLSI.2016.04.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LourencoMCPH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaZLZ16,
author = {Ning Ma and
Zhuo Zou and
Zhonghai Lu and
Li{-}Rong Zheng},
title = {Design and implementation of multi-mode routers for large-scale inter-core
networks},
journal = {Integr.},
volume = {53},
pages = {1--13},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.10.002},
doi = {10.1016/J.VLSI.2015.10.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MaZLZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MahdianiSS16,
author = {Hoda Mahdiani and
Saeed Safari and
Mostafa E. Salehi},
title = {Fast and accurate FPGA-based framework for processor architecture
vulnerability analysis},
journal = {Integr.},
volume = {53},
pages = {14--26},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.11.005},
doi = {10.1016/J.VLSI.2015.11.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MahdianiSS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MartinsPLH16,
author = {Ricardo Martins and
Ricardo Povoa and
Nuno Louren{\c{c}}o and
Nuno Horta},
title = {Current-flow and current-density-aware multi-objective optimization
of analog {IC} placement},
journal = {Integr.},
volume = {55},
pages = {295--306},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.05.008},
doi = {10.1016/J.VLSI.2016.05.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MartinsPLH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MayilavelaneB16,
author = {Aroutchelvame Mayilavelane and
Brian Berscheid},
title = {A Fast {FIR} filtering technique for multirate filters},
journal = {Integr.},
volume = {52},
pages = {62--70},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.011},
doi = {10.1016/J.VLSI.2015.07.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MayilavelaneB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MazumderHEZXF16,
author = {Pinaki Mazumder and
D. Hu and
Idongesit E. Ebong and
Xu Zhang and
Z. Xu and
Silvia Ferrari},
title = {Digital implementation of a virtual insect trained by spike-timing
dependent plasticity},
journal = {Integr.},
volume = {54},
pages = {109--117},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.01.002},
doi = {10.1016/J.VLSI.2016.01.002},
timestamp = {Thu, 04 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MazumderHEZXF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MohantyMSS16,
author = {Basant Kumar Mohanty and
Pramod Kumar Meher and
Subodh Kumar Singhal and
M. N. S. Swamy},
title = {A high-performance {VLSI} architecture for reconfigurable {FIR} using
distributed arithmetic},
journal = {Integr.},
volume = {54},
pages = {37--46},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.01.006},
doi = {10.1016/J.VLSI.2016.01.006},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MohantyMSS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MosaffaMS16,
author = {Mahdi Mosaffa and
Siamak Mohammadi and
Saeed Safari},
title = {Statistical analysis of asynchronous pipelines in presence of process
variation using formal models},
journal = {Integr.},
volume = {55},
pages = {98--117},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.04.003},
doi = {10.1016/J.VLSI.2016.04.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MosaffaMS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MoyalLTF16,
author = {Lior Moyal and
Itamar Levi and
Adam Teman and
Alexander Fish},
title = {Synthesis of Dual Mode Logic},
journal = {Integr.},
volume = {55},
pages = {246--253},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.07.004},
doi = {10.1016/J.VLSI.2016.07.004},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MoyalLTF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NahtigalS16,
author = {Uros Nahtigal and
Drago Strle},
title = {Design, simulation, and implementation of an integrated, hybrid photocurrent-to-digital
converter in {CMOS} technology},
journal = {Integr.},
volume = {55},
pages = {254--264},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.08.002},
doi = {10.1016/J.VLSI.2016.08.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NahtigalS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/NasserianKMM16,
author = {Mahshid Nasserian and
Mohammad Kafi Kangi and
Mohammad Maymandi{-}Nejad and
Farshad Moradi},
title = {A low-power fast tag comparator by modifying charging scheme of wide
fan-in dynamic {OR} gates},
journal = {Integr.},
volume = {52},
pages = {129--141},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.09.004},
doi = {10.1016/J.VLSI.2015.09.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/NasserianKMM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OrcioniGSVC16,
author = {Simone Orcioni and
Marco Giammarini and
Cristiano Scavongelli and
Giovanni B. Vece and
Massimo Conti},
title = {Energy estimation in SystemC with Powersim},
journal = {Integr.},
volume = {55},
pages = {118--128},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.04.006},
doi = {10.1016/J.VLSI.2016.04.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/OrcioniGSVC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PakFD16,
author = {Murat Pak and
Francisco V. Fern{\'{a}}ndez and
G{\"{u}}nhan D{\"{u}}ndar},
title = {Comparison of QMC-based yield-aware pareto front techniques for multi-objective
robust analog synthesis},
journal = {Integr.},
volume = {55},
pages = {357--365},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.04.004},
doi = {10.1016/J.VLSI.2016.04.004},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PakFD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PandeyCPTFLH16,
author = {Mrinalinee Pandey and
Ant{\'{o}}nio Canelas and
Ricardo P{\'{o}}voa and
Jorge Alves Torres and
Jo{\~{a}}o Costa Freire and
Nuno Louren{\c{c}}o and
Nuno Horta},
title = {Design and application of a {CMOS} active inductor at Ku band based
on a multi-objective optimizer},
journal = {Integr.},
volume = {55},
pages = {330--340},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.06.007},
doi = {10.1016/J.VLSI.2016.06.007},
timestamp = {Thu, 28 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PandeyCPTFLH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ParkCHS16,
author = {Sun{-}Mi Park and
Ku{-}Young Chang and
Dowon Hong and
Changho Seo},
title = {Explicit formulae for Mastrovito matrix and its corresponding Toeplitz
matrix for all irreducible pentanomials using shifted polynomial basis},
journal = {Integr.},
volume = {53},
pages = {27--38},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.11.004},
doi = {10.1016/J.VLSI.2015.11.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ParkCHS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PashakiS16,
author = {Elahe Rastegar Pashaki and
Majid Shalchian},
title = {Design and simulation of an ultra-low power high performance {CMOS}
logic: {DMTGDI}},
journal = {Integr.},
volume = {55},
pages = {194--201},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.06.004},
doi = {10.1016/J.VLSI.2016.06.004},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PashakiS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PerezCMRLGT16,
author = {Jos{\'{e}}{-}Cruz Nu{\~{n}}ez P{\'{e}}rez and
Jos{\'{e}} Ricardo C{\'{a}}rdenas{-}Valdez and
Katherine Montoya{-}Villegas and
J. Apolinar Reynoso{-}Hern{\'{a}}ndez and
Jos{\'{e}} Ra{\'{u}}l Loo{-}Yau and
Christian Gontrand and
Esteban Tlelo{-}Cuautle},
title = {FPGA-based test bed for measurement of {AM/AM} and {AM/PM} distortion
and modeling memory effects in {RF} PAs},
journal = {Integr.},
volume = {52},
pages = {291--300},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.06.007},
doi = {10.1016/J.VLSI.2015.06.007},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PerezCMRLGT16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PettenghiCMS16,
author = {H{\'{e}}ctor Pettenghi and
Ricardo Chaves and
Roberto de Matos and
Leonel Sousa},
title = {Method for designing two levels {RNS} reverse converters for large
dynamic ranges},
journal = {Integr.},
volume = {55},
pages = {22--29},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.02.004},
doi = {10.1016/J.VLSI.2016.02.004},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/PettenghiCMS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PirbastiFP16,
author = {Marzieh Ranjbar Pirbasti and
Mahdi Fazeli and
Ahmad Patooghy},
title = {Phase Change Memory lifetime enhancement via online data swapping},
journal = {Integr.},
volume = {54},
pages = {47--55},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.01.003},
doi = {10.1016/J.VLSI.2016.01.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PirbastiFP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PovoaBLH16,
author = {Ricardo Povoa and
Ivan Bastos and
Nuno Louren{\c{c}}o and
Nuno Horta},
title = {Automatic synthesis of {RF} front-end blocks using multi-objective
evolutionary techniques},
journal = {Integr.},
volume = {52},
pages = {243--252},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.04.005},
doi = {10.1016/J.VLSI.2015.04.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PovoaBLH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RamosPF16,
author = {Filipe Guimar{\~{a}}es Russo Ramos and
Tales Cleber Pimenta and
Luis Henrique de Carvalho Ferreira},
title = {A mixed-signal pulse width modulator for portable {SMPS} applications},
journal = {Integr.},
volume = {55},
pages = {265--273},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.07.005},
doi = {10.1016/J.VLSI.2016.07.005},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RamosPF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RashidiSF16,
author = {Bahram Rashidi and
Sayed Masoud Sayedi and
Reza Rezaeian Farashahi},
title = {An efficient and high-speed {VLSI} implementation of optimal normal
basis multiplication over GF(2\({}^{\mbox{m}}\))},
journal = {Integr.},
volume = {55},
pages = {138--154},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.05.006},
doi = {10.1016/J.VLSI.2016.05.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RashidiSF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ReimannSR16,
author = {Tiago Reimann and
Cliff C. N. Sze and
Ricardo Reis},
title = {Challenges of cell selection algorithms in industrial high performance
microprocessor designs},
journal = {Integr.},
volume = {52},
pages = {347--354},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.09.001},
doi = {10.1016/J.VLSI.2015.09.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ReimannSR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RioGSBB16,
author = {David del Rio and
I{\~{n}}aki Gurutzeaga and
H{\'{e}}ctor Solar and
Andoni Beriain and
Roc Berenguer},
title = {Layout-aware design methodology for a 75 GHz power amplifier in a
55 nm SiGe technology},
journal = {Integr.},
volume = {52},
pages = {208--216},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.010},
doi = {10.1016/J.VLSI.2015.07.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RioGSBB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RocaS16,
author = {Elisenda Roca and
Javier J. Sieiro},
title = {Introduction to the special issue on Radio Frequency Integrated Circuits
{(RFIC)} design techniques},
journal = {Integr.},
volume = {52},
pages = {183--184},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.11.001},
doi = {10.1016/J.VLSI.2015.11.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RocaS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SaberkariKSY16,
author = {Alireza Saberkari and
Shima Kazemi and
Vahideh Shirmohammadli and
Mustapha C. E. Yagoub},
title = {g\({}_{\mbox{m}}\)-boosted flat gain {UWB} low noise amplifier with
active inductor-based input matching network},
journal = {Integr.},
volume = {52},
pages = {323--333},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.06.002},
doi = {10.1016/J.VLSI.2015.06.002},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SaberkariKSY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SaberkariZMA16,
author = {Alireza Saberkari and
Saman Ziabakhsh and
Herminio Mart{\'{\i}}nez and
Eduard Alarc{\'{o}}n},
title = {Active inductor-based tunable impedance matching network for {RF}
power amplifier application},
journal = {Integr.},
volume = {52},
pages = {301--308},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.013},
doi = {10.1016/J.VLSI.2015.07.013},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SaberkariZMA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SafariNK16,
author = {Azadeh Safari and
Cheeckottu Vayalil Niras and
Yinan Kong},
title = {Power-performance enhancement of two-dimensional RNS-based {DWT} image
processor using static voltage scaling},
journal = {Integr.},
volume = {53},
pages = {145--156},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.12.006},
doi = {10.1016/J.VLSI.2015.12.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SafariNK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SaglamdemirBDS16,
author = {Muharrem Orkun Saglamdemir and
G{\"{o}}nen{\c{c}} Berkol and
G{\"{u}}nhan D{\"{u}}ndar and
Alper Sen},
title = {An analog behavioral equivalence boundary search methodology for simulink
models and circuit level designs utilizing evolutionary computation},
journal = {Integr.},
volume = {55},
pages = {366--375},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.05.005},
doi = {10.1016/J.VLSI.2016.05.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SaglamdemirBDS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SaitS16,
author = {Sadiq M. Sait and
Umair F. Siddiqi},
title = {A stochastic evolution algorithm based 2D {VLSI} global router},
journal = {Integr.},
volume = {53},
pages = {115--125},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.12.007},
doi = {10.1016/J.VLSI.2015.12.007},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SaitS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SalimiDN16,
author = {Atefeh Salimi and
Rasoul Dehghani and
Abdolreza Nabavi},
title = {A digital predistortion assisted hybrid supply modulator for envelope
tracking power amplifiers},
journal = {Integr.},
volume = {52},
pages = {282--290},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.04.002},
doi = {10.1016/J.VLSI.2015.04.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SalimiDN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SallemPFF16,
author = {Amin Sallem and
Pedro Pereira and
M. Helena Fino and
Mourad Fakhfakh},
title = {A hybrid approach for the sensitivity analysis of integrated inductors},
journal = {Integr.},
volume = {52},
pages = {237--242},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.04.006},
doi = {10.1016/J.VLSI.2015.04.006},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SallemPFF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SantosMV16,
author = {Pedro Mendon{\c{c}}a dos Santos and
Lu{\'{\i}}s Mendes and
Jo{\~{a}}o Caldinhas Vaz},
title = {Substrate noise isolation improvement in a single-well standard {CMOS}
process},
journal = {Integr.},
volume = {52},
pages = {122--128},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.09.006},
doi = {10.1016/J.VLSI.2015.09.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SantosMV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SarfrazC16,
author = {Khawar Sarfraz and
Mansun Chan},
title = {A compact low-power 4-port register file with grounded write bitlines
and single-ended read operations},
journal = {Integr.},
volume = {55},
pages = {12--21},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.02.008},
doi = {10.1016/J.VLSI.2016.02.008},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SarfrazC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SethiHH16,
author = {Muhammad Athar Javed Sethi and
Fawnizu Azmadi Hussin and
Nor Hisham Hamid},
title = {Bio-inspired NoC fault tolerant techniques using guaranteed throughput
and best effort services},
journal = {Integr.},
volume = {54},
pages = {65--96},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.02.001},
doi = {10.1016/J.VLSI.2016.02.001},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SethiHH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShapiroAKJFF16,
author = {Alexander E. Shapiro and
Francois Atallah and
Kyugseok Kim and
Jihoon Jeong and
Jeff Fischer and
Eby G. Friedman},
title = {Adaptive power gating of 32-bit Kogge Stone adder},
journal = {Integr.},
volume = {53},
pages = {80--87},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.12.001},
doi = {10.1016/J.VLSI.2015.12.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShapiroAKJFF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShokouhifarJ16,
author = {Mohammad Shokouhifar and
Ali Jalali},
title = {Two-stage fuzzy inference system for symbolic simplification of analog
circuits},
journal = {Integr.},
volume = {55},
pages = {281--292},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.08.004},
doi = {10.1016/J.VLSI.2016.08.004},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ShokouhifarJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/StatterC16,
author = {Yishai Statter and
Tom Chen},
title = {A novel high-throughput method for table look-up based analog design
automation},
journal = {Integr.},
volume = {52},
pages = {168--181},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.09.003},
doi = {10.1016/J.VLSI.2015.09.003},
timestamp = {Mon, 02 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/StatterC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/StatterC16a,
author = {Yishai Statter and
Tom Chen},
title = {{\(\Gamma\)} (Gamma): {A} SaaS-enabled fast and accurate analog design
System},
journal = {Integr.},
volume = {55},
pages = {67--84},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.03.003},
doi = {10.1016/J.VLSI.2016.03.003},
timestamp = {Mon, 02 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/StatterC16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SunXTZR16,
author = {Jin Sun and
Liang Xiao and
Jiangshan Tian and
He Zhou and
Janet Roveda},
title = {Surrogating circuit design solutions with robustness metrics},
journal = {Integr.},
volume = {52},
pages = {1--9},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.015},
doi = {10.1016/J.VLSI.2015.07.015},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SunXTZR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TabriziBSR16,
author = {Aysa Fakheri Tabrizi and
Laleh Behjat and
William Swartz and
Logan M. Rakai},
title = {A fast force-directed simulated annealing for 3D {IC} partitioning},
journal = {Integr.},
volume = {55},
pages = {202--211},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.06.003},
doi = {10.1016/J.VLSI.2016.06.003},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TabriziBSR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TorabiJ16,
author = {Zeinab Torabi and
Ghassem Jaberipur},
title = {Fast low energy {RNS} comparators for 4-moduli sets \{2\({}^{\mbox{n}}\){\(\pm\)}1,
2\({}^{\mbox{n}}\), m\} with m{\(\in\)}\{2\({}^{\mbox{n+1}}\){\(\pm\)}1,
2\({}^{\mbox{n-1}}\)-1\}},
journal = {Integr.},
volume = {55},
pages = {155--161},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.05.009},
doi = {10.1016/J.VLSI.2016.05.009},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TorabiJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Toro-FriasMMCRR16,
author = {Antonio Toro{-}Fr{\'{\i}}as and
Pablo Mart{\'{\i}}n{-}Lloret and
Javier Mart{\'{\i}}n{-}Mart{\'{\i}}nez and
Rafael Castro{-}L{\'{o}}pez and
Elisenda Roca and
Rosana Rodr{\'{\i}}guez and
Montserrat Nafr{\'{\i}}a and
Francisco V. Fern{\'{a}}ndez},
title = {Reliability simulation for analog ICs: Goals, solutions, and challenges},
journal = {Integr.},
volume = {55},
pages = {341--348},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.05.002},
doi = {10.1016/J.VLSI.2016.05.002},
timestamp = {Thu, 11 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Toro-FriasMMCRR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TorresF16,
author = {Jorge Alves Torres and
Jo{\~{a}}o Costa Freire},
title = {K Band SiGe {HBT} single ended active inductors},
journal = {Integr.},
volume = {52},
pages = {272--281},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.016},
doi = {10.1016/J.VLSI.2015.07.016},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TorresF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TsaiTHH16,
author = {Tsung{-}Han Tsai and
Pei{-}Yun Tsai and
Meng{-}Yuan Huang and
Li{-}Yang Huang},
title = {{WHDVI:} {A} wireless high definition video interface technique for
digital home},
journal = {Integr.},
volume = {53},
pages = {138--144},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.11.003},
doi = {10.1016/J.VLSI.2015.11.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/TsaiTHH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangTTLWC16,
author = {Po{-}Hao Wang and
Shang{-}Jen Tsai and
Rizal Tanjung and
Tay{-}Jyi Lin and
Jinn{-}Shyan Wang and
Tien{-}Fu Chen},
title = {Cross-matching caches: Dynamic timing calibration and bit-level timing-failure
mask caches to reduce timing discrepancies with low voltage processors},
journal = {Integr.},
volume = {54},
pages = {24--36},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.01.001},
doi = {10.1016/J.VLSI.2016.01.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangTTLWC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WilleSSD16,
author = {Robert Wille and
Eleonora Sch{\"{o}}nborn and
Mathias Soeken and
Rolf Drechsler},
title = {SyReC: {A} hardware description language for the specification and
synthesis of reversible circuits},
journal = {Integr.},
volume = {53},
pages = {39--53},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.10.001},
doi = {10.1016/J.VLSI.2015.10.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WilleSSD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XingLHZH16,
author = {Lidong Xing and
Tao Li and
Hucai Huang and
Qingsheng Zhang and
Jungang Han},
title = {Efficient modeling and analysis of energy consumption for 3D graphics
rendering},
journal = {Integr.},
volume = {55},
pages = {455--464},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.02.009},
doi = {10.1016/J.VLSI.2016.02.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/XingLHZH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YanHHWM16,
author = {Zhiting Yan and
Guanghui He and
Weifeng He and
Shuaijie Wang and
Zhigang Mao},
title = {High performance parallel turbo decoder with configurable interleaving
network for {LTE} application},
journal = {Integr.},
volume = {52},
pages = {77--90},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.05.003},
doi = {10.1016/J.VLSI.2015.05.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YanHHWM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangWA16,
author = {Xiaokun Yang and
Nansong Wu and
Jean H. Andrian},
title = {A novel bus transfer mode {(AS} transfer) and a performance evaluation
methodology},
journal = {Integr.},
volume = {52},
pages = {23--33},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.07.012},
doi = {10.1016/J.VLSI.2015.07.012},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YangWA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangYZP16,
author = {Zhiming Yang and
Yang Yu and
Chengcheng Zhang and
Xiyuan Peng},
title = {NBTI-aware adaptive minimum leakage vector selection using a linear
programming approach},
journal = {Integr.},
volume = {53},
pages = {126--137},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.12.009},
doi = {10.1016/J.VLSI.2015.12.009},
timestamp = {Thu, 31 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/YangYZP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhangYG16,
author = {Hao Zhang and
Dongyi Ye and
Wenzhong Guo},
title = {A heuristic for constructing a rectilinear Steiner tree by reusing
routing resources over obstacles},
journal = {Integr.},
volume = {55},
pages = {162--175},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.06.001},
doi = {10.1016/J.VLSI.2016.06.001},
timestamp = {Mon, 08 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhangYG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhouLW016,
author = {Jun Zhou and
Huawei Li and
Tiancheng Wang and
Xiaowei Li},
title = {{LOFT:} {A} low-overhead fault-tolerant routing scheme for 3D NoCs},
journal = {Integr.},
volume = {52},
pages = {41--50},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.08.002},
doi = {10.1016/J.VLSI.2015.08.002},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ZhouLW016.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhuQT16,
author = {Jingyang Zhu and
Zhiliang Qian and
Chi{-}Ying Tsui},
title = {BiLink: {A} high performance NoC router architecture using bi-directional
link with double data rate},
journal = {Integr.},
volume = {55},
pages = {30--42},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2016.02.006},
doi = {10.1016/J.VLSI.2016.02.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhuQT16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/0001CCB15,
author = {Sudip Roy and
Partha Pratim Chakrabarti and
Krishnendu Chakrabarty and
Bhargab B. Bhattacharya},
title = {Waste-aware single-target dilution of a biochemical fluid using digital
microfluidic biochips},
journal = {Integr.},
volume = {51},
pages = {194--207},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.12.004},
doi = {10.1016/J.VLSI.2014.12.004},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/0001CCB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AjazL15,
author = {Sabooh Ajaz and
Hanho Lee},
title = {Efficient multi-Gb/s multi-mode {LDPC} decoder architecture for {IEEE}
802.11ad applications},
journal = {Integr.},
volume = {51},
pages = {21--36},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2015.05.001},
doi = {10.1016/J.VLSI.2015.05.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AjazL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AlistarP15,
author = {Mirela Alistar and
Paul Pop},
title = {Synthesis of biochemical applications on digital microfluidic biochips
with operation execution time variability},
journal = {Integr.},
volume = {51},
pages = {158--168},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2015.02.004},
doi = {10.1016/J.VLSI.2015.02.004},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AlistarP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AnsariAENAP15,
author = {Mohammad Ansari and
Hassan Afzali{-}Kusha and
Behzad Ebrahimi and
Zainalabedin Navabi and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {A near-threshold 7T {SRAM} cell with high write and read margins and
low write time for sub-20 nm FinFET technologies},
journal = {Integr.},
volume = {50},
pages = {91--106},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2015.02.002},
doi = {10.1016/J.VLSI.2015.02.002},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AnsariAENAP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Asyaei15,
author = {Mohammad Asyaei},
title = {A new leakage-tolerant domino circuit using voltage-comparison for
wide fan-in gates in deep sub-micron technology},
journal = {Integr.},
volume = {51},
pages = {61--71},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2015.06.003},
doi = {10.1016/J.VLSI.2015.06.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Asyaei15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BashizadeS15,
author = {Ramin Bashizade and
Hamid Sarbazi{-}Azad},
title = {{P2R2:} Parallel Pseudo-Round-Robin arbiter for high performance NoCs},
journal = {Integr.},
volume = {50},
pages = {173--182},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.11.002},
doi = {10.1016/J.VLSI.2014.11.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BashizadeS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Bayrakci15,
author = {Alp Arslan Bayrakci},
title = {Stochastic logical effort as a variation aware delay model to estimate
timing yield},
journal = {Integr.},
volume = {48},
pages = {101--108},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.07.003},
doi = {10.1016/J.VLSI.2014.07.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Bayrakci15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Ben-ItzhakCK15,
author = {Yaniv Ben{-}Itzhak and
Israel Cidon and
Avinoam Kolodny},
title = {Average latency and link utilization analysis of heterogeneous wormhole
NoCs},
journal = {Integr.},
volume = {51},
pages = {92--106},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2015.07.002},
doi = {10.1016/J.VLSI.2015.07.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Ben-ItzhakCK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Cardenas-Valdez15,
author = {Jos{\'{e}} Ricardo C{\'{a}}rdenas{-}Valdez and
Jos{\'{e}}{-}Cruz Nu{\~{n}}ez P{\'{e}}rez and
Jos{\'{e}} Alejandro Galaviz{-}Aguilar and
Andr{\'{e}}s Calvillo{-}T{\'{e}}llez and
Christian Gontrand and
J. Apolinar Reynoso{-}Hern{\'{a}}ndez and
Esteban Tlelo{-}Cuautle},
title = {Modeling memory effects in {RF} power amplifiers applied to a digital
pre-distortion algorithm and emulated on a {DSP-FPGA} board},
journal = {Integr.},
volume = {49},
pages = {49--64},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.12.005},
doi = {10.1016/J.VLSI.2014.12.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Cardenas-Valdez15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CasuM15,
author = {Mario R. Casu and
Paolo Mantovani},
title = {A synchronous latency-insensitive {RISC} for better than worst-case
design},
journal = {Integr.},
volume = {48},
pages = {72--82},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.01.003},
doi = {10.1016/J.VLSI.2014.01.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CasuM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChandrasettyA15,
author = {Vikram Arkalgud Chandrasetty and
Syed Mahfuzul Aziz},
title = {Resource efficient {LDPC} decoders for multimedia communication},
journal = {Integr.},
volume = {48},
pages = {213--220},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.09.002},
doi = {10.1016/J.VLSI.2014.09.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChandrasettyA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CharieteBGW15,
author = {Abderrahim Chariete and
Mohamed Bakhouya and
Jaafar Gaber and
Maxime Wack},
title = {A design space exploration methodology for customizing on-chip communication
architectures: Towards fractal NoCs},
journal = {Integr.},
volume = {50},
pages = {158--172},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.11.007},
doi = {10.1016/J.VLSI.2014.11.007},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CharieteBGW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenX15,
author = {Chunhong Chen and
Ran Xiao},
title = {A fast model for analysis and improvement of gate-level circuit reliability},
journal = {Integr.},
volume = {50},
pages = {107--115},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2015.02.005},
doi = {10.1016/J.VLSI.2015.02.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChenX15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CondoMRM15,
author = {Carlo Condo and
Maurizio Martina and
Massimo Ruo Roch and
Guido Masera},
title = {Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative
channel code decoder architectures},
journal = {Integr.},
volume = {50},
pages = {139--146},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.11.003},
doi = {10.1016/J.VLSI.2014.11.003},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CondoMRM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CorsonelloFP15,
author = {Pasquale Corsonello and
Fabio Frustaci and
Stefania Perri},
title = {Power supply noise in accurate delay model for the sub-threshold domain},
journal = {Integr.},
volume = {50},
pages = {127--136},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2015.02.001},
doi = {10.1016/J.VLSI.2015.02.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/CorsonelloFP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DaneshtalabBS15,
author = {Masoud Daneshtalab and
Nader Bagherzadeh and
Hamid Sarbazi{-}Azad},
title = {On-chip parallel and network-based systems},
journal = {Integr.},
volume = {50},
pages = {137--138},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2015.04.004},
doi = {10.1016/J.VLSI.2015.04.004},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DaneshtalabBS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Ezz-EldinEH15,
author = {Rabab Ezz{-}Eldin and
Magdy A. El{-}Moursy and
Hesham F. A. Hamed},
title = {High Throughput Asynchronous NoC Design under High Process Variation},
journal = {Integr.},
volume = {49},
pages = {1--13},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.10.006},
doi = {10.1016/J.VLSI.2014.10.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Ezz-EldinEH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FarkhaniPM15,
author = {Hooman Farkhani and
Ali Peiravi and
Farshad Moradi},
title = {A new write assist technique for {SRAM} design in 65 nm {CMOS} technology},
journal = {Integr.},
volume = {50},
pages = {16--27},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2015.01.001},
doi = {10.1016/J.VLSI.2015.01.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FarkhaniPM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
retrieved on 2024-06-18 04:45 CEST from data curated by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
