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@inproceedings{DBLP:conf/glvlsi/AbdulkarimS07,
author = {Osman Musa Abdulkarim and
Maitham Shams},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A symmetric mos current-mode logic universal gate for high speed applications},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {212--215},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228839},
doi = {10.1145/1228784.1228839},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/AbdulkarimS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AgostaBS07,
author = {Giovanni Agosta and
Francesco Bruschi and
Donatella Sciuto},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {An efficient cost-based canonical form for Boolean matching},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {445--448},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228889},
doi = {10.1145/1228784.1228889},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/AgostaBS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AgrawalSOV07,
author = {Prashant Agrawal and
R. Srinivasa and
Ajit N. Oke and
Saurabh Vijay},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A path based modeling approach for dynamic power estimation},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {588--593},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228922},
doi = {10.1145/1228784.1228922},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/AgrawalSOV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AltunK07,
author = {Mustafa Altun and
Hakan Kuntman},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {High {CMRR} current mode operational amplifier with a novel class
{AB} input stage},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {192--195},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228834},
doi = {10.1145/1228784.1228834},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/AltunK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AminzadehD07,
author = {Hamed Aminzadeh and
Mohammad Danaie},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Systematic design of two-stage operational amplifiers based on settling
time and open-loop constraints},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {497--500},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228902},
doi = {10.1145/1228784.1228902},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/AminzadehD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AminzadehS07,
author = {Soheil Aminzadeh and
Saeed Safari},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Co-evolutionary high-level test synthesis},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {67--72},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228805},
doi = {10.1145/1228784.1228805},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/AminzadehS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AroraKW07,
author = {Himanshu Arora and
Nikolaus Klemmer and
Patrick D. Wolf},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A 900 MHz {ISM} band mash-12 fractional-n frequency synthesizer for
5-Mbps data transmission},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {381--386},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228875},
doi = {10.1145/1228784.1228875},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/AroraKW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BarrosGH07,
author = {Manuel F. M. Barros and
Jorge Guilherme and
Nuno Horta},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {{GA-SVM} feasibility model and optimization kernel applied to analog
{IC} design automation},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {469--472},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228895},
doi = {10.1145/1228784.1228895},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/BarrosGH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BernardiGMRS07,
author = {Paolo Bernardi and
Filippo Gandino and
Bartolomeo Montrucchio and
Maurizio Rebaudengo and
Erwing Ricardo Sanchez},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Design of an {UHF} {RFID} transponder for secure authentication},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {387--392},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228876},
doi = {10.1145/1228784.1228876},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/BernardiGMRS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BernardiGR07,
author = {Paolo Bernardi and
Michelangelo Grosso and
Matteo Sonza Reorda},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Hardware-accelerated path-delay fault grading of functional test programs
for processor-based systems},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {411--416},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228881},
doi = {10.1145/1228784.1228881},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/BernardiGR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BernasconiCC07,
author = {Anna Bernasconi and
Valentina Ciriani and
Roberto Cordone},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {An approximation algorithm for fully testable kEP-SOP networks},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {417--422},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228883},
doi = {10.1145/1228784.1228883},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/BernasconiCC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BolchiniQS07,
author = {Cristiana Bolchini and
Davide Quarta and
Marco D. Santambrogio},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {{SEU} mitigation for sram-based fpgas through dynamic partial reconfiguration},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {55--60},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228803},
doi = {10.1145/1228784.1228803},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/BolchiniQS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ButzenRKR07,
author = {Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis and
Chris H. Kim and
Renato P. Ribas},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Modeling and estimating leakage current in series-parallel {CMOS}
networks},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {269--274},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228852},
doi = {10.1145/1228784.1228852},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ButzenRKR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/CalimeraPSBMMP07,
author = {Andrea Calimera and
Antonio Pullini and
Ashoka Visweswara Sathanur and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Design of a family of sleep transistor cells for a clustered power-gating
flow in 65nm technology},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {501--504},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228903},
doi = {10.1145/1228784.1228903},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/CalimeraPSBMMP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/CartaAVAMRBM07,
author = {Salvatore Carta and
Andrea Acquaviva and
Pablo Garc{\'{\i}}a Del Valle and
David Atienza and
Giovanni De Micheli and
Fernando Rinc{\'{o}}n and
Luca Benini and
Jose Manuel Mendias},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Multi-processor operating system emulation framework with thermal
feedback for systems-on-chip},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {311--316},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228787},
doi = {10.1145/1228784.1228787},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/CartaAVAMRBM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/CenkeramaddiSY07,
author = {Linga Reddy Cenkeramaddi and
Tajeshwar Singh and
Trond Ytterdal},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Self-biased charge sampling amplifier in 90nm {CMOS} for medical ultrasound
imaging},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {168--171},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228828},
doi = {10.1145/1228784.1228828},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/CenkeramaddiSY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/CeratoMN07,
author = {Barbara Cerato and
Guido Masera and
Peter Nilsson},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Hardware architecture for matrix factorization in mimo receivers},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {196--199},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228835},
doi = {10.1145/1228784.1228835},
timestamp = {Thu, 21 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/CeratoMN07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChavetCUM07,
author = {Cyrille Chavet and
Philippe Coussy and
Pascal Urard and
Eric Martin},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A design methodology for space-time adapter},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {347--352},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228868},
doi = {10.1145/1228784.1228868},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ChavetCUM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChenC07,
author = {Chichyang Chen and
Paul Chow},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Design of a versatile and cost-effective hybrid floating-point/LNS
arithmetic processor},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {540--545},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228912},
doi = {10.1145/1228784.1228912},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ChenC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Cho07,
author = {Sangyeun Cho},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {I-cache multi-banking and vertical interleaving},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {14--19},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228794},
doi = {10.1145/1228784.1228794},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Cho07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChungKK07,
author = {Chun{-}Mok Chung and
Jihong Kim and
Dohyung Kim},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Reducing snoop-energy in shared bus-based mpsocs by filtering useless
broadcasts},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {126--131},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228818},
doi = {10.1145/1228784.1228818},
timestamp = {Thu, 13 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ChungKK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DalM07,
author = {Deniz Dal and
Nazanin Mansouri},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A high-level register optimization technique for minimizing leakage
and dynamic power},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {517--520},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228907},
doi = {10.1145/1228784.1228907},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/DalM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DasSIZK07,
author = {Debasish Das and
Ahmed Shebaita and
Yehea I. Ismail and
Hai Zhou and
Kip Killpack},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {NostraXtalk: a predictive framework for accurate static timing analysis
in udsm vlsi circuits},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {25--30},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228797},
doi = {10.1145/1228784.1228797},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/DasSIZK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DassattiZNM07,
author = {Alberto Dassatti and
Simone Zezza and
Mario Nicola and
Guido Masera},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Beyond 3G wireless communication system prototype},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {335--340},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228865},
doi = {10.1145/1228784.1228865},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/DassattiZNM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DellBB07,
author = {Brandon L. Dell and
Jonathan F. Bolus and
Travis N. Blalock},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {An automated unique tagging system using {CMOS} process variation},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {216--218},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228840},
doi = {10.1145/1228784.1228840},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/DellBB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DimitroulakosKGG07,
author = {Grigoris Dimitroulakos and
Nikos Kostaras and
Michalis D. Galanis and
Costas E. Goutis},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Compiler assisted architectural exploration for coarse grained reconfigurable
arrays},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {164--167},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228827},
doi = {10.1145/1228784.1228827},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/DimitroulakosKGG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/EvainD07,
author = {Samuel Evain and
Jean{-}Philippe Diguet},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Efficient space-time noc path allocation based on mutual exclusion
and pre-reservation},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {457--460},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228892},
doi = {10.1145/1228784.1228892},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/EvainD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/FarahaniKFS07,
author = {Amin Farmahini Farahani and
Mehdi Kamal and
Seid Mehdi Fakhraie and
Saeed Safari},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {{HW/SW} partitioning using discrete particle swarm},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {359--364},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228870},
doi = {10.1145/1228784.1228870},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/FarahaniKFS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/FarivarKIJ07,
author = {Rashid Farivar and
Simon Kristiansson and
Fredrik Ingvarson and
Kjell O. Jeppson},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Evaluation of using active circuitry for substrate noise suppression},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {449--452},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228890},
doi = {10.1145/1228784.1228890},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/FarivarKIJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/FernandezRB07,
author = {Carlos Fern{\'{a}}ndez and
Rajkumar K. Raval and
Chris J. Bleakley},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {{GALS} SoC interconnect bus for wireless sensor network processor
platforms},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {132--137},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228819},
doi = {10.1145/1228784.1228819},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/FernandezRB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GalanisDG07,
author = {Michalis D. Galanis and
Grigoris Dimitroulakos and
Costas E. Goutis},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Improving performance and energy consumption in embedded microprocessor
platforms with a flexible custom coprocessor data-path},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {2--7},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228792},
doi = {10.1145/1228784.1228792},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GalanisDG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GentiliniSD07,
author = {Raffaella Gentilini and
Klaus Schneider and
Alexander Dreyer},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Three-valued automated reasoning on analog properties},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {485--488},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228899},
doi = {10.1145/1228784.1228899},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GentiliniSD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Gergel-HackettRPHR07,
author = {Nadine Gergel{-}Hackett and
Garrett S. Rose and
Peter C. Paliwoda and
Christina A. Hacker and
Curt A. Richter},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {On-chip characterization of molecular electronic devices using {CMOS:}
the design and simulation of a hybrid circuit based on experimental
molecular electronic device results},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {108--113},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228814},
doi = {10.1145/1228784.1228814},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Gergel-HackettRPHR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GhermanWMSG07,
author = {Valentin Gherman and
Hans{-}Joachim Wunderlich and
R. D. Mascarenhas and
J{\"{u}}rgen Schl{\"{o}}ffel and
Michael Garbers},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Synthesis of irregular combinational functions with large don't care
sets},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {287--292},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228856},
doi = {10.1145/1228784.1228856},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GhermanWMSG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Gielen07,
author = {Georges G. E. Gielen},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Future trends for wireless communication frontends in nanometer {CMOS}},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {600--605},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228790},
doi = {10.1145/1228784.1228790},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Gielen07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GiorgettiSST07,
author = {Jacopo Giorgetti and
Giuseppe Scotti and
Andrea Simonetti and
Alessandro Trifiletti},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Analysis of data dependence of leakage current in {CMOS} cryptographic
hardware},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {78--83},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228808},
doi = {10.1145/1228784.1228808},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GiorgettiSST07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GolubevaLP07,
author = {Olga Golubeva and
Mirko Loghi and
Massimo Poncino},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {On the energy efficiency of synchronization primitives for shared-memory
single-chip multiprocessors},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {489--492},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228900},
doi = {10.1145/1228784.1228900},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GolubevaLP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GowdaVK07,
author = {Tejaswi Gowda and
Sarma B. K. Vrudhula and
Goran Konjevod},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Combinational equivalence checking for threshold logic circuits},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {102--107},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228813},
doi = {10.1145/1228784.1228813},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/GowdaVK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GrosseCDD07,
author = {Daniel Gro{\ss}e and
Xiaobo Chen and
Gerhard W. Dueck and
Rolf Drechsler},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Exact sat-based toffoli network synthesis},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {96--101},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228812},
doi = {10.1145/1228784.1228812},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/GrosseCDD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GrosseED07,
author = {Daniel Gro{\ss}e and
R{\"{u}}diger Ebendt and
Rolf Drechsler},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Improvements for constraint solving in the systemc verification library},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {493--496},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228901},
doi = {10.1145/1228784.1228901},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/GrosseED07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GuptaNRM07,
author = {Rachit Kumar Gupta and
Vikas Narang and
H. M. Roopashree and
Vinod Menezes},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A low-power 333Mbps mobile-double data rate output driver with adaptive
feedback to minimize overshoots and undershoots},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {477--480},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228897},
doi = {10.1145/1228784.1228897},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GuptaNRM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HagiwaraUSM07,
author = {Shiho Hagiwara and
Takumi Uezono and
Takashi Sato and
Kazuya Masu},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Improvement of power distribution network using correlation-based
regression analysis},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {513--516},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228906},
doi = {10.1145/1228784.1228906},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/HagiwaraUSM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HaraTHTI07,
author = {Yuko Hara and
Hiroyuki Tomiyama and
Shinya Honda and
Hiroaki Takada and
Katsuya Ishii},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Complexity-constrainted partitioning of sequential programs for efficient
behavioral synthesis},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {365--370},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228871},
doi = {10.1145/1228784.1228871},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/HaraTHTI07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HeDBMH07,
author = {Ou He and
Sheqin Dong and
Jinian Bian and
Yuchun Ma and
Xianlong Hong},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {An effective buffer planning algorithm for {IP} based fixed-outline
{SOC} placement},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {564--569},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228917},
doi = {10.1145/1228784.1228917},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/HeDBMH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HeSGS07,
author = {Fei He and
Xiaoyu Song and
Ming Gu and
Jiaguang Sun},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Effective heuristics for counterexample-guided abstraction refinement},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {393--398},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228878},
doi = {10.1145/1228784.1228878},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/HeSGS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HessWBLSFF07,
author = {C. Hess and
Markus Wenk and
Andreas Burg and
Peter Luethi and
Christoph Studer and
Norbert Felber and
Wolfgang Fichtner},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Reduced-complexity mimo detector with close-to ml error rate performance},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {200--203},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228836},
doi = {10.1145/1228784.1228836},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/HessWBLSFF07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HwangRP07,
author = {Chanseok Hwang and
Peng Rong and
Massoud Pedram},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Sleep transistor distribution in row-based {MTCMOS} designs},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {235--240},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228786},
doi = {10.1145/1228784.1228786},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/HwangRP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ItohYK07,
author = {Kiyoo Itoh and
Masanao Yamaoka and
Takayuki Kawahara},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Low-voltage limitations of deep-sub-100-nm {CMOS} LSIs: view of memory
designers},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {529--533},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228789},
doi = {10.1145/1228784.1228789},
timestamp = {Thu, 07 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ItohYK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/JahanianZ07,
author = {Ali Jahanian and
Morteza Saheb Zamani},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Improved timing closure by early buffer planning in floor-placement
design flow},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {558--563},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228916},
doi = {10.1145/1228784.1228916},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/JahanianZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/JiaCH07,
author = {Yanming Jia and
Yici Cai and
Xianlong Hong},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Dummy fill aware buffer insertion during routing},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {31--36},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228798},
doi = {10.1145/1228784.1228798},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/JiaCH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KangKSK07,
author = {Kyungsu Kang and
Jungsoo Kim and
Heejun Shim and
Chong{-}Min Kyung},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Software power estimation using IPI(inter-prefetch interval) power
model for advanced off-the-shelf processor},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {594--599},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228923},
doi = {10.1145/1228784.1228923},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/KangKSK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Kania07,
author = {Dariusz Kania},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A new approach to logic synthesis of multi-output boolean functions
on pal-based {CPLDS}},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {152--155},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228824},
doi = {10.1145/1228784.1228824},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/Kania07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KarfaSMR07,
author = {Chandan Karfa and
Dipankar Sarkar and
Chittaranjan A. Mandal and
Chris Reade},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Hand-in-hand verification of high-level synthesis},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {429--434},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228885},
doi = {10.1145/1228784.1228885},
timestamp = {Mon, 08 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/KarfaSMR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KarimiMNL07,
author = {Naghmeh Karimi and
Shahrzad Mirkhani and
Zainalabedin Navabi and
Fabrizio Lombardi},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {{RT} level reliability enhancement by constructing dynamic {TMRS}},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {172--175},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228829},
doi = {10.1145/1228784.1228829},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/KarimiMNL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KawaC07,
author = {Jamil Kawa and
Charles C. Chiang},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {{DFM} issues for 65nm and beyond},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {318--322},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228861},
doi = {10.1145/1228784.1228861},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/KawaC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KheirabadiZ07,
author = {Hamid Reza Kheirabadi and
Morteza Saheb Zamani},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {An efficient net ordering algorithm for buffer insertion},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {521--524},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228908},
doi = {10.1145/1228784.1228908},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/KheirabadiZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LeeO07,
author = {Dong{-}Ho Lee and
Jong{-}Soo Oh},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Multi-segment \emph{GF}(2\({}^{\mbox{\emph{m}}}\)) multiplication
and its application to elliptic curve cryptography},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {546--551},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228913},
doi = {10.1145/1228784.1228913},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LeeO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LiWIG07,
author = {Shen Li and
Xianghui Wei and
Takeshi Ikenaga and
Satoshi Goto},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A {VLSI} architecture design of an edge based fast intra prediction
mode decision algorithm for H.264/avc},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {20--24},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228795},
doi = {10.1145/1228784.1228795},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LiWIG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LiWW07,
author = {Dan Li and
Tingcun Wei and
Wei Wu},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A novel charge recycler for {TFT-LCD} source driver {IC}},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {156--159},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228825},
doi = {10.1145/1228784.1228825},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LiWW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LinF07,
author = {Hai Lin and
Yunsi Fei},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Utilizing custom registers in application-specific instruction set
processors for register spills elimination},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {323--328},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228863},
doi = {10.1145/1228784.1228863},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/LinF07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LingasubramanianB07,
author = {Karthikeyan Lingasubramanian and
Sanjukta Bhanja},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Probabilistic maximum error modeling for unreliable logic circuits},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {223--226},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228842},
doi = {10.1145/1228784.1228842},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LingasubramanianB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LiuHSGI07,
author = {Zhenyu Liu and
Yiqing Huang and
Yang Song and
Satoshi Goto and
Takeshi Ikenaga},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Hardware-efficient propagate partial sad architecture for variable
block size motion estimation in {H.264/AVC}},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {160--163},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228826},
doi = {10.1145/1228784.1228826},
timestamp = {Mon, 23 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LiuHSGI07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LiuYQ07,
author = {Chunyue Liu and
Xiaolang Yan and
Xing Qin},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {An optimized linear skewing interleave scheme for on-chip multi-access
memory systems},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {8--13},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228793},
doi = {10.1145/1228784.1228793},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LiuYQ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Magarshack07,
author = {Philippe Magarshack},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Design challenges in 45nm and below: DFM, low-power and design for
reliability},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {1},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228785},
doi = {10.1145/1228784.1228785},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Magarshack07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MahramNP07,
author = {Atabak Mahram and
Mehrdad Najibi and
Hossein Pedram},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {An asynchronous fpga logic cell implementation},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {176--179},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228830},
doi = {10.1145/1228784.1228830},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MahramNP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MantovaniLRAB07,
author = {Marco Mantovani and
Simone Leardini and
Martino Ruggiero and
Andrea Acquaviva and
Luca Benini},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A lightweight parallel java execution environment for embedded multiprocessor
systems-on-chip},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {509--512},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228905},
doi = {10.1145/1228784.1228905},
timestamp = {Thu, 16 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MantovaniLRAB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MarquesRRSR07,
author = {Felipe S. Marques and
Leomar S. da Rosa Jr. and
Renato P. Ribas and
Sachin S. Sapatnekar and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {{DAG} based library-free technology mapping},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {293--298},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228857},
doi = {10.1145/1228784.1228857},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MarquesRRSR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MartinaM07,
author = {Maurizio Martina and
Guido Masera},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Flexible blocks for high throughput serially concatenated convolutional
codes},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {184--187},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228832},
doi = {10.1145/1228784.1228832},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MartinaM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MartinaTVMMDP07,
author = {Maurizio Martina and
Andrea Terreno and
Fabrizio Vacca and
Andrea Molino and
Guido Masera and
Giuseppe D'Angelo and
Giorgio Pasquettaz},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Real-time implementation of a time-frequency analysis scheme},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {180--183},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228831},
doi = {10.1145/1228784.1228831},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/MartinaTVMMDP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MatsunagaM07,
author = {Taeko Matsunaga and
Yusuke Matsunaga},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Area minimization algorithm for parallel prefix adders under bitwise
delay constraints},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {435--440},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228886},
doi = {10.1145/1228784.1228886},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MatsunagaM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MentensSPV07,
author = {Nele Mentens and
Kazuo Sakiyama and
Bart Preneel and
Ingrid Verbauwhede},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Efficient pipelining for modular multiplication architectures in prime
fields},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {534--539},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228911},
doi = {10.1145/1228784.1228911},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/MentensSPV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MohammadZadehNHG07,
author = {Naser MohammadZadeh and
Morteza NajafVand and
Shaahin Hessabi and
Maziar Goudarzi},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Implementation of a jpeg object-oriented {ASIP:} a case study on a
system-level design methodology},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {329--334},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228864},
doi = {10.1145/1228784.1228864},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/MohammadZadehNHG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MuraPNS07,
author = {Marcello Mura and
Marco Paolieri and
Luca Negri and
Mariagiovanna Sami},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {StateCharts to systemc: a high level hardware simulation approach},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {505--508},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228904},
doi = {10.1145/1228784.1228904},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MuraPNS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NajibiSP07,
author = {Mehrdad Najibi and
Kamran Saleh and
Hossein Pedram},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Using standard asic back-end for qdi asynchronous circuits: dealing
with isochronic fork constraint},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {299--304},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228858},
doi = {10.1145/1228784.1228858},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/NajibiSP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NakatakeKTS07,
author = {Shigetoshi Nakatake and
Zohreh Karimi and
Taraneh Taghavi and
Majid Sarrafzadeh},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Block placement to ensure channel routability},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {465--468},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228894},
doi = {10.1145/1228784.1228894},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/NakatakeKTS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NaseerDBDW07,
author = {Riaz Naseer and
Jeff Draper and
Younes Boulghassoul and
Sandeepan DasGupta and
Art Witulski},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Critical charge and set pulse widths for combinational logic in commercial
90nm cmos technology},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {227--230},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228843},
doi = {10.1145/1228784.1228843},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/NaseerDBDW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NessHL07,
author = {Drew C. Ness and
Christian J. Hescott and
David J. Lilja},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Exploring subsets of standard cell libraries to exploit natural fault
masking capabilities for reliable logic},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {208--211},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228838},
doi = {10.1145/1228784.1228838},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/NessHL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NooriGIM07,
author = {Hamid Noori and
Maziar Goudarzi and
Koji Inoue and
Kazuaki J. Murakami},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {The effect of temperature on cache size tuning for low energy embedded
systems},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {453--456},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228891},
doi = {10.1145/1228784.1228891},
timestamp = {Mon, 06 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/NooriGIM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NunezQA07,
author = {Juan N{\'{u}}{\~{n}}ez and
Jos{\'{e}} M. Quintana and
Maria J. Avedillo},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Operation limits in RTD-based ternary quantizers},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {114--119},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228815},
doi = {10.1145/1228784.1228815},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/NunezQA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/OhashiK07,
author = {Koji Ohashi and
Mineo Kaneko},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Extended register-sharing in the synthesis of dual-rail two-phase
asynchronous datapath},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {481--484},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228898},
doi = {10.1145/1228784.1228898},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/OhashiK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/OskuiiKA07,
author = {Saeeid Tahmasbi Oskuii and
Per Gunnar Kjeldsberg and
Einar J. Aas},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Probabilistic gate-level power estimation using a novel waveform set
method},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {37--42},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228799},
doi = {10.1145/1228784.1228799},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/OskuiiKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/OskuiiKG07,
author = {Saeeid Tahmasbi Oskuii and
Per Gunnar Kjeldsberg and
Oscar Gustafsson},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Transition-activity aware design of reduction-stages for parallel
multipliers},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {120--125},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228817},
doi = {10.1145/1228784.1228817},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/OskuiiKG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/OuSQA07,
author = {Jen{-}Chieh Ou and
Daniel G. Saab and
Qiang Qiang and
Jacob A. Abraham},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Reducing verification overhead with {RTL} slicing},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {399--404},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228879},
doi = {10.1145/1228784.1228879},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/OuSQA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PanitzOBK07,
author = {Philipp V. Panitz and
Markus Olbrich and
Erich Barke and
J{\"{u}}rgen Koehl},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Robust wiring networks for DfY considering timing constraints},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {43--48},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228800},
doi = {10.1145/1228784.1228800},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PanitzOBK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PapaefstathiouKC07,
author = {Ioannis Papaefstathiou and
George Kornaros and
Nikolaos Chrysos},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A buffered crossbar-based chip interconnection framework supporting
quality of service},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {90--95},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228810},
doi = {10.1145/1228784.1228810},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PapaefstathiouKC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PatelLP07,
author = {Kimish Patel and
Wonbok Lee and
Massoud Pedram},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Active bank switching for temperature control of the register file
in a microprocessor},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {231--234},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228844},
doi = {10.1145/1228784.1228844},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PatelLP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Popa07,
author = {Cosmin Popa},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Linearized {CMOS} active resistor independent on the bulk effect},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {253--256},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228848},
doi = {10.1145/1228784.1228848},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Popa07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RaghavendraA07,
author = {R. G. Raghavendra and
Bharadwaj Amrutur},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Area efficient loop filter design for charge pump phase locked loop},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {148--151},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228823},
doi = {10.1145/1228784.1228823},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/RaghavendraA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RaghunandanSS07,
author = {Chittarsu Raghunandan and
K. S. Sainarayanan and
M. B. Srinivas},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Bus-encoding technique to reduce delay, power and simultaneous switching
noise {(SSN)} in {RLC} interconnects},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {371--376},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228873},
doi = {10.1145/1228784.1228873},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/RaghunandanSS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Rahimi07,
author = {Kambiz Rahimi},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Minimizing peak power in synchronous logic circuits},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {247--252},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228847},
doi = {10.1145/1228784.1228847},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Rahimi07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RaudvereSJ07,
author = {Tarvo Raudvere and
Ingo Sander and
Axel Jantsch},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A synchronization algorithm for local temporal refinements in perfectly
synchronous models with nested feedback loops},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {353--358},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228869},
doi = {10.1145/1228784.1228869},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/RaudvereSJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RicciMC07,
author = {Andrea Ricci and
Ilaria De Munari and
Paolo Ciampolini},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {An evolutionary approach for standard-cell library reduction},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {305--310},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228859},
doi = {10.1145/1228784.1228859},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/RicciMC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RobinsonG07,
author = {Andrew Robinson and
Jim D. Garside},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Sensitive registers: a technique for reducing the fetch bandwidth
in low-power microprocessors},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {138--143},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228820},
doi = {10.1145/1228784.1228820},
timestamp = {Mon, 11 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/RobinsonG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RyanWC07,
author = {Joseph F. Ryan and
Jiajing Wang and
Benton H. Calhoun},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Analyzing and modeling process balance for sub-threshold circuit design},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {275--280},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228853},
doi = {10.1145/1228784.1228853},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/RyanWC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SaglamdemirYTD07,
author = {Muharrem Orkun Saglamdemir and
{\"{O}}mer Yetik and
Sel{\c{c}}uk Talay and
G{\"{u}}nhan D{\"{u}}ndar},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A coefficient optimization and architecture selection tool for {SD}
modulators considering component non-idealities},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {423--428},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228884},
doi = {10.1145/1228784.1228884},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/SaglamdemirYTD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SairamZC07,
author = {Tarun Sairam and
Wei Zhao and
Yu Cao},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Optimizing finfet technology for high-speed and low-power design},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {73--77},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228807},
doi = {10.1145/1228784.1228807},
timestamp = {Mon, 18 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/SairamZC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SakiyamaMPV07,
author = {Kazuo Sakiyama and
Elke De Mulder and
Bart Preneel and
Ingrid Verbauwhede},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Side-channel resistant system-level design flow for public-key cryptography},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {144--147},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228822},
doi = {10.1145/1228784.1228822},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/SakiyamaMPV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SalmehM07,
author = {Roghoyeh Salmeh and
Brent Maundy},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A 5 GHz wide band input and output matched low noise amplifier},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {377--380},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228874},
doi = {10.1145/1228784.1228874},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/SalmehM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Sapatnekar07,
author = {Sachin S. Sapatnekar},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Computer-aided design of 3d integrated circuits},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {317},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228788},
doi = {10.1145/1228784.1228788},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/Sapatnekar07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SillYT07,
author = {Frank Sill and
Jiaxi You and
Dirk Timmermann},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Design of mixed gates for leakage reduction},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {263--268},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228851},
doi = {10.1145/1228784.1228851},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/SillYT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/StanisavljevicGSLG07,
author = {Milos Stanisavljevic and
Frank K. G{\"{u}}rkaynak and
Alexandre Schmid and
Yusuf Leblebici and
Maria Gabrani},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Design and realization of a fault-tolerant 90nm {CMOS} cryptographic
engine capable of performing under massive defect density},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {204--207},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228837},
doi = {10.1145/1228784.1228837},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/StanisavljevicGSLG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SterponeV07,
author = {Luca Sterpone and
Massimo Violante},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A new decompression system for the configuration process of SRAM-based
{FPGAS}},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {241--246},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228846},
doi = {10.1145/1228784.1228846},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/SterponeV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SterponeV07a,
author = {Luca Sterpone and
Massimo Violante},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A new hardware architecture for performing the gridding of {DNA} microarray
images},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {341--346},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228866},
doi = {10.1145/1228784.1228866},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/SterponeV07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/TakahashiKT07,
author = {Yosuke Takahashi and
Yukihide Kohira and
Atsushi Takahashi},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A fast clock scheduling for peak power reduction in {LSI}},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {582--587},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228921},
doi = {10.1145/1228784.1228921},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/TakahashiKT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/TayadeKNOA07,
author = {Rajeshwary Tayade and
Vijay Kiran Kalyanam and
Sani R. Nassif and
Michael Orshansky and
Jacob A. Abraham},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Estimating path delay distribution considering coupling noise},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {61--66},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228804},
doi = {10.1145/1228784.1228804},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/TayadeKNOA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/TumeoMPFS07,
author = {Antonino Tumeo and
Matteo Monchiero and
Gianluca Palermo and
Fabrizio Ferrandi and
Donatella Sciuto},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A design kit for a fully working shared memory multiprocessor on {FPGA}},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {219--222},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228841},
doi = {10.1145/1228784.1228841},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/TumeoMPFS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/VeeramachaneniAKS07,
author = {Sreehari Veeramachaneni and
Lingamneni Avinash and
Kirthi M. Krishna and
M. B. Srinivas},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Novel architectures for efficient (m, n) parallel counters},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {188--191},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228833},
doi = {10.1145/1228784.1228833},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/VeeramachaneniAKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/VillaZYBS07,
author = {Tiziano Villa and
Svetlana Zharikova and
Nina Yevtushenko and
Robert K. Brayton and
Alberto L. Sangiovanni{-}Vincentelli},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {A new algorithm for the largest compositionally progressive solution
of synchronous language equations},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {441--444},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228888},
doi = {10.1145/1228784.1228888},
timestamp = {Tue, 15 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/VillaZYBS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/VorwerkKCB07,
author = {Kristofer Vorwerk and
Andrew A. Kennings and
Doris T. Chen and
Laleh Behjat},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Floorplan repair using dynamic whitespace management},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {552--557},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228915},
doi = {10.1145/1228784.1228915},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/VorwerkKCB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WangKZ07,
author = {Jia Wang and
Ming{-}Yang Kao and
Hai Zhou},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Address generation for nanowire decoders},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {525--528},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228909},
doi = {10.1145/1228784.1228909},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/WangKZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WeiCH07,
author = {Xinjie Wei and
Yici Cai and
Xianlong Hong},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Physical aware clock skew rescheduling},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {473--476},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228896},
doi = {10.1145/1228784.1228896},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/WeiCH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WengYH07,
author = {Chia{-}Chien Weng and
Ching{-}Shang Yang and
Shi{-}Yu Huang},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {RT-level vector selection for realistic peak power simulation},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {576--581},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228920},
doi = {10.1145/1228784.1228920},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/WengYH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WimmerHB07,
author = {Ralf Wimmer and
Marc Herbstritt and
Bernd Becker},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Optimization techniques for BDD-based bisimulation computation},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {405--410},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228880},
doi = {10.1145/1228784.1228880},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/WimmerHB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WuC07,
author = {Chih{-}Nan Wu and
Wei{-}Chung Cheng},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Viewing direction-aware backlight scaling},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {281--286},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228854},
doi = {10.1145/1228784.1228854},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/WuC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/YuPL07,
author = {Zhengtao Yu and
Marios C. Papaefthymiou and
Xun Liu},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Skew spreading for peak current reduction},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {461--464},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228893},
doi = {10.1145/1228784.1228893},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/YuPL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZhangS07,
author = {Yan Zhang and
Mircea R. Stan},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Temperature-aware circuit design using adaptive body biasing},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {84--89},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228809},
doi = {10.1145/1228784.1228809},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ZhangS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZhouYW07,
author = {Bin Zhou and
Yizheng Ye and
Yongsheng Wang},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Simultaneous reduction in test data volume and test time for TRC-reseeding},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {49--54},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228802},
doi = {10.1145/1228784.1228802},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ZhouYW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZhuoLZCH07,
author = {Yue Zhuo and
Hao Li and
Qiang Zhou and
Yici Cai and
Xianlong Hong},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {New timing and routability driven placement algorithms for {FPGA}
synthesis},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {570--575},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228918},
doi = {10.1145/1228784.1228918},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ZhuoLZCH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZieglerDKQS07,
author = {Matthew M. Ziegler and
Gary S. Ditlow and
Stephen V. Kosonocky and
Zhenyu Qi and
Mircea R. Stan},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Structured and tuned array generation {(STAG)} for high-performance
random logic},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {257--262},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228849},
doi = {10.1145/1228784.1228849},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ZieglerDKQS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/2007,
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784},
doi = {10.1145/1228784},
isbn = {978-1-59593-605-9},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/2007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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