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@inproceedings{DBLP:conf/isca/AdveAHV91,
  author       = {Sarita V. Adve and
                  Vikram S. Adve and
                  Mark D. Hill and
                  Mary K. Vernon},
  editor       = {Zvonko G. Vranesic},
  title        = {Comparison of Hardware and Software Cache Coherence Schemes},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {298--308},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115982},
  doi          = {10.1145/115952.115982},
  timestamp    = {Fri, 09 Jul 2021 15:51:20 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/AdveAHV91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/AdveHMN91,
  author       = {Sarita V. Adve and
                  Mark D. Hill and
                  Barton P. Miller and
                  Robert H. B. Netzer},
  editor       = {Zvonko G. Vranesic},
  title        = {Detecting Data Races on Weak Memory Systems},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {234--243},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115976},
  doi          = {10.1145/115952.115976},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/AdveHMN91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/AkellaS91,
  author       = {Janaki Akella and
                  Daniel P. Siewiorek},
  editor       = {Zvonko G. Vranesic},
  title        = {Modeling and Measurement of the Impact of Input/Output on System Performance},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {390--399},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115991},
  doi          = {10.1145/115952.115991},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/AkellaS91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/BradleeEH91,
  author       = {David G. Bradlee and
                  Susan J. Eggers and
                  Robert R. Henry},
  editor       = {Zvonko G. Vranesic},
  title        = {The Effect on {RISC} Performance of Register Set Size and Structure
                  Versus Code Generation Strategy},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {330--339},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115985},
  doi          = {10.1145/115952.115985},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/BradleeEH91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/ButlerYPASS91,
  author       = {Michael Butler and
                  Tse{-}Yu Yeh and
                  Yale N. Patt and
                  Mitch Alsup and
                  Hunter Scales and
                  Michael Shebanow},
  editor       = {Zvonko G. Vranesic},
  title        = {Single Instruction Stream Parallelism is Greater Than Two},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {276--286},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115980},
  doi          = {10.1145/115952.115980},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/ButlerYPASS91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/ChangMCWH91,
  author       = {Pohua P. Chang and
                  Scott A. Mahlke and
                  William Y. Chen and
                  Nancy J. Warter and
                  Wen{-}mei W. Hwu},
  editor       = {Zvonko G. Vranesic},
  title        = {{IMPACT:} An Architectural Framework for Multiple-Instruction-Issue
                  Processors},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {266--275},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115979},
  doi          = {10.1145/115952.115979},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/ChangMCWH91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/Chiueh91,
  author       = {Tzi{-}cker Chiueh},
  editor       = {Zvonko G. Vranesic},
  title        = {Multi-Threaded Vectorization},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {352--361},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115987},
  doi          = {10.1145/115952.115987},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/Chiueh91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/DeMaraM91,
  author       = {Ronald F. DeMara and
                  Dan I. Moldovan},
  editor       = {Zvonko G. Vranesic},
  title        = {The {SNAP-1} Parallel {AI} Prototype},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {2--11},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115954},
  doi          = {10.1145/115952.115954},
  timestamp    = {Wed, 25 Sep 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/DeMaraM91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/DimpseyI91,
  author       = {Robert T. Dimpsey and
                  Ravishankar K. Iyer},
  editor       = {Zvonko G. Vranesic},
  title        = {Performance Prediction and Tuning on a Multiprocessor},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {190--199},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115972},
  doi          = {10.1145/115952.115972},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/DimpseyI91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/Dowd91,
  author       = {Patrick W. Dowd},
  editor       = {Zvonko G. Vranesic},
  title        = {High Performance Interprocessor Communication through Optical Wavelength
                  Division Multiple Access Channels},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {96--105},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115963},
  doi          = {10.1145/115952.115963},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/Dowd91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/FarrensP91,
  author       = {Matthew K. Farrens and
                  Arvin Park},
  editor       = {Zvonko G. Vranesic},
  title        = {Dynamic Base Register Caching: {A} Technique for Reducing Address
                  Bus Width},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {128--137},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115966},
  doi          = {10.1145/115952.115966},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/FarrensP91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/FarrensP91a,
  author       = {Matthew K. Farrens and
                  Andrew R. Pleszkun},
  editor       = {Zvonko G. Vranesic},
  title        = {Strategies for Achieving Improved Processor Throughput},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {362--369},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115988},
  doi          = {10.1145/115952.115988},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/FarrensP91a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/FuP91,
  author       = {John W. C. Fu and
                  Janak H. Patel},
  editor       = {Zvonko G. Vranesic},
  title        = {Data Prefetching in Multiprocessor Vector Cache Memories},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {54--63},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115959},
  doi          = {10.1145/115952.115959},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/FuP91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/GuptaHGMW91,
  author       = {Anoop Gupta and
                  John L. Hennessy and
                  Kourosh Gharachorloo and
                  Todd C. Mowry and
                  Wolf{-}Dietrich Weber},
  editor       = {Zvonko G. Vranesic},
  title        = {Comparative Evaluation of Latency Reducing and Tolerating Techniques},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {254--263},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115978},
  doi          = {10.1145/115952.115978},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/GuptaHGMW91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/HallR91,
  author       = {Judith S. Hall and
                  Paul T. Robinson},
  editor       = {Zvonko G. Vranesic},
  title        = {Virtualizing the {VAX} Architecture},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {380--389},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115990},
  doi          = {10.1145/115952.115990},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/HallR91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/Harper91,
  author       = {David T. Harper III},
  editor       = {Zvonko G. Vranesic},
  title        = {Reducing Memory Contention in Shared Memory Multiprocessors},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {66--73},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115960},
  doi          = {10.1145/115952.115960},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/Harper91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/HiguchiFHTNK91,
  author       = {Tetsuya Higuchi and
                  Tatsumi Furuya and
                  Ken'ichi Handa and
                  Naoto Takahashi and
                  Hiroyasu Nishiyama and
                  Akio Kokubu},
  editor       = {Zvonko G. Vranesic},
  title        = {{IXM2:} {A} Parallel Associative Processor},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {22--31},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115956},
  doi          = {10.1145/115952.115956},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/HiguchiFHTNK91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/KaeliE91,
  author       = {David R. Kaeli and
                  Philip G. Emma},
  editor       = {Zvonko G. Vranesic},
  title        = {Branch History Table Prediction of Moving Target Branches due to Subroutine
                  Returns},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {34--42},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115957},
  doi          = {10.1145/115952.115957},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/KaeliE91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/KagimasaTMY91,
  author       = {Toyohiko Kagimasa and
                  Kikuo Takahashi and
                  Toshiaki Mori and
                  Seiichi Yoshizumi},
  editor       = {Zvonko G. Vranesic},
  title        = {Adaptive Storage Management for Very Large Virtual/Real Storage Systems},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {372--379},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115989},
  doi          = {10.1145/115952.115989},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/KagimasaTMY91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/KlaiberL91,
  author       = {Alexander C. Klaiber and
                  Henry M. Levy},
  editor       = {Zvonko G. Vranesic},
  title        = {An Architecture for Software-Controlled Data Prefetching},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {43--53},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115958},
  doi          = {10.1145/115952.115958},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/KlaiberL91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/KoldingerEL91,
  author       = {Eric J. Koldinger and
                  Susan J. Eggers and
                  Henry M. Levy},
  editor       = {Zvonko G. Vranesic},
  title        = {On the Validity of Trace-Driven Simulation for Multiprocessors},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {244--253},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115977},
  doi          = {10.1145/115952.115977},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/KoldingerEL91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/KonstantinidouS91,
  author       = {Smaragda Konstantinidou and
                  Lawrence Snyder},
  editor       = {Zvonko G. Vranesic},
  title        = {Chaos Router: Architecture and Performance},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {212--221},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115974},
  doi          = {10.1145/115952.115974},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/KonstantinidouS91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/KurianHCM91,
  author       = {Lizyamma Kurian and
                  Paul T. Hulina and
                  Lee D. Coraor and
                  Dhamir N. Mannai},
  editor       = {Zvonko G. Vranesic},
  title        = {Classification and Performance Evaluation of Instruction Buffering
                  Techniques},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {150--159},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115968},
  doi          = {10.1145/115952.115968},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/KurianHCM91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/LandinHH91,
  author       = {Anders Landin and
                  Erik Hagersten and
                  Seif Haridi},
  editor       = {Zvonko G. Vranesic},
  title        = {Race-Free Interconnection Networks and Multiprocessor Consistency},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {106--115},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115964},
  doi          = {10.1145/115952.115964},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/LandinHH91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/LiP91,
  author       = {Kai Li and
                  Karin Petersen},
  editor       = {Zvonko G. Vranesic},
  title        = {Evaluation of Memory System Extensions},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {84--93},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115962},
  doi          = {10.1145/115952.115962},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/LiP91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/LinN91,
  author       = {Xiaola Lin and
                  Lionel M. Ni},
  editor       = {Zvonko G. Vranesic},
  title        = {Deadlock-Free Multicast Wormhole Routing in Multicomputer Networks},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {116--125},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115965},
  doi          = {10.1145/115952.115965},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/LinN91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/MelvinP91,
  author       = {Stephen W. Melvin and
                  Yale N. Patt},
  editor       = {Zvonko G. Vranesic},
  title        = {Exploiting Fine-Grained Parallelism Through a Combination of Hardware
                  and Software Techniques},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {287--296},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115981},
  doi          = {10.1145/115952.115981},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/MelvinP91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/NakajimaNNYGNSKK91,
  author       = {Masaitsu Nakajima and
                  Hiraku Nakano and
                  Yasuhiro Nakakura and
                  Tadahiro Yoshida and
                  Yoshiyuki Goi and
                  Yuji Nakai and
                  Reiji Segawa and
                  Takeshi Kishida and
                  Hiroshi Kadota},
  editor       = {Zvonko G. Vranesic},
  title        = {{OHMEGA:} {A} {VLSI} Superscalar Processor Architecture for Numerical
                  Applications},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {160--168},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115969},
  doi          = {10.1145/115952.115969},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/NakajimaNNYGNSKK91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/OehlrichQ91,
  author       = {C. W. Oehlrich and
                  Andreas Quick},
  editor       = {Zvonko G. Vranesic},
  title        = {Performance Evaluation of a Communication System for Transputer-Networks
                  Based on Monitored Event Traces},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {202--211},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115973},
  doi          = {10.1145/115952.115973},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/OehlrichQ91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/OlukotunMB91,
  author       = {Kunle Olukotun and
                  Trevor N. Mudge and
                  Richard B. Brown},
  editor       = {Zvonko G. Vranesic},
  title        = {Implementing a Cache for a High-Performance GaAs Microprocessor},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {138--147},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115967},
  doi          = {10.1145/115952.115967},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/OlukotunMB91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/PapadopoulosT91,
  author       = {Gregory M. Papadopoulos and
                  Kenneth R. Traub},
  editor       = {Zvonko G. Vranesic},
  title        = {Multithreading: {A} Revisionist View of Dataflow Architectures},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {342--351},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115986},
  doi          = {10.1145/115952.115986},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/PapadopoulosT91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/QuammenM91,
  author       = {Donna J. Quammen and
                  D. Richard Miller},
  editor       = {Zvonko G. Vranesic},
  title        = {Flexible Register Management for Sequential Programs},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {320--329},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115984},
  doi          = {10.1145/115952.115984},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/QuammenM91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/Rau91,
  author       = {B. Ramakrishna Rau},
  editor       = {Zvonko G. Vranesic},
  title        = {Pseudo-Randomly Interleaved Memory},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {74--83},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115961},
  doi          = {10.1145/115952.115961},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/Rau91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/ShuklaA91,
  author       = {Shridhar B. Shukla and
                  Dharma P. Agrawal},
  editor       = {Zvonko G. Vranesic},
  title        = {Scheduling Pipelined Communication in Distributed Memory Multiprocessors
                  for Real-Time Applications},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {222--231},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115975},
  doi          = {10.1145/115952.115975},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/ShuklaA91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/SimoniH91,
  author       = {Richard Simoni and
                  Mark Horowitz},
  editor       = {Zvonko G. Vranesic},
  title        = {Modeling the Performance of Limited Pointers Directories for Cache
                  Coherence},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {309--319},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115983},
  doi          = {10.1145/115952.115983},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/SimoniH91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/StephensCHPS91,
  author       = {Chriss Stephens and
                  Bryce Cogswell and
                  John Heinlein and
                  Gregory Palmer and
                  John Paul Shen},
  editor       = {Zvonko G. Vranesic},
  title        = {Instruction Level Profiling and Evaluation of the {IBM/6000}},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {180--189},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115971},
  doi          = {10.1145/115952.115971},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/StephensCHPS91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/TanRA91,
  author       = {Wei Siong Tan and
                  H. Russ and
                  Cecil O. Alford},
  editor       = {Zvonko G. Vranesic},
  title        = {{GT-EP:} {A} Novel High-Performance Real-Time Architecture},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {13--21},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115955},
  doi          = {10.1145/115952.115955},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/TanRA91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/VajapeyamSH91,
  author       = {Sriram Vajapeyam and
                  Gurindar S. Sohi and
                  Wei{-}Chung Hsu},
  editor       = {Zvonko G. Vranesic},
  title        = {An Empirical Study of the {CRAY} {Y-MP} Processor Using the Perfect
                  Club Benchmarks},
  booktitle    = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  pages        = {170--179},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952.115970},
  doi          = {10.1145/115952.115970},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/VajapeyamSH91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/isca/1991,
  editor       = {Zvonko G. Vranesic},
  title        = {Proceedings of the 18th Annual International Symposium on Computer
                  Architecture. Toronto, Canada, May, 27-30 1991},
  publisher    = {{ACM}},
  year         = {1991},
  url          = {https://doi.org/10.1145/115952},
  doi          = {10.1145/115952},
  isbn         = {0-89791-394-9},
  timestamp    = {Fri, 09 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/1991.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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