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@inproceedings{DBLP:conf/patmos/AcostaJJBV00,
author = {Antonio J. Acosta and
Ra{\'{u}}l Jim{\'{e}}nez and
Jorge Juan{-}Chico and
Manuel J. Bellido and
Manuel Valencia{-}Barrero},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Influence of Clocking Strategies on the Design of Low Switching-Noise
Digital and Mixed-Signal {VLSI} Circuits},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {316--326},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_33},
doi = {10.1007/3-540-45373-3\_33},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AcostaJJBV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AliotoP00,
author = {Massimo Alioto and
Gaetano Palumbo},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Modeling of Power Consumption of Adiabatic Gates versus Fan in and
Comparison with Conventional Gates},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {265--275},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_28},
doi = {10.1007/3-540-45373-3\_28},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AliotoP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AntonCCMPB00,
author = {Crina Anton and
Pierluigi Civera and
Ionel Colonescu and
Enrico Macii and
Massimo Poncino and
Alessandro Bogliolo},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {{RTL} Estimation of Steering Logic Power},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {36--46},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_5},
doi = {10.1007/3-540-45373-3\_5},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AntonCCMPB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AntonCSZ00,
author = {Manuela Anton and
Mauro Chinosi and
Daniele Sirtori and
Roberto Zafalon},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Architectural Design Space Exploration Achieved through Innovative
{RTL} Power Estimation Techniques},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {3--13},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_2},
doi = {10.1007/3-540-45373-3\_2},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AntonCSZ00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ArmMP00,
author = {Claude Arm and
Jean{-}Marc Masgonty and
Christian Piguet},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Double-Latch Clocking Scheme for Low-Power {I.P.} Cores},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {217--224},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_23},
doi = {10.1007/3-540-45373-3\_23},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ArmMP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BoglioloMMP00,
author = {Alessandro Bogliolo and
Enrico Macii and
Virgil Mihailovici and
Massimo Poncino},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Power Models for Semi-autonomous {RTL} Macros},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {14--23},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_3},
doi = {10.1007/3-540-45373-3\_3},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BoglioloMMP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/CorsonelloPC00,
author = {Pasquale Corsonello and
Stefania Perri and
Giuseppe Cocorullo},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {{VLSI} Implementation of a Low-Power High-Speed Self-Timed Adder},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {195--204},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_20},
doi = {10.1007/3-540-45373-3\_20},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/CorsonelloPC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DenolfVBB00,
author = {Kristof Denolf and
Peter Vos and
Jan Bormans and
Ivo Bolsens},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Cost-Efficient C-Level Design of an {MPEG-4} Video Decoder},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {233--242},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_25},
doi = {10.1007/3-540-45373-3\_25},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DenolfVBB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Dutta00,
author = {Santanu Dutta},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Architecture, Design, and Verification of an 18 Million Transistor
Digital Television and Media Processor Chip},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {225--232},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_24},
doi = {10.1007/3-540-45373-3\_24},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Dutta00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ErikssonL00,
author = {Henrik Eriksson and
Per Larsson{-}Edefors},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Impact of Voltage Scaling on Glitch Power Consumption},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {139--148},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_14},
doi = {10.1007/3-540-45373-3\_14},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ErikssonL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Freimann00,
author = {Achim Freimann},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Framework for High-Level Power Estimation of Signal Processing Architectures},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {56--65},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_7},
doi = {10.1007/3-540-45373-3\_7},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Freimann00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/HartensteinHN00,
author = {Reiner W. Hartenstein and
Thomas Hoffmann and
Ulrich Nageldinger},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Design-Space Exploration of Low Power Coarse Grained Reconfigurable
Datapath Array Architectures},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {118--128},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_12},
doi = {10.1007/3-540-45373-3\_12},
timestamp = {Tue, 08 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/HartensteinHN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/HerrmannBSS00,
author = {Andreas Herrmann and
Erich Barke and
Mathias Silvant and
J{\"{u}}rgen Schl{\"{o}}ffel},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {{PARCOURS} - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {306--315},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_32},
doi = {10.1007/3-540-45373-3\_32},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/HerrmannBSS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/IrvinKVS00,
author = {Mary Jane Irwin and
Mahmut T. Kandemir and
Narayanan Vijaykrishnan and
Anand Sivasubramaniam},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {A Holistic Approach to System Level Energy Optimization},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {88--107},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_10},
doi = {10.1007/3-540-45373-3\_10},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/IrvinKVS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/JimenezAPR00,
author = {Ra{\'{u}}l Jim{\'{e}}nez and
Antonio J. Acosta and
Eduardo J. Peral{\'{\i}}as and
Adoraci{\'{o}}n Rueda},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {An Application of Self-Timed Circuits to the Reduction of Switching
Noise in Analog-Digital Circuits},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {295--305},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_31},
doi = {10.1007/3-540-45373-3\_31},
timestamp = {Fri, 03 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/JimenezAPR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/JochensKSSN00,
author = {Gerd Jochens and
Lars Kruse and
Eike Schmidt and
Ansgar Stammermann and
Wolfgang Nebel},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Power Macro-Modelling for Firm-Macro},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {24--35},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_4},
doi = {10.1007/3-540-45373-3\_4},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/JochensKSSN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Juan-ChicoBRAV00,
author = {Jorge Juan{-}Chico and
Manuel J. Bellido and
Paulino Ruiz{-}de{-}Clavijo and
Antonio J. Acosta and
Manuel Valencia{-}Barrero},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Degradation Delay Model Extension to {CMOS} Gates},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {149--158},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_15},
doi = {10.1007/3-540-45373-3\_15},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Juan-ChicoBRAV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KakaroudasPKG00,
author = {Athanasios Kakarountas and
Kyriakos Papadomanolakis and
Vasileios Kokkinos and
Constantinos E. Goutis},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Comparative Study on Self-Checking Carry-Propagate Adders in Terms
of Area, Power and Performance},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {187--194},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_19},
doi = {10.1007/3-540-45373-3\_19},
timestamp = {Thu, 22 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KakaroudasPKG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KimP00,
author = {Joohee Kim and
Marios C. Papaefthymiou},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Dynamic Memory Design for Low Data-Retention Power},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {207--216},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_22},
doi = {10.1007/3-540-45373-3\_22},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KimP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KretzschmarSM00,
author = {Claudia Kretzschmar and
Robert Siegmund and
Dietmar M{\"{u}}ller},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Adaptive Bus Encoding Technique for Switching Activity Reduced Data
Transfer over Wide System Buses},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {66--75},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_8},
doi = {10.1007/3-540-45373-3\_8},
timestamp = {Sat, 04 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KretzschmarSM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LajoloLRV00,
author = {Marcello Lajolo and
Luciano Lavagno and
Matteo Sonza Reorda and
Massimo Violante},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Early Power Estimation for System-on-Chip Designs},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {108--117},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_11},
doi = {10.1007/3-540-45373-3\_11},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LajoloLRV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LeukenNG00,
author = {Rene van Leuken and
Reinder Nouta and
Alexander de Graaf},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Constraints, Hurdles, and Opportunities for a Successful European
Take-Up Action},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {1--2},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_1},
doi = {10.1007/3-540-45373-3\_1},
timestamp = {Tue, 13 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LeukenNG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MaurineRA00,
author = {Philippe Maurine and
Mustapha Rezzoug and
Daniel Auvergne},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Internal Power Dissipation Modeling and Minimization for Submicronic
{CMOS} Design},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {129--138},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_13},
doi = {10.1007/3-540-45373-3\_13},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MaurineRA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/PaliourasS00,
author = {Vassilis Paliouras and
Thanos Stouraitis},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Logarithmic Number System for Low-Power Arithmetic},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {285--294},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_30},
doi = {10.1007/3-540-45373-3\_30},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/PaliourasS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/PessolanoK00,
author = {Francesco Pessolano and
Joep L. W. Kessels},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Asynchronous First-in First-out Queues},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {178--186},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_18},
doi = {10.1007/3-540-45373-3\_18},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/PessolanoK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/RezzougMA00,
author = {Mustapha Rezzoug and
Philippe Maurine and
Daniel Auvergne},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Second Generation Delay Model for Submicron {CMOS} Process},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {159--167},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_16},
doi = {10.1007/3-540-45373-3\_16},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/RezzougMA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SaasSN00,
author = {Christoph Saas and
Andreas Schlaffer and
Josef A. Nossek},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {An Adiabatic Multiplier},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {276--284},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_29},
doi = {10.1007/3-540-45373-3\_29},
timestamp = {Wed, 10 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/SaasSN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Sedlak00,
author = {Holger Sedlak},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Low Power Design Techniques for Contactless Chipcards},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {205--206},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_21},
doi = {10.1007/3-540-45373-3\_21},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Sedlak00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SoudrisZADTGT00,
author = {Dimitrios Soudris and
Nikolaos D. Zervas and
Antonios Argyriou and
Minas Dasygenis and
Konstantinos Tatas and
Constantinos E. Goutis and
Adonios Thanailakis},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time
Multimedia Applications},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {243--254},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_26},
doi = {10.1007/3-540-45373-3\_26},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SoudrisZADTGT00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/StarodoubtsevBY00,
author = {Nikolai Starodoubtsev and
Alexandre V. Bystrov and
Alexandre Yakovlev},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Semi-modular Latch Chains for Asynchronous Circuit Design},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {168--177},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_17},
doi = {10.1007/3-540-45373-3\_17},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/StarodoubtsevBY00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/TheodoridisTZG00,
author = {George Theodoridis and
S. Theoharis and
Nikolaos D. Zervas and
Constantinos E. Goutis},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Accurate Power Estimation of Logic Structures Based on Timed Boolean
Functions},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {76--87},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_9},
doi = {10.1007/3-540-45373-3\_9},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/TheodoridisTZG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/VosDAPSW00,
author = {Alexis De Vos and
Bart Desoete and
Artur Adamski and
Piotr Pietrzak and
Maciej Sib{\'{\i}}nski and
Tomasz Widerski},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Design of Reversible Logic Circuits by Means of Control Gates},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {255--264},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_27},
doi = {10.1007/3-540-45373-3\_27},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/VosDAPSW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/WichmannT00,
author = {Tim Wichmann and
Manfred Thole},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Computer Aided Generation of Analytic Models for Nonlinear Function
Blocks},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {327--335},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_34},
doi = {10.1007/3-540-45373-3\_34},
timestamp = {Mon, 16 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/WichmannT00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ZervasTKTSG00,
author = {Nikolaos D. Zervas and
S. Theoharis and
Athanasios Kakarountas and
George Theodoridis and
Dimitrios Soudris and
Constantinos E. Goutis},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Reducing Power Consumption through Dynamic Frequency Scaling for a
Class of Digital Receivers},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {47--55},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_6},
doi = {10.1007/3-540-45373-3\_6},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ZervasTKTSG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/patmos/2000,
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3},
doi = {10.1007/3-540-45373-3},
isbn = {3-540-41068-6},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/2000.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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