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@article{DBLP:journals/integration/AartsBKR91,
  author       = {Emile H. L. Aarts and
                  F. M. J. de Bont and
                  Jan H. M. Korst and
                  J. M. J. Rongen},
  title        = {An efficient macro-cell placement algorithm},
  journal      = {Integr.},
  volume       = {10},
  number       = {3},
  pages        = {299--317},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(05)80023-9},
  doi          = {10.1016/S0167-9260(05)80023-9},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/AartsBKR91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenK91,
  author       = {H. Y. Chen and
                  Sung{-}Mo Kang},
  title        = {iCOACH: {A} circuit optimization aid for {CMOS} high-performance circuits},
  journal      = {Integr.},
  volume       = {10},
  number       = {2},
  pages        = {185--212},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(06)80015-5},
  doi          = {10.1016/S0167-9260(06)80015-5},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/ChenK91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Curatelli91,
  author       = {Francesco Curatelli},
  title        = {Region definition and ordering for macrocells with unconstrained placement},
  journal      = {Integr.},
  volume       = {10},
  number       = {2},
  pages        = {169--184},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(06)80014-3},
  doi          = {10.1016/S0167-9260(06)80014-3},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Curatelli91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HeuslerF91,
  author       = {Lucas S. Heusler and
                  Wolfgang Fichtner},
  title        = {Transistor sizing for large combinational digital {CMOS} circuits},
  journal      = {Integr.},
  volume       = {10},
  number       = {2},
  pages        = {155--168},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(06)80013-1},
  doi          = {10.1016/S0167-9260(06)80013-1},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/HeuslerF91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Kappen91,
  author       = {H. J. Kappen},
  title        = {An efficient heuristic for standard-cell placement},
  journal      = {Integr.},
  volume       = {10},
  number       = {3},
  pages        = {251--269},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(05)80021-5},
  doi          = {10.1016/S0167-9260(05)80021-5},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Kappen91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KuM91a,
  author       = {David C. Ku and
                  Giovanni De Micheli},
  title        = {Optimal synthesis of control logic from behavioral specifications},
  journal      = {Integr.},
  volume       = {10},
  number       = {3},
  pages        = {271--298},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(05)80022-7},
  doi          = {10.1016/S0167-9260(05)80022-7},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KuM91a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MatobaLHM91,
  author       = {Takako Matoba and
                  Kuo Chi Lee and
                  Gary E. Herman and
                  William H. Mansfield Jr.},
  title        = {A rapid turnaround design of a high speed {VLSI} search processor},
  journal      = {Integr.},
  volume       = {10},
  number       = {3},
  pages        = {319--337},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(05)80024-0},
  doi          = {10.1016/S0167-9260(05)80024-0},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/MatobaLHM91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Payer91,
  author       = {Michael Payer},
  title        = {Partitioning and ordering of {CMOS} circuits for switch level analysis},
  journal      = {Integr.},
  volume       = {10},
  number       = {2},
  pages        = {113--141},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(06)80011-8},
  doi          = {10.1016/S0167-9260(06)80011-8},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Payer91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PelzB91,
  author       = {Georg Pelz and
                  Volker Meyer zu Bexten},
  title        = {Efficient fracturing of all angle shaped {VLSI} mask pattern data},
  journal      = {Integr.},
  volume       = {10},
  number       = {2},
  pages        = {143--154},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(06)80012-X},
  doi          = {10.1016/S0167-9260(06)80012-X},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/PelzB91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PiguetD91,
  author       = {Christian Piguet and
                  Evert Dijkstra},
  title        = {Design methodologies and {CAD} tools},
  journal      = {Integr.},
  volume       = {10},
  number       = {3},
  pages        = {219--250},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(05)80020-3},
  doi          = {10.1016/S0167-9260(05)80020-3},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/PiguetD91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Spaanenburg91c,
  author       = {Lambert Spaanenburg},
  title        = {Editorial},
  journal      = {Integr.},
  volume       = {10},
  number       = {3},
  pages        = {i},
  year         = {1991},
  url          = {https://doi.org/10.1016/S0167-9260(05)80019-7},
  doi          = {10.1016/S0167-9260(05)80019-7},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Spaanenburg91c.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HsiaoCF90,
  author       = {Pei{-}Yung Hsiao and
                  H. F. Steven Chen and
                  Wu{-}Shiung Feng},
  title        = {A new control strategy for an artificial intelligence approach to
                  {VLSI} layout compaction},
  journal      = {Integr.},
  volume       = {10},
  number       = {1},
  pages        = {55--70},
  year         = {1990},
  url          = {https://doi.org/10.1016/S0167-9260(05)80035-5},
  doi          = {10.1016/S0167-9260(05)80035-5},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/HsiaoCF90.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimK90,
  author       = {Youngtak Kim and
                  Myunghwan Kim},
  title        = {A stepwise-overlapped parallel simulated annealing algorithm},
  journal      = {Integr.},
  volume       = {10},
  number       = {1},
  pages        = {39--54},
  year         = {1990},
  url          = {https://doi.org/10.1016/S0167-9260(05)80034-3},
  doi          = {10.1016/S0167-9260(05)80034-3},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KimK90.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiaoLS90,
  author       = {Kuo{-}Feng Liao and
                  D. T. Lee and
                  Majid Sarrafzadeh},
  title        = {Planar subset of multi-terminal nets},
  journal      = {Integr.},
  volume       = {10},
  number       = {1},
  pages        = {19--37},
  year         = {1990},
  url          = {https://doi.org/10.1016/S0167-9260(05)80033-1},
  doi          = {10.1016/S0167-9260(05)80033-1},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/LiaoLS90.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LukDM90,
  author       = {Wing K. Luk and
                  Alvar A. Dean and
                  John W. Mathews},
  title        = {Partitioning and floor-planning for data-path chip (microprocessor)
                  layout},
  journal      = {Integr.},
  volume       = {10},
  number       = {1},
  pages        = {89--108},
  year         = {1990},
  url          = {https://doi.org/10.1016/S0167-9260(05)80037-9},
  doi          = {10.1016/S0167-9260(05)80037-9},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/LukDM90.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Papananos90,
  author       = {Yannis Papananos},
  title        = {A new wiring architectUre for parallel processing applications},
  journal      = {Integr.},
  volume       = {10},
  number       = {1},
  pages        = {71--88},
  year         = {1990},
  url          = {https://doi.org/10.1016/S0167-9260(05)80036-7},
  doi          = {10.1016/S0167-9260(05)80036-7},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Papananos90.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Spaanenburg90,
  author       = {Lambert Spaanenburg},
  title        = {Editorial},
  journal      = {Integr.},
  volume       = {10},
  number       = {1},
  pages        = {1},
  year         = {1990},
  url          = {https://doi.org/10.1016/S0167-9260(05)80030-6},
  doi          = {10.1016/S0167-9260(05)80030-6},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Spaanenburg90.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangC90,
  author       = {Ted C. Yang and
                  Che W. Chiou},
  title        = {Universal syndrome-testable design of programmable logic arrays},
  journal      = {Integr.},
  volume       = {10},
  number       = {1},
  pages        = {3--8},
  year         = {1990},
  url          = {https://doi.org/10.1016/S0167-9260(05)80031-8},
  doi          = {10.1016/S0167-9260(05)80031-8},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/YangC90.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YangC90a,
  author       = {Ted C. Yang and
                  Che W. Chiou},
  title        = {Testable {PLA} design with minimal overheads},
  journal      = {Integr.},
  volume       = {10},
  number       = {1},
  pages        = {9--18},
  year         = {1990},
  url          = {https://doi.org/10.1016/S0167-9260(05)80032-X},
  doi          = {10.1016/S0167-9260(05)80032-X},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/YangC90a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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