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@article{DBLP:journals/jsa/BrandenburgS17,
  author       = {Jens Brandenburg and
                  Benno Stabernack},
  title        = {Simulation-based {HW/SW} co-exploration of the concurrent execution
                  of {HEVC} intra encoding algorithms for heterogeneous multi-core architectures},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {26--42},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2016.12.009},
  doi          = {10.1016/J.SYSARC.2016.12.009},
  timestamp    = {Mon, 24 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jsa/BrandenburgS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jsa/HannigCF17,
  author       = {Frank Hannig and
                  Jo{\~{a}}o M. P. Cardoso and
                  Dietmar Fey},
  title        = {Introduction to the special issue on architecture of computing systems},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {1--2},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2017.04.003},
  doi          = {10.1016/J.SYSARC.2017.04.003},
  timestamp    = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jsa/HannigCF17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jsa/HesselbarthSB17,
  author       = {Sebastian Hesselbarth and
                  Gregor Schewior and
                  Holger Blume},
  title        = {{FPGA} emulation methodology for fast and accurate power estimation
                  of embedded processors},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {14--25},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2016.12.008},
  doi          = {10.1016/J.SYSARC.2016.12.008},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jsa/HesselbarthSB17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jsa/HuangGTZ17,
  author       = {Yujian Huang and
                  Kehua Guo and
                  Yayuan Tang and
                  Lili Zhu},
  title        = {{UDPF:} {A} unified data provision framework for developing dynamic
                  resource-oriented embedded applications},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {52--62},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2017.01.004},
  doi          = {10.1016/J.SYSARC.2017.01.004},
  timestamp    = {Mon, 24 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jsa/HuangGTZ17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jsa/LazcanoMSDPGFOL17,
  author       = {Raquel Lazcano and
                  Daniel Madro{\~{n}}al and
                  Rub{\'{e}}n Salvador and
                  Karol Desnos and
                  Maxime Pelcat and
                  Ra{\'{u}}l Guerra and
                  Himar Fabelo and
                  Samuel Ortega and
                  Sebasti{\'{a}}n L{\'{o}}pez and
                  Gustavo Marrero Callic{\'{o}} and
                  Eduardo Ju{\'{a}}rez Mart{\'{\i}}nez and
                  C{\'{e}}sar Sanz},
  title        = {Porting a PCA-based hyperspectral image dimensionality reduction algorithm
                  for brain cancer detection on a manycore architecture},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {101--111},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2017.05.001},
  doi          = {10.1016/J.SYSARC.2017.05.001},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jsa/LazcanoMSDPGFOL17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jsa/MaSGZZXXSP17,
  author       = {De Ma and
                  Juncheng Shen and
                  Zonghua Gu and
                  Ming Zhang and
                  Xiaolei Zhu and
                  Xiaoqiang Xu and
                  Qi Xu and
                  Yangjing Shen and
                  Gang Pan},
  title        = {Darwin: {A} neuromorphic hardware co-processor based on spiking neural
                  networks},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {43--51},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2017.01.003},
  doi          = {10.1016/J.SYSARC.2017.01.003},
  timestamp    = {Mon, 09 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jsa/MaSGZZXXSP17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jsa/MoreacRLB17,
  author       = {Erwan Moreac and
                  Andr{\'{e}} Rossi and
                  Johann Laurent and
                  Pierre Bomel},
  title        = {Bit-accurate energy estimation for Networks-on-Chip},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {112--124},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2017.05.002},
  doi          = {10.1016/J.SYSARC.2017.05.002},
  timestamp    = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jsa/MoreacRLB17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jsa/ParkKPJ17,
  author       = {Boo{-}Kwang Park and
                  Hyun{-}Woo Kim and
                  Jong Hyuk Park and
                  Young{-}Sik Jeong},
  title        = {Adaptive power management scheme using many-core for maximizing network
                  topology lifetime based on ubiquitous computing},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {63--71},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2017.02.002},
  doi          = {10.1016/J.SYSARC.2017.02.002},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jsa/ParkKPJ17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jsa/PelliccioneKHAM17,
  author       = {Patrizio Pelliccione and
                  Eric Knauss and
                  Rogardt Heldal and
                  Magnus {\AA}gren and
                  Piergiuseppe Mallozzi and
                  Anders Alminger and
                  Daniel Borgentun},
  title        = {Automotive Architecture Framework: The experience of Volvo Cars},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {83--100},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2017.02.005},
  doi          = {10.1016/J.SYSARC.2017.02.005},
  timestamp    = {Sun, 25 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jsa/PelliccioneKHAM17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jsa/XueQZWXZ17,
  author       = {Chun Xue and
                  Keni Qiu and
                  Weigong Zhang and
                  Jing Wang and
                  Yuanchao Xu and
                  Mengying Zhao},
  title        = {Data re-allocation enabled cache locking for embedded systems},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {3--13},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2016.12.002},
  doi          = {10.1016/J.SYSARC.2016.12.002},
  timestamp    = {Wed, 05 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jsa/XueQZWXZ17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jsa/ZaibWHHBWT17,
  author       = {Aurang Zaib and
                  Thomas Wild and
                  Andreas Herkersdorf and
                  Jan Heisswolf and
                  J{\"{u}}rgen Becker and
                  Andreas Weichslgartner and
                  J{\"{u}}rgen Teich},
  title        = {Efficient task spawning for shared memory and message passing in many-core
                  architectures},
  journal      = {J. Syst. Archit.},
  volume       = {77},
  pages        = {72--82},
  year         = {2017},
  url          = {https://doi.org/10.1016/j.sysarc.2017.03.004},
  doi          = {10.1016/J.SYSARC.2017.03.004},
  timestamp    = {Mon, 24 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jsa/ZaibWHHBWT17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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