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@article{DBLP:journals/tcad/AbbaspourFP07,
author = {Soroush Abbaspour and
Hanif Fatemi and
Massoud Pedram},
title = {Parameterized Non-Gaussian Variational Gate Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1495--1508},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.893552},
doi = {10.1109/TCAD.2007.893552},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AbbaspourFP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AhmedTRB07,
author = {Nisar Ahmed and
Mohammad Tehranipoor and
C. P. Ravikumar and
Kenneth M. Butler},
title = {Local At-Speed Scan Enable Generation for Transition Fault Testing
Using Low-Cost Testers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {896--906},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361583},
doi = {10.1109/TCAD.2007.8361583},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AhmedTRB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AineCK07,
author = {Sandip Aine and
P. P. Chakrabarti and
Rajeev Kumar},
title = {An Automated Meta-Level Control Framework for Optimizing the Quality-Time
Tradeoff of {VLSI} Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {1992--2008},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906456},
doi = {10.1109/TCAD.2007.906456},
timestamp = {Mon, 07 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/AineCK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Al-HarbiNA07,
author = {Sultan M. Al{-}Harbi and
Fadel Noor and
Fadi M. Al{-}Turjman},
title = {March {DSS:} {A} New Diagnostic March Test for All Memory Simple Static
Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1713--1720},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895609},
doi = {10.1109/TCAD.2007.895609},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Al-HarbiNA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Al-YamaniDCGG07,
author = {Ahmad A. Al{-}Yamani and
Narendra Devta{-}Prasanna and
Erik Chmelar and
M. Grinchuk and
Arun Gunda},
title = {Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {907--918},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361584},
doi = {10.1109/TCAD.2007.8361584},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Al-YamaniDCGG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AngioliniMCRB07,
author = {Federico Angiolini and
Paolo Meloni and
Salvatore Carta and
Luigi Raffo and
Luca Benini},
title = {A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects
for MPSoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {421--434},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888287},
doi = {10.1109/TCAD.2006.888287},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AngioliniMCRB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Aoyama07,
author = {Kazuo Aoyama},
title = {Design Methods for Symmetric Function Generators Based on Threshold
Elements},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {1934--1946},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906472},
doi = {10.1109/TCAD.2007.906472},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Aoyama07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Baeg07,
author = {Sanghyeon Baeg},
title = {Delay Fault Coverage Enhancement by Partial Clocking for Low-Power
Designs With Heavily Gated Clocks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2215--2221},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.907017},
doi = {10.1109/TCAD.2007.907017},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Baeg07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BalakrishnanT07,
author = {Kedarnath J. Balakrishnan and
Nur A. Touba},
title = {Relationship Between Entropy and Test Data Compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {386--395},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882600},
doi = {10.1109/TCAD.2006.882600},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BalakrishnanT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BalarinP07,
author = {Felice Balarin and
Roberto Passerone},
title = {Specification, Synthesis, and Simulation of Transactor Processes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1749--1762},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895792},
doi = {10.1109/TCAD.2007.895792},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BalarinP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BanerjeeCB07,
author = {Shibaji Banerjee and
Dipanwita Roy Chowdhury and
Bhargab B. Bhattacharya},
title = {An Efficient Scan Tree Design for Compact Test Pattern Set},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1331--1339},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895840},
doi = {10.1109/TCAD.2007.895840},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BanerjeeCB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BazarganD07,
author = {Kia Bazargan and
Andr{\'{e}} DeHon},
title = {Guest Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {201--202},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891079},
doi = {10.1109/TCAD.2007.891079},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BazarganD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeltrameSS07,
author = {Giovanni Beltrame and
Donatella Sciuto and
Cristina Silvano},
title = {Multi-Accuracy Power and Performance Transaction-Level Modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1830--1842},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895790},
doi = {10.1109/TCAD.2007.895790},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeltrameSS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Beyene07,
author = {Wendemagegnehu T. Beyene},
title = {Application of Artificial Neural Networks to Statistical Analysis
and Nonlinear Modeling of High-Speed Interconnect Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {166--176},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882518},
doi = {10.1109/TCAD.2006.882518},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Beyene07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BiswasDPI07,
author = {Partha Biswas and
Nikil D. Dutt and
Laura Pozzi and
Paolo Ienne},
title = {Introduction of Architecturally Visible Storage in Instruction Set
Extensions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {435--446},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.890582},
doi = {10.1109/TCAD.2006.890582},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BiswasDPI07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BondD07,
author = {Bradley N. Bond and
Luca Daniel},
title = {A Piecewise-Linear Moment-Matching Approach to Parameterized Model-Order
Reduction for Highly Nonlinear Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2116--2129},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.907258},
doi = {10.1109/TCAD.2007.907258},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BondD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CaoC07,
author = {Yu Cao and
Lawrence T. Clark},
title = {Mapping Statistical Process Variations Toward Circuit Performance
Variability: An Analytical Modeling Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1866--1873},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895613},
doi = {10.1109/TCAD.2007.895613},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CaoC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangBM07,
author = {Kai{-}Hui Chang and
Valeria Bertacco and
Igor L. Markov},
title = {Simulation-Based Bug Trace Minimization With BMC-Based Refinement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {152--165},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882511},
doi = {10.1109/TCAD.2006.882511},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangBM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChaudharyCHNRW07,
author = {Amitabh Chaudhary and
Danny Z. Chen and
Xiaobo Sharon Hu and
Michael T. Niemier and
Ramprasad Ravichandran and
Kevin Whitton},
title = {Fabricatable Interconnect and Molecular {QCA} Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {1978--1991},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906467},
doi = {10.1109/TCAD.2007.906467},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChaudharyCHNRW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenC07,
author = {Tai{-}Chen Chen and
Yao{-}Wen Chang},
title = {Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity
Correction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1041--1053},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884492},
doi = {10.1109/TCAD.2006.884492},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenGNA07,
author = {Changzhong Chen and
Emad Gad and
Natalie Nakhla and
Ramachandra Achar},
title = {Analysis of Frequency-Dependent Interconnects Using Integrated Congruence
Transform},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1139--1149},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884489},
doi = {10.1109/TCAD.2006.884489},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenGNA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenH07,
author = {Jun Chen and
Lei He},
title = {Efficient In-Package Decoupling Capacitor Optimization for {I/O} Power
Integrity},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {734--738},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888262},
doi = {10.1109/TCAD.2006.888262},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenMS07,
author = {Xiaoyong Chen and
Douglas L. Maskell and
Yang Sun},
title = {Fast Identification of Custom Instructions for Extensible Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {359--368},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883915},
doi = {10.1109/TCAD.2006.883915},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenMS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenZ07,
author = {Ruiming Chen and
Hai Zhou},
title = {An Effective Algorithm for Buffer Insertion in General Circuits Based
on Network Flow},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {2069--2073},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906481},
doi = {10.1109/TCAD.2007.906481},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengLLWH07,
author = {Lerong Cheng and
Fei Li and
Yan Lin and
Phoebe Wong and
Lei He},
title = {Device and Architecture Cooptimization for {FPGA} Power Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1211--1221},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888289},
doi = {10.1109/TCAD.2006.888289},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengLLWH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChiangKSXZ07,
author = {Charles C. Chiang and
Andrew B. Kahng and
Subarna Sinha and
Xu Xu and
Alexander Zelikovsky},
title = {Fast and Efficient Bright-Field {AAPSM} Conflict Detection and Correction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {115--126},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882642},
doi = {10.1109/TCAD.2006.882642},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChiangKSXZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoC07,
author = {Youngjin Cho and
Naehyuck Chang},
title = {Energy-Aware Clock-Frequency Assignment in Microprocessors and Memory
Devices for Dynamic Voltage Scaling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1030--1040},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885835},
doi = {10.1109/TCAD.2006.885835},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoCKHKH07,
author = {Sung Jin Cho and
Un{-}Sook Choi and
Han{-}Doo Kim and
Yoon{-}Hee Hwang and
Jin{-}Gyoung Kim and
Seong{-}Hun Heo},
title = {New Synthesis of One-Dimensional 90/150 Linear Hybrid Group Cellular
Automata},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1720--1724},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895784},
doi = {10.1109/TCAD.2007.895784},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoCKHKH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoP07,
author = {Minsik Cho and
David Z. Pan},
title = {BoxRouter: {A} New Global Router Based on Box Expansion and Progressive
{ILP}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2130--2143},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.907003},
doi = {10.1109/TCAD.2007.907003},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiBMMR07,
author = {Jung Hwan Choi and
Aditya Bansal and
Mesut Meterelliyoz and
Jayathi Murthy and
Kaushik Roy},
title = {Self-Consistent Approach to Leakage Power and Temperature Estimation
to Predict Thermal Runaway in FinFET Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {2059--2068},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906470},
doi = {10.1109/TCAD.2007.906470},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoiBMMR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiCK07,
author = {Yongseok Choi and
Naehyuck Chang and
Taewhan Kim},
title = {{DC-DC} Converter-Aware Power Management for Low-Power Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1367--1381},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.890837},
doi = {10.1109/TCAD.2007.890837},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoiCK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongM07,
author = {Jason Cong and
Kirill Minkovich},
title = {Optimality Study of Logic Synthesis for LUT-Based FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {230--239},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.887922},
doi = {10.1109/TCAD.2006.887922},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DattaGCMLR07,
author = {Animesh Datta and
Ashish Goel and
R. T. Cakici and
Hamid Mahmoodi and
Dheepa Lekshmanan and
Kaushik Roy},
title = {Modeling and Circuit Synthesis for Independently Controlled Double
Gate FinFET Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {1957--1966},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.896320},
doi = {10.1109/TCAD.2007.896320},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DattaGCMLR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DongL07,
author = {Wei Dong and
Peng Li},
title = {Hierarchical Harmonic-Balance Methods for Frequency-Domain Analog-Circuit
Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2089--2101},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.907018},
doi = {10.1109/TCAD.2007.907018},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DongL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FangLCW07,
author = {Jia{-}Wei Fang and
I{-}Jye Lin and
Yao{-}Wen Chang and
Jyh{-}Herng Wang},
title = {A Network-Flow-Based {RDL} Routing Algorithmz for Flip-Chip Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1417--1429},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891364},
doi = {10.1109/TCAD.2007.891364},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FangLCW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GerstlauerSPDG07,
author = {Andreas Gerstlauer and
Dongwan Shin and
Junyu Peng and
Rainer D{\"{o}}mer and
Daniel Gajski},
title = {Automatic Layer-Based Generation of System-On-Chip Bus Communication
Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1676--1687},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895794},
doi = {10.1109/TCAD.2007.895794},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GerstlauerSPDG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhoshBR07,
author = {Swaroop Ghosh and
Swarup Bhunia and
Kaushik Roy},
title = {{CRISTA:} {A} New Paradigm for Low-Power, Variation-Tolerant, and
Adaptive Circuit Synthesis Using Critical Path Isolation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {1947--1956},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.896305},
doi = {10.1109/TCAD.2007.896305},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhoshBR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GielenS07,
author = {Georges G. E. Gielen and
Donatella Sciuto},
title = {Guest Editorial [intro. to the special issue on the 2006 {IEEE/ACM}
Design, Automation and Test in Europe Conference]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {405--407},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.890147},
doi = {10.1109/TCAD.2006.890147},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GielenS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GiunchigliaNT07,
author = {Enrico Giunchiglia and
Massimo Narizzano and
Armando Tacchella},
title = {Quantifier Structure in Search-Based Procedures for QBFs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {497--507},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888264},
doi = {10.1109/TCAD.2006.888264},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GiunchigliaNT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GrecuISP07,
author = {Cristian Grecu and
Andr{\'{e}} Ivanov and
Resve A. Saleh and
Partha Pratim Pande},
title = {Testing Network-on-Chip Communication Fabrics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2201--2214},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.907263},
doi = {10.1109/TCAD.2007.907263},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GrecuISP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuWDZ07,
author = {Zhenyu (Peter) Gu and
Jia Wang and
Robert P. Dick and
Hai Zhou},
title = {Unified Incremental Physical-Level and High-Level Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1576--1588},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895780},
doi = {10.1109/TCAD.2007.895780},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuWDZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuptaKKS07,
author = {Puneet Gupta and
Andrew B. Kahng and
Youngmin Kim and
Dennis Sylvester},
title = {Self-Compensating Design for Reduction of Timing and Leakage Sensitivity
to Systematic Pattern-Dependent Variation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1614--1624},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895759},
doi = {10.1109/TCAD.2007.895759},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuptaKKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuptaKP07,
author = {Puneet Gupta and
Andrew B. Kahng and
Chul{-}Hong Park},
title = {Detailed Placement for Enhanced Control of Resist and Etch CDs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2144--2157},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906998},
doi = {10.1109/TCAD.2007.906998},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuptaKP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HarishBP07,
author = {B. P. Harish and
Navakanta Bhat and
Mahesh B. Patil},
title = {On a Generalized Framework for Modeling the Effects of Process Variations
on Circuit Delay Performance Using Response Surface Methodology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {606--614},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883910},
doi = {10.1109/TCAD.2006.883910},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HarishBP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HeJ07,
author = {Chen He and
Margarida F. Jacome},
title = {Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {817--833},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361577},
doi = {10.1109/TCAD.2007.8361577},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HeJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HeKTX07,
author = {Lei He and
Andrew B. Kahng and
King Ho Tam and
Jinjun Xiong},
title = {Simultaneous Buffer Insertion and Wire Sizing Considering Systematic
{CMP} Variation and Random L\({}_{\mbox{eff}}\) Variation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {845--857},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361579},
doi = {10.1109/TCAD.2007.8361579},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HeKTX07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HealyVEBLLL07,
author = {Michael B. Healy and
Mario Vittes and
Mongkol Ekpanyapong and
Chinnakrishnan S. Ballapuram and
Sung Kyu Lim and
Hsien{-}Hsin S. Lee and
Gabriel H. Loh},
title = {Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {38--52},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883925},
doi = {10.1109/TCAD.2006.883925},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HealyVEBLLL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HollandH07,
author = {Mark Holland and
Scott Hauck},
title = {Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {291--295},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.887926},
doi = {10.1109/TCAD.2006.887926},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HollandH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehCWH07,
author = {Wen{-}Wen Hsieh and
Po{-}Yuan Chen and
Chun{-}Yao Wang and
TingTing Hwang},
title = {A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance
Processor Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2222--2227},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.907260},
doi = {10.1109/TCAD.2007.907260},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiehCWH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuAHKLSS07,
author = {Shiyan Hu and
Charles J. Alpert and
Jiang Hu and
Shrirang K. Karandikar and
Zhuo Li and
Weiping Shi and
Chin Ngai Sze},
title = {Fast Algorithms for Slew-Constrained Minimum Cost Buffering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {2009--2022},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906477},
doi = {10.1109/TCAD.2007.906477},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuAHKLSS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuM07,
author = {Jiang Hu and
Patrick H. Madden},
title = {Guest Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {617--618},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.892957},
doi = {10.1109/TCAD.2007.892957},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JariwalaL07,
author = {Devang Jariwala and
John Lillis},
title = {{RBI:} Simultaneous Placement and Routing Optimization Technique},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {127--141},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883918},
doi = {10.1109/TCAD.2006.883918},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JariwalaL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangLJ07,
author = {Tai{-}Ying Jiang and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
title = {Observability Analysis on {HDL} Descriptions for Effective Functional
Validation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1509--1521},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891366},
doi = {10.1109/TCAD.2007.891366},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangLJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JingFHHHY07,
author = {Tom Tong Jing and
Zhe Feng and
Yu Hu and
Xianlong Hong and
Xiaodong Hu and
Guiying Yan},
title = {lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With
O(nlog n) Complexity},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {2073--2079},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.896291},
doi = {10.1109/TCAD.2007.896291},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JingFHHHY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JingHZZ07,
author = {Ming{-}e Jing and
Yue Hao and
Dian Zhou and
Xuan Zeng},
title = {A Novel Optimization Method for Parametric Yield: Uniform Design Mapping
Distance Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1149--1155},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885833},
doi = {10.1109/TCAD.2006.885833},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JingHZZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KadayifNKS07,
author = {Ismail Kadayif and
Partho Nath and
Mahmut T. Kandemir and
Anand Sivasubramaniam},
title = {Reducing Data {TLB} Power via Compiler-Directed Address Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {312--324},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882599},
doi = {10.1109/TCAD.2006.882599},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KadayifNKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngLX07,
author = {Andrew B. Kahng and
Bao Liu and
Xu Xu},
title = {Statistical Timing Analysis in the Presence of Signal-Integrity Effects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1873--1877},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895771},
doi = {10.1109/TCAD.2007.895771},
timestamp = {Thu, 21 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KahngLX07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngMXZ07,
author = {Andrew B. Kahng and
Ion I. Mandoiu and
Xu Xu and
Alexander Zelikovsky},
title = {Enhanced Design Flow and Optimizations for Multiproject Wafers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {301--311},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883922},
doi = {10.1109/TCAD.2006.883922},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngMXZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KakadeK07,
author = {Jayawant Kakade and
Dimitrios Kagaris},
title = {Minimization of Linear Dependencies Through the Use of Phase Shifters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1877--1882},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.896316},
doi = {10.1109/TCAD.2007.896316},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KakadeK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KangIP07,
author = {Chang Woo Kang and
Ali Iranli and
Massoud Pedram},
title = {A Synthesis Approach for Coarse-Grained Antifuse-Based FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1564--1575},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895781},
doi = {10.1109/TCAD.2007.895781},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KangIP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KangKRA07,
author = {Kunhyuk Kang and
Haldun Kufluoglu and
Kaushik Roy and
Muhammad Ashraful Alam},
title = {Impact of Negative-Bias Temperature Instability in Nanoscale {SRAM}
Array: Modeling and Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1770--1781},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.896317},
doi = {10.1109/TCAD.2007.896317},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KangKRA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KavousianosKN07,
author = {Xrysovalantis Kavousianos and
Emmanouil Kalligeros and
Dimitris Nikolos},
title = {Multilevel Huffman Coding: An Efficient Test-Data Compression Method
for {IP} Cores},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1070--1083},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885830},
doi = {10.1109/TCAD.2006.885830},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KavousianosKN07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KhandelwalS07,
author = {Vishal Khandelwal and
Ankur Srivastava},
title = {Leakage Control Through Fine-Grained Placement and Sizing of Sleep
Transistors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1246--1255},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888282},
doi = {10.1109/TCAD.2006.888282},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KhandelwalS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimK07,
author = {Taewhan Kim and
Jungeun Kim},
title = {Integration of Code Scheduling, Memory Allocation, and Array Binding
for Memory-Access Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {142--151},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882639},
doi = {10.1109/TCAD.2006.882639},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimWK07,
author = {Kyosun Kim and
Kaijie Wu and
Ramesh Karri},
title = {The Robust {QCA} Adder Designs Using Composable {QCA} Building Blocks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {176--183},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883921},
doi = {10.1109/TCAD.2006.883921},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimWK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KodaKF07,
author = {Shinichi Koda and
Chikaaki Kodama and
Kunihiro Fujiyoshi},
title = {Linear Programming-Based Cell Placement With Symmetry Constraints
for Analog {IC} Layout},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {659--668},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891365},
doi = {10.1109/TCAD.2007.891365},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KodaKF07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuI07,
author = {Ja Chun Ku and
Yehea I. Ismail},
title = {On the Scaling of Temperature-Dependent Effects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1882--1888},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895774},
doi = {10.1109/TCAD.2007.895774},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuI07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KumarA07,
author = {Akhilesh Kumar and
Mohab Anis},
title = {Dual-Threshold {CAD} Framework for Subthreshold Leakage Power Aware
FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {53--66},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882595},
doi = {10.1109/TCAD.2006.882595},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KumarA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KumarT07,
author = {Mahilchi Milir Vaseekar Kumar and
Spyros Tragoudas},
title = {High-Quality Transition Fault {ATPG} for Small Delay Defects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {983--989},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361591},
doi = {10.1109/TCAD.2007.8361591},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KumarT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuoCHW07,
author = {Wu{-}An Kuo and
Yi{-}Ling Chiang and
TingTing Hwang and
Allen C.{-}H. Wu},
title = {Performance-Driven Crosstalk Elimination at Postcompiler Level-The
Case of Low-Crosstalk Op-Code Assignment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {564--573},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884861},
doi = {10.1109/TCAD.2006.884861},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuoCHW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuonR07,
author = {Ian Kuon and
Jonathan Rose},
title = {Measuring the Gap Between FPGAs and ASICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {203--215},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884574},
doi = {10.1109/TCAD.2006.884574},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuonR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LasbouyguesWAM07,
author = {B. Lasbouygues and
Robin Wilson and
Nadine Az{\'{e}}mard and
Philippe Maurine},
title = {Temperature- and Voltage-Aware Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {801--815},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884860},
doi = {10.1109/TCAD.2006.884860},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LasbouyguesWAM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeCY07,
author = {Hsun{-}Cheng Lee and
Yao{-}Wen Chang and
Hannah Honghua Yang},
title = {MB\({}^{\mbox{ast}}\)-Tree: {A} Multilevel Floorplanner for Large-Scale
Building-Module Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1430--1444},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891368},
doi = {10.1109/TCAD.2007.891368},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeCY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeT07,
author = {Jinkyu Lee and
Nur A. Touba},
title = {LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {396--401},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882509},
doi = {10.1109/TCAD.2006.882509},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeW07,
author = {Sungjae Lee and
Kevin J. Webb},
title = {A Correlated Diffusion Noise Model for the Field-Effect Transistor},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1782--1789},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895770},
doi = {10.1109/TCAD.2007.895770},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Li07,
author = {Jin{-}Fu Li},
title = {Testing Ternary Content Addressable Memories With Comparison Faults
Using March-Like Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {919--931},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361585},
doi = {10.1109/TCAD.2007.8361585},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Li07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Li07a,
author = {Jin{-}Fu Li},
title = {Transparent-Test Methodologies for Random Access Memories Without/With
{ECC}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1888--1893},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895772},
doi = {10.1109/TCAD.2007.895772},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Li07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiBK07,
author = {Jianhua Li and
Laleh Behjat and
Andrew A. Kennings},
title = {Net Cluster: {A} Net-Reduction-Based Clustering Preprocessing Algorithm
for Partitioning and Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {669--679},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.892339},
doi = {10.1109/TCAD.2007.892339},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiBK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiCL07,
author = {Yih{-}Lang Li and
Hsin{-}Yu Chen and
Chih{-}Ta Lin},
title = {{NEMO:} {A} New Implicit-Connection-Graph-Based Gridless Router With
Multilayer Planes and Pseudo Tile Propagation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {705--718},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891381},
doi = {10.1109/TCAD.2007.891381},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiCL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiCLSC07,
author = {Katherine Shu{-}Min Li and
Yao{-}Wen Chang and
Chung{-}Len Lee and
Chauchin Su and
Jwu E. Chen},
title = {Multilevel Full-Chip Routing With Testability and Yield Enhancement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1625--1636},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895587},
doi = {10.1109/TCAD.2007.895587},
timestamp = {Tue, 07 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiCLSC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiGXP07,
author = {Xin Li and
Padmini Gopalakrishnan and
Yang Xu and
Lawrence T. Pileggi},
title = {Robust Analog/RF Circuit Design With Projection-Based Performance
Modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {2--15},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882513},
doi = {10.1109/TCAD.2006.882513},
timestamp = {Tue, 12 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiGXP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiHZZBYYPC07,
author = {Zhuoyuan Li and
Xianlong Hong and
Qiang Zhou and
Shan Zeng and
Jinian Bian and
Wenjian Yu and
Hannah Honghua Yang and
Vijay Pitchumani and
Chung{-}Kuan Cheng},
title = {Efficient Thermal via Planning Approach and Its Application in 3-D
Floorplanning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {645--658},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885831},
doi = {10.1109/TCAD.2006.885831},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiHZZBYYPC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLC07,
author = {Yih{-}Lang Li and
Jin{-}Yih Li and
Wen{-}Bin Chen},
title = {An Efficient Tile-Based {ECO} Router Using Routing Graph Reduction
and Enhanced Global Routing Flow},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {345--358},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883923},
doi = {10.1109/TCAD.2006.883923},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiLC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLGP07,
author = {Xin Li and
Jiayong Le and
Padmini Gopalakrishnan and
Lawrence T. Pileggi},
title = {Asymptotic Probability Extraction for Nonnormal Performance Distributions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {16--37},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882593},
doi = {10.1109/TCAD.2006.882593},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiLGP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLH07,
author = {Fei Li and
Yan Lin and
Lei He},
title = {Field Programmability of Supply Voltages for {FPGA} Power Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {752--764},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884848},
doi = {10.1109/TCAD.2006.884848},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiLH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiXKCM07,
author = {Chen Li and
Min Xie and
Cheng{-}Kok Koh and
Jason Cong and
Patrick H. Madden},
title = {Routability-Driven Placement and White Space Allocation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {858--871},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361580},
doi = {10.1109/TCAD.2007.8361580},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiXKCM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiZS07,
author = {Zhuo Li and
Nancy Ying Zhou and
Weiping Shi},
title = {Wire Sizing for Non-Tree Topology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {872--880},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361581},
doi = {10.1109/TCAD.2007.8361581},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiZS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinGLW07,
author = {Mingjie Lin and
Abbas El Gamal and
Yi{-}Chang Lu and
S. Simon Wong},
title = {Performance Benefits of Monolithically Stacked 3-D {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {216--229},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.887920},
doi = {10.1109/TCAD.2006.887920},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinGLW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinLC07,
author = {Yung{-}Chieh Lin and
Feng Lu and
Kwang{-}Ting Cheng},
title = {Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern
Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {932--942},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361586},
doi = {10.1109/TCAD.2007.8361586},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LinLC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinYL07,
author = {Saihua Lin and
Huazhong Yang and
Rong Luo},
title = {A Novel gamma d/n, {RLCG} Transmission Line Model Considering Complex
{RC(L)} Loads},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {970--977},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361589},
doi = {10.1109/TCAD.2007.8361589},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinYL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinZ07,
author = {Chuan Lin and
Hai Zhou},
title = {Tradeoff Between Latch and Flop for Min-Period Sequential Circuit
Designs With Crosstalk},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1222--1232},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888273},
doi = {10.1109/TCAD.2006.888273},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Linares-BarrancoS07,
author = {Bernab{\'{e}} Linares{-}Barranco and
Teresa Serrano{-}Gotarredona},
title = {On an Efficient {CAD} Implementation of the Distance Term in Pelgrom's
Mismatch Model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1534--1538},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.893546},
doi = {10.1109/TCAD.2007.893546},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Linares-BarrancoS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LingSB07,
author = {Andrew C. Ling and
Deshanand P. Singh and
Stephen Dean Brown},
title = {{FPGA} {PLB} Architecture Evaluation and Area Optimization Techniques
Using Boolean Satisfiability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1196--1210},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891362},
doi = {10.1109/TCAD.2007.891362},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LingSB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LingappanJ07,
author = {Loganathan Lingappan and
Niraj K. Jha},
title = {Efficient Design for Testability Solution Based on Unsatisfiability
for Register-Transfer Level Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1339--1345},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888268},
doi = {10.1109/TCAD.2006.888268},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LingappanJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuC07,
author = {Chen{-}Wei Liu and
Yao{-}Wen Chang},
title = {Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {693--704},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.892336},
doi = {10.1109/TCAD.2007.892336},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuH07,
author = {Yi{-}Yu Liu and
TingTing Hwang},
title = {Crosstalk-Aware Domino-Logic Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1155--1161},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885740},
doi = {10.1109/TCAD.2006.885740},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuO07,
author = {Fang Liu and
Sule Ozev},
title = {Statistical Test Development for Analog Circuits Under High Process
Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1465--1477},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891373},
doi = {10.1109/TCAD.2007.891373},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuTMWH07,
author = {Pu Liu and
Sheldon X.{-}D. Tan and
Bruce McGaughy and
Lifeng Wu and
Lei He},
title = {TermMerg: An Efficient Terminal-Reduction Method for Interconnect
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1382--1392},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.893554},
doi = {10.1109/TCAD.2007.893554},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuTMWH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LopezCN07,
author = {Juan A. L{\'{o}}pez and
Carlos Carreras and
Octavio Nieto{-}Taladriz},
title = {Improved Interval-Based Characterization of Fixed-Point {LTI} Systems
With Feedback Loops},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {1923--1933},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.896306},
doi = {10.1109/TCAD.2007.896306},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LopezCN07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuoJ07,
author = {Jiong Luo and
Niraj K. Jha},
title = {Power-Efficient Scheduling for Heterogeneous Distributed Real-Time
Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1161--1170},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885736},
doi = {10.1109/TCAD.2006.885736},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuoJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaR07,
author = {James D. Ma and
Rob A. Rutenbar},
title = {Interval-Valued Reduced-Order Statistical Interconnect Modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1602--1613},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895577},
doi = {10.1109/TCAD.2007.895577},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MaR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Macii07,
author = {Enrico Macii},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {1},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888846},
doi = {10.1109/TCAD.2006.888846},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Macii07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MallikSBZ07,
author = {Arindam Mallik and
Debjit Sinha and
Prithviraj Banerjee and
Hai Zhou},
title = {Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based
{ASIC} Design Environment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {447--455},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888291},
doi = {10.1109/TCAD.2006.888291},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MallikSBZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ManiDOZ07,
author = {Murari Mani and
Anirudh Devgan and
Michael Orshansky and
Yaping Zhan},
title = {A Statistical Algorithm for Power- and Timing-Limited Parametric Yield
Optimization of Large Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1790--1802},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895797},
doi = {10.1109/TCAD.2007.895797},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ManiDOZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ManichGF07,
author = {Salvador Manich and
Lucas Garcia{-}Deiros and
Joan Figueras},
title = {Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained
Memory Resources},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {2046--2058},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906465},
doi = {10.1109/TCAD.2007.906465},
timestamp = {Wed, 15 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ManichGF07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarchiBFS07,
author = {Luca De Marchi and
Emanuele Baravelli and
Francesco Franz{\`{e}} and
Nicol{\`{o}} Speciale},
title = {Wavelet Adaptivity for 3-D Device Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {1967--1977},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906474},
doi = {10.1109/TCAD.2007.906474},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MarchiBFS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MeiR07,
author = {Ting Mei and
Jaijeet S. Roychowdhury},
title = {Small-Signal Analysis of Oscillators Using Generalized Multitime Partial
Differential Equations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1054--1069},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885826},
doi = {10.1109/TCAD.2006.885826},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MeiR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MishchenkoCB07,
author = {Alan Mishchenko and
Satrajit Chatterjee and
Robert K. Brayton},
title = {Improvements to Technology Mapping for LUT-Based FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {240--253},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.887925},
doi = {10.1109/TCAD.2006.887925},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MishchenkoCB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MrugalskiPRT07,
author = {Grzegorz Mrugalski and
Artur Pogiel and
Janusz Rajski and
Jerzy Tyszer},
title = {Fault Diagnosis With Convolutional Compactors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1478--1494},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891361},
doi = {10.1109/TCAD.2007.891361},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MrugalskiPRT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukhopadhyaySC07,
author = {Debdeep Mukhopadhyay and
Gaurav Sengar and
Dipanwita Roy Chowdhury},
title = {Hierarchical Verification of Galois Field Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1893--1898},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895755},
doi = {10.1109/TCAD.2007.895755},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukhopadhyaySC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MuraliBM07,
author = {Srinivasan Murali and
Luca Benini and
Giovanni De Micheli},
title = {An Application-Specific Design Methodology for On-Chip Crossbar Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1283--1296},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888284},
doi = {10.1109/TCAD.2006.888284},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MuraliBM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MuttrejaRRJ07,
author = {Anish Muttreja and
Anand Raghunathan and
Srivaths Ravi and
Niraj K. Jha},
title = {Automated Energy/Performance Macromodeling of Embedded Software},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {542--552},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883914},
doi = {10.1109/TCAD.2006.883914},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MuttrejaRRJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MuttrejaRRJ07a,
author = {Anish Muttreja and
Anand Raghunathan and
Srivaths Ravi and
Niraj K. Jha},
title = {Hybrid Simulation for Energy Estimation of Embedded Software},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1843--1854},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895760},
doi = {10.1109/TCAD.2007.895760},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MuttrejaRRJ07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NajmMF07,
author = {Farid N. Najm and
Noel Menezes and
Imad A. Ferzli},
title = {A Yield Model for Integrated Circuits and its Application to Statistical
Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {574--591},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883924},
doi = {10.1109/TCAD.2006.883924},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NajmMF07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NelsonMY07,
author = {Curtis A. Nelson and
Chris J. Myers and
Tomohiro Yoneda},
title = {Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {592--605},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883912},
doi = {10.1109/TCAD.2006.883912},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NelsonMY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Odanaka07,
author = {Shinji Odanaka},
title = {A High-Resolution Method for Quantum Confinement Transport Simulations
in MOSFETs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {80--85},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882531},
doi = {10.1109/TCAD.2006.882531},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Odanaka07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PasrichaD07,
author = {Sudeep Pasricha and
Nikil D. Dutt},
title = {A Framework for Cosynthesis of Memory and Communication Architectures
for MPSoC},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {408--420},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884487},
doi = {10.1109/TCAD.2006.884487},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PasrichaD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PasrichaDB07,
author = {Sudeep Pasricha and
Nikil D. Dutt and
Mohamed Ben{-}Romdhane},
title = {{BMSYN:} Bus Matrix Communication Architecture Synthesis for MPSoC},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1454--1464},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891376},
doi = {10.1109/TCAD.2007.891376},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PasrichaDB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PatelSB07,
author = {Hiren D. Patel and
Sandeep K. Shukla and
Reinaldo A. Bergamaschi},
title = {Heterogeneous Behavioral Hierarchy Extensions for SystemC},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {765--780},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884859},
doi = {10.1109/TCAD.2006.884859},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PatelSB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PaulKKAR07,
author = {Bipul Chandra Paul and
Kunhyuk Kang and
Haldun Kufluoglu and
Muhammad Ashraful Alam and
Kaushik Roy},
title = {Negative Bias Temperature Instability: Estimation and Design for Improved
Reliability of Nanoscale Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {743--751},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884870},
doi = {10.1109/TCAD.2006.884870},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PaulKKAR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PeiJH07,
author = {Wei Pei and
Wen{-}Ben Jone and
Yiming Hu},
title = {Fault Modeling and Detection for Drowsy {SRAM} Caches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1084--1100},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885827},
doi = {10.1109/TCAD.2006.885827},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PeiJH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz07,
author = {Irith Pomeranz},
title = {Invariant States and Redundant Logic in Synchronous Sequential Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1171--1175},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885832},
doi = {10.1109/TCAD.2006.885832},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Generation of Broadside Transition-Fault Test Sets That Detect Four-Way
Bridging Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1311--1319},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891370},
doi = {10.1109/TCAD.2007.891370},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzRV07,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Srikanth Venkataraman},
title = {z-Diagnosis: {A} Framework for Diagnostic Fault Simulation and Test
Generation Utilizing Subsets of Outputs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1700--1712},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895758},
doi = {10.1109/TCAD.2007.895758},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzRV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaoCBS07,
author = {Rajeev R. Rao and
Kaviraj Chopra and
David T. Blaauw and
Dennis Sylvester},
title = {Computing the Soft Error Rate of a Combinational Logic Circuit Using
Parameterized Descriptors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {468--479},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891036},
doi = {10.1109/TCAD.2007.891036},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RaoCBS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RashidzadehAM07,
author = {Rashid Rashidzadeh and
Majid Ahmadi and
William C. Miller},
title = {Test and Measurement of Analog and {RF} Cores in Mixed-Signal SoC
Environment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1855--1865},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895791},
doi = {10.1109/TCAD.2007.895791},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RashidzadehAM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RenPAVN07,
author = {Haoxing Ren and
David Z. Pan and
Charles J. Alpert and
Paul G. Villarrubia and
Gi{-}Joon Nam},
title = {Diffusion-Based Placement Migration With Application on Legalization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2158--2172},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.907005},
doi = {10.1109/TCAD.2007.907005},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RenPAVN07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoyCCH07,
author = {Sanghamitra Roy and
Weijen Chen and
Charlie Chung{-}Ping Chen and
Yu Hen Hu},
title = {Numerically Convex Forms and Their Application in Gate Sizing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1637--1647},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895793},
doi = {10.1109/TCAD.2007.895793},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoyCCH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoyM07,
author = {Jarrod A. Roy and
Igor L. Markov},
title = {Seeing the Forest and the Trees: Steiner Wirelength Optimization in
Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {632--644},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888260},
doi = {10.1109/TCAD.2006.888260},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoyM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoyM07a,
author = {Jarrod A. Roy and
Igor L. Markov},
title = {ECO-System: Embracing the Change in Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2173--2185},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.907271},
doi = {10.1109/TCAD.2007.907271},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoyM07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Ruiz-SautuaMM07,
author = {Rafael Ruiz{-}Sautua and
Mar{\'{\i}}a C. Molina and
Jose Manuel Mendias},
title = {Exploiting Bit-Level Delay Calculations to Soften Read-After-Write
Dependences in Behavioral Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1589--1601},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895570},
doi = {10.1109/TCAD.2007.895570},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Ruiz-SautuaMM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Saint-Laurent07,
author = {Martin Saint{-}Laurent},
title = {A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {834--844},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361578},
doi = {10.1109/TCAD.2007.8361578},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Saint-Laurent07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SalmanDTKF07,
author = {Emre Salman and
Ali Dasdan and
Feroze Taraporevala and
Kayhan K{\"{u}}{\c{c}}{\"{u}}k{\c{c}}akar and
Eby G. Friedman},
title = {Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1114--1125},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885834},
doi = {10.1109/TCAD.2006.885834},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SalmanDTKF07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sangiovanni-Vincentelli07,
author = {Alberto L. Sangiovanni{-}Vincentelli},
title = {Remembering Richard [Obituary, Richard A.Newton]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1357--1366},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.902701},
doi = {10.1109/TCAD.2007.902701},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sangiovanni-Vincentelli07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchirnerD07,
author = {Gunar Schirner and
Rainer D{\"{o}}mer},
title = {Result-Oriented Modeling - {A} Novel Technique for Fast and Accurate
{TLM}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1688--1699},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895757},
doi = {10.1109/TCAD.2007.895757},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SchirnerD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SengarMC07,
author = {Gaurav Sengar and
Debdeep Mukhopadhyay and
Dipanwita Roy Chowdhury},
title = {Secured Flipped Scan-Chain Model for Crypto-Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {2080--2084},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906483},
doi = {10.1109/TCAD.2007.906483},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SengarMC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SenguptaS07,
author = {Dipanjan Sengupta and
Resve A. Saleh},
title = {Generalized Power-Delay Metrics in Deep Submicron {CMOS} Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {183--189},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883926},
doi = {10.1109/TCAD.2006.883926},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SenguptaS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShangDJ07,
author = {Li Shang and
Robert P. Dick and
Niraj K. Jha},
title = {{SLOPES:} Hardware-Software Cosynthesis of Low-Power Real-Time Distributed
Embedded Systems With Dynamically Reconfigurable FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {508--526},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883909},
doi = {10.1109/TCAD.2006.883909},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShangDJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sheehan07,
author = {Bernard N. Sheehan},
title = {Realizable Reduction of {RC} Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1393--1407},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891374},
doi = {10.1109/TCAD.2007.891374},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sheehan07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShekharKE07,
author = {Namrata Shekhar and
Sudhakar Kalla and
Florian Enescu},
title = {Equivalence Verification of Polynomial Datapaths Using Ideal Membership
Testing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1320--1330},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888277},
doi = {10.1109/TCAD.2006.888277},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShekharKE07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiCTFH07,
author = {Jin Shi and
Yici Cai and
Sheldon X.{-}D. Tan and
Jeffrey Fan and
Xianlong Hong},
title = {Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {680--692},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.892337},
doi = {10.1109/TCAD.2007.892337},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShiCTFH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShinK07,
author = {Dongkun Shin and
Jihong Kim},
title = {Optimizing Intratask Voltage Scheduling Using Profile and Data-Flow
Information},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {369--385},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883928},
doi = {10.1109/TCAD.2006.883928},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShinK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShrivastavaPEDNP07,
author = {Aviral Shrivastava and
Sanghyun Park and
Eugene Earlie and
Nikil D. Dutt and
Alexandru Nicolau and
Yunheung Paek},
title = {Automatic Design Space Exploration of Register Bypasses in Embedded
Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2102--2115},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.907066},
doi = {10.1109/TCAD.2007.907066},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ShrivastavaPEDNP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghalBE07,
author = {Love Singhal and
Elaheh Bozorgzadeh and
David Eppstein},
title = {Interconnect Criticality-Driven Delay Relaxation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1803--1817},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.896319},
doi = {10.1109/TCAD.2007.896319},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghalBE07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinhaZS07,
author = {Debjit Sinha and
Hai Zhou and
Narendra V. Shenoy},
title = {Advances in Computation of the Maximum of a Set of Gaussian Random
Variables},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1522--1533},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.893544},
doi = {10.1109/TCAD.2007.893544},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinhaZS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SokolovBY07,
author = {Danil Sokolov and
Alexandre V. Bystrov and
Alexandre Yakovlev},
title = {Direct Mapping of Low-Latency Asynchronous Controllers From STGs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {993--1009},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884416},
doi = {10.1109/TCAD.2006.884416},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SokolovBY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SovianiTE07,
author = {Cristian Soviani and
Olivier Tardieu and
Stephen A. Edwards},
title = {Optimizing Sequential Cycles Through Shannon Decomposition and Retiming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {456--467},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.890583},
doi = {10.1109/TCAD.2006.890583},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SovianiTE07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SpevakG07,
author = {Michael Spevak and
Tibor Grasser},
title = {Discretization of Macroscopic Transport Equations on Non-Cartesian
Coordinate Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1408--1416},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891378},
doi = {10.1109/TCAD.2007.891378},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SpevakG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SridharaS07,
author = {Srinivasa R. Sridhara and
Naresh R. Shanbhag},
title = {Coding for Reliable On-Chip Buses: {A} Class of Fundamental Bounds
and Practical Codes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {977--982},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361590},
doi = {10.1109/TCAD.2007.8361590},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SridharaS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SrivastavaKS07,
author = {Ashish Srivastava and
T. Kachru and
Dennis Sylvester},
title = {Low-Power-Design Space Exploration Considering Process Variation Using
Robust Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {67--79},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882491},
doi = {10.1109/TCAD.2006.882491},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SrivastavaKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StehrGA07,
author = {Guido Stehr and
Helmut E. Graeb and
Kurt Antreich},
title = {Analog Performance Space Exploration by Normal-Boundary Intersection
and by Fourier-Motzkin Elimination},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1733--1748},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895756},
doi = {10.1109/TCAD.2007.895756},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StehrGA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuC07,
author = {Bor{-}Yiing Su and
Yao{-}Wen Chang},
title = {An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1818--1829},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.896307},
doi = {10.1109/TCAD.2007.896307},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuCH07,
author = {Bor{-}Yiing Su and
Yao{-}Wen Chang and
Jiang Hu},
title = {An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing
Considering Routing Obstacles},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {719--733},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.892338},
doi = {10.1109/TCAD.2007.892338},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuCH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SunRRJ07,
author = {Fei Sun and
Srivaths Ravi and
Anand Raghunathan and
Niraj K. Jha},
title = {A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor
Generation for Extensible Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {2035--2045},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906457},
doi = {10.1109/TCAD.2007.906457},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SunRRJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SunWN07,
author = {Welson Sun and
Michael J. Wirthlin and
Stephen Neuendorffer},
title = {{FPGA} Pipeline Synthesis Design Exploration Using Module Selection
and Resource Sharing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {254--265},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.887923},
doi = {10.1109/TCAD.2006.887923},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SunWN07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SzeAHS07,
author = {Chin Ngai Sze and
Charles J. Alpert and
Jiang Hu and
Weiping Shi},
title = {Path-Based Buffer Insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1346--1355},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888281},
doi = {10.1109/TCAD.2006.888281},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SzeAHS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TahooriM07,
author = {Mehdi Baradaran Tahoori and
Subhasish Mitra},
title = {Application-Dependent Delay Testing of FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {553--563},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882503},
doi = {10.1109/TCAD.2006.882503},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TahooriM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TamhankarMSPABM07,
author = {Rutuparna Tamhankar and
Srinivasan Murali and
Stergios Stergiou and
Antonio Pullini and
Federico Angiolini and
Luca Benini and
Giovanni De Micheli},
title = {Timing-Error-Tolerant Network-on-Chip Design Methodology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1297--1310},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891371},
doi = {10.1109/TCAD.2007.891371},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TamhankarMSPABM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TehranipoorR07,
author = {Mohammad Tehranipoor and
Reza M. Rad},
title = {Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based
Nanofabrics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {943--958},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361587},
doi = {10.1109/TCAD.2007.8361587},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TehranipoorR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TessierBNEG07,
author = {Russell Tessier and
Vaughn Betz and
David Neto and
Aaron Egier and
Thiagaraja Gopalsamy},
title = {Power-Efficient {RAM} Mapping Algorithms for {FPGA} Embedded Memory
Blocks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {278--290},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.887924},
doi = {10.1109/TCAD.2006.887924},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TessierBNEG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ThornbergPHOKOC07,
author = {Benny Th{\"{o}}rnberg and
Martin Palkovic and
Qubo Hu and
Leif Olsson and
Per Gunnar Kjeldsberg and
Mattias O'Nils and
Francky Catthoor},
title = {Bit-Width Constrained Memory Hierarchy Optimization for Real-Time
Video Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {781--800},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884569},
doi = {10.1109/TCAD.2006.884569},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ThornbergPHOKOC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TongYCD07,
author = {Dennis K. Y. Tong and
Evangeline F. Y. Young and
Chris C. N. Chu and
Sampath Dechu},
title = {Wire Retiming Problem With Net Topology Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1648--1660},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895583},
doi = {10.1109/TCAD.2007.895583},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TongYCD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TuanRDTK07,
author = {Tim Tuan and
Arifur Rahman and
Satyaki Das and
Steven Trimberger and
Sean Kao},
title = {A 90-nm Low-Power {FPGA} for Battery-Powered Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {296--300},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885731},
doi = {10.1109/TCAD.2006.885731},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TuanRDTK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TummeltshammerHP07,
author = {Peter Tummeltshammer and
James C. Hoe and
Markus P{\"{u}}schel},
title = {Time-Multiplexed Multiple-Constant Multiplication},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1551--1563},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.893549},
doi = {10.1109/TCAD.2007.893549},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TummeltshammerHP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VaraprasadPJA07,
author = {B. K. S. V. L. Varaprasad and
Lalit M. Patnaik and
Hirisave S. Jamadagni and
V. K. Agrawal},
title = {A New {ATPG} Technique (ExpoTan) for Testing Analog Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {189--196},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882596},
doi = {10.1109/TCAD.2006.882596},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VaraprasadPJA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VecianaLHMS07,
author = {Gustavo de Veciana and
Marcello Lajolo and
Chen He and
Enrico Macii and
Sachin S. Sapatnekar},
title = {In Memoriam: Margarida F. Jacome},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1549--1550},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.903725},
doi = {10.1109/TCAD.2007.903725},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VecianaLHMS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WagnerBA07,
author = {Ilya Wagner and
Valeria Bertacco and
Todd M. Austin},
title = {Microprocessor Verification via Feedback-Adjusted Markov Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1126--1138},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884494},
doi = {10.1109/TCAD.2006.884494},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WagnerBA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangGDK07,
author = {Gang Wang and
Wenrui Gong and
Brian DeRenzi and
Ryan Kastner},
title = {Ant Colony Optimizations for Resource- and Timing-Constrained Operation
Scheduling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1010--1029},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885829},
doi = {10.1109/TCAD.2006.885829},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangGDK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangM07,
author = {Baohua Wang and
Pinaki Mazumder},
title = {Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {325--344},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883919},
doi = {10.1109/TCAD.2006.883919},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangZ07,
author = {Jia Wang and
Hai Zhou},
title = {Optimal Jumper Insertion for Antenna Avoidance Considering Antenna
Charge Sharing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1445--1453},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.893551},
doi = {10.1109/TCAD.2007.893551},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WedlerSBK07,
author = {Markus Wedler and
Dominik Stoffel and
Raik Brinkmann and
Wolfgang Kunz},
title = {A Normalization Method for Arithmetic Data-Path Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {1909--1922},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906458},
doi = {10.1109/TCAD.2007.906458},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WedlerSBK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WeiDT07,
author = {Ying Wei and
Alex Doboli and
Hua Tang},
title = {Systematic Methodology for Designing Reconfigurable DeltaSigma Modulator
Topologies for Multimode Communication Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {480--496},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885734},
doi = {10.1109/TCAD.2006.885734},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WeiDT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WongB07,
author = {Ngai Wong and
Venkataramanan Balakrishnan},
title = {Fast Positive-Real Balanced Truncation Via Quadratic Alternating Direction
Implicit Iteration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1725--1731},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895617},
doi = {10.1109/TCAD.2007.895617},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WongB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WongML07,
author = {Eric Wong and
Jacob R. Minz and
Sung Kyu Lim},
title = {Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {2023--2034},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906463},
doi = {10.1109/TCAD.2007.906463},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WongML07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuWLW07,
author = {Huaizhi Wu and
Martin D. F. Wong and
I{-}Min Liu and
Yusu Wang},
title = {Placement-Proximity-Based Voltage Island Grouping Under Performance
Requirement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1256--1269},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888270},
doi = {10.1109/TCAD.2006.888270},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuWLW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiongH07,
author = {Jinjun Xiong and
Lei He},
title = {Probabilistic Transitive-Closure Ordering and Its Application on Variational
Buffer Insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {739--742},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891360},
doi = {10.1109/TCAD.2007.891360},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XiongH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiongZH07,
author = {Jinjun Xiong and
Vladimir Zolotov and
Lei He},
title = {Robust Extraction of Spatial Correlation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {619--631},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884403},
doi = {10.1109/TCAD.2006.884403},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XiongZH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuCJ07,
author = {Fei Xu and
Chip{-}Hong Chang and
Ching{-}Chuen Jong},
title = {Design of Low-Complexity {FIR} Filters Based on Signed-Powers-of-Two
Coefficients With Reusable Common Subexpressions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1898--1907},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895615},
doi = {10.1109/TCAD.2007.895615},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuCJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuNC07,
author = {Qiang Xu and
Nicola Nicolici and
Krishnendu Chakrabarty},
title = {Test Wrapper Design and Optimization Under Power Constraints for Embedded
Cores With Multiple Clock Domains},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1539--1547},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.893556},
doi = {10.1109/TCAD.2007.893556},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XuNC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangC07,
author = {Kai Yang and
Kwang{-}Ting Cheng},
title = {Silicon Debug for Timing Errors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {2084--2088},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906479},
doi = {10.1109/TCAD.2007.906479},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YangC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangGZDS07,
author = {Yonghong Yang and
Zhenyu (Peter) Gu and
Changyun Zhu and
Robert P. Dick and
Li Shang},
title = {{ISAC:} Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {86--99},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882589},
doi = {10.1109/TCAD.2006.882589},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangGZDS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangK07,
author = {Bo Yang and
Ramesh Karri},
title = {Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate
Technique},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1763--1769},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.896308},
doi = {10.1109/TCAD.2007.896308},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YehCCW07,
author = {Jen{-}Chieh Yeh and
Kuo{-}Liang Cheng and
Yung{-}Fa Chou and
Cheng{-}Wen Wu},
title = {Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test
Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1101--1113},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885828},
doi = {10.1109/TCAD.2006.885828},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YehCCW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YehM07,
author = {Chao{-}Yang Yeh and
Malgorzata Marek{-}Sadowska},
title = {Timing-Aware Power-Noise Reduction in Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {3},
pages = {527--541},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883917},
doi = {10.1109/TCAD.2006.883917},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YehM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YiKH07,
author = {Youngmin Yi and
Dohyung Kim and
Soonhoi Ha},
title = {Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual
Synchronization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {12},
pages = {2186--2200},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.907048},
doi = {10.1109/TCAD.2007.907048},
timestamp = {Fri, 15 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YiKH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YiannacourasSR07,
author = {Peter Yiannacouras and
J. Gregory Steffan and
Jonathan Rose},
title = {Exploration and Customization of FPGA-Based Soft Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {266--277},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.887921},
doi = {10.1109/TCAD.2006.887921},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YiannacourasSR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YonedaM07,
author = {Tomohiro Yoneda and
Chris J. Myers},
title = {Synthesis of Timed Circuits Based on Decomposition},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1177--1195},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888269},
doi = {10.1109/TCAD.2006.888269},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YonedaM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhanS07,
author = {Yong Zhan and
Sachin S. Sapatnekar},
title = {High-Efficiency Green Function-Based Thermal Simulation Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1661--1675},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895754},
doi = {10.1109/TCAD.2007.895754},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhanS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangGJ07,
author = {Rui Zhang and
Pallav Gupta and
Niraj K. Jha},
title = {Majority and Minority Network Synthesis With Application to QCA-,
SET-, and TPL-Based Nanotechnologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1233--1245},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888267},
doi = {10.1109/TCAD.2006.888267},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangGJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouHLL07,
author = {Zai{-}Fa Zhou and
Qing{-}An Huang and
Wei{-}Hua Li and
Wei Lu},
title = {A Novel 3-D Dynamic Cellular Automata Model for Photoresist-Etching
Process Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {100--114},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882510},
doi = {10.1109/TCAD.2006.882510},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhouHLL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouWS07,
author = {Lili Zhou and
Cherry Wakayama and
C.{-}J. Richard Shi},
title = {{CASCADE:} {A} Standard Supercell Design Methodology With Congestion-Driven
Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale
Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1270--1282},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888266},
doi = {10.1109/TCAD.2006.888266},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhouWS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouYCZHCSCSC07,
author = {Shuo Zhou and
Bo Yao and
Hongyu Chen and
Yi Zhu and
Michael D. Hutton and
Truman Collins and
Sridhar Srinivasan and
Nan{-}Chi Chou and
Peter Suaris and
Chung{-}Kuan Cheng},
title = {Efficient Timing Analysis With Known False Paths Using Biclique Covering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {959--969},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361588},
doi = {10.1109/TCAD.2007.8361588},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhouYCZHCSCSC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhuPCRBK07,
author = {Zhengyong Zhu and
He Peng and
Chung{-}Kuan Cheng and
Khosro Rouz and
Manjit Borah and
Ernest S. Kuh},
title = {Two-Stage Newton-Raphson Method for Transistor-Level Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {5},
pages = {881--895},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.8361582},
doi = {10.1109/TCAD.2007.8361582},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhuPCRBK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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