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@article{DBLP:journals/todaes/AdityaMR00,
author = {Shail Aditya and
Scott A. Mahlke and
B. Ramakrishna Rau},
title = {Code size minimization and retargetable assembly for custom {EPIC}
and {VLIW} instruction formats},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {4},
pages = {752--773},
year = {2000},
url = {https://doi.org/10.1145/362652.362658},
doi = {10.1145/362652.362658},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/AdityaMR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BaharLM00,
author = {R. Iris Bahar and
Ernest T. Lampe and
Enrico Macii},
title = {Power optimization of technology-dependent circuits based on symbolic
computation of logic implications},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {267--293},
year = {2000},
url = {https://doi.org/10.1145/348019.348028},
doi = {10.1145/348019.348028},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/BaharLM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BalakrishnanK00,
author = {M. Balakrishnan and
Heman Khanna},
title = {Allocation of {FIFO} structures in {RTL} data paths},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {294--310},
year = {2000},
url = {https://doi.org/10.1145/348019.348044},
doi = {10.1145/348019.348044},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/BalakrishnanK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BeniniM00,
author = {Luca Benini and
Giovanni De Micheli},
title = {System-level power optimization: techniques and tools},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {2},
pages = {115--192},
year = {2000},
url = {https://doi.org/10.1145/335043.335044},
doi = {10.1145/335043.335044},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/BeniniM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BeniniM00a,
author = {Luca Benini and
Giovanni De Micheli},
title = {Synthesis of low-power selectively-clocked systems from high-level
specification},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {311--321},
year = {2000},
url = {https://doi.org/10.1145/348019.348050},
doi = {10.1145/348019.348050},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/BeniniM00a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BlytheW00,
author = {Stephen A. Blythe and
Robert A. Walker},
title = {Efficient optimal design space characterization methodologies},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {322--336},
year = {2000},
url = {https://doi.org/10.1145/348019.348058},
doi = {10.1145/348019.348058},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/BlytheW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BoglioloBM00,
author = {Alessandro Bogliolo and
Luca Benini and
Giovanni De Micheli},
title = {Regression-based {RTL} power modeling},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {337--372},
year = {2000},
url = {https://doi.org/10.1145/348019.348081},
doi = {10.1145/348019.348081},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/BoglioloBM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BommuOC00,
author = {Surendra Bommu and
Niall O'Neill and
Maciej J. Ciesielski},
title = {Retiming-based factorization for sequential logic optimization},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {373--398},
year = {2000},
url = {https://doi.org/10.1145/348019.348068},
doi = {10.1145/348019.348068},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/BommuOC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/CarchioloMM00,
author = {Vincenza Carchiolo and
Michele Malgeri and
Giuseppe Mangioni},
title = {Hardware/software synthesis of formal specifications in codesign of
embedded systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {399--432},
year = {2000},
url = {https://doi.org/10.1145/348019.348093},
doi = {10.1145/348019.348093},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/CarchioloMM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChangZW00,
author = {Yao{-}Wen Chang and
Kai Zhu and
D. F. Wong},
title = {Timing-driven routing for symmetrical array-based FPGAs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {433--450},
year = {2000},
url = {https://doi.org/10.1145/348019.348101},
doi = {10.1145/348019.348101},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/ChangZW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/CongH00,
author = {Jason Cong and
Yean{-}Yow Hwang},
title = {Structural gate decomposition for depth-optimal technology mapping
in LUT-based {FPGA} designs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {2},
pages = {193--225},
year = {2000},
url = {https://doi.org/10.1145/335043.335045},
doi = {10.1145/335043.335045},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/CongH00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/EijkMPZBMJ00,
author = {Koen van Eijk and
Bart Mesman and
Carlos A. Alba Pinto and
Qin Zhao and
Marco Bekooij and
Jef L. van Meerbergen and
Jochen A. G. Jess},
title = {Constraint analysis for code generation: basic techniques and applications
in {FACTS}},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {4},
pages = {774--793},
year = {2000},
url = {https://doi.org/10.1145/362652.362660},
doi = {10.1145/362652.362660},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/EijkMPZBMJ00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/FangW00,
author = {Wen{-}Jong Fang and
Allen C.{-}H. Wu},
title = {Multiway {FPGA} partitioning by fully exploiting design hierarchy},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {1},
pages = {34--50},
year = {2000},
url = {https://doi.org/10.1145/329458.329463},
doi = {10.1145/329458.329463},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/FangW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/GeloshS00,
author = {Donald S. Gelosh and
Dorothy E. Setliff},
title = {Modeling layout tools to derive forward estimates of area and delay
at the {RTL} level},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {451--491},
year = {2000},
url = {https://doi.org/10.1145/348019.348148},
doi = {10.1145/348019.348148},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/GeloshS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/GogniatABP00,
author = {Guy Gogniat and
Michel Auguin and
Luc Bianco and
Alain Pegatoquet},
title = {A codesign back-end approach for embedded system design},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {492--509},
year = {2000},
url = {https://doi.org/10.1145/348019.348156},
doi = {10.1145/348019.348156},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/GogniatABP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/GuptaH00,
author = {Avaneendra Gupta and
John P. Hayes},
title = {{CLIP:} integer-programming-based optimal layout synthesis of 2D {CMOS}
cells},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {510--547},
year = {2000},
url = {https://doi.org/10.1145/348019.348234},
doi = {10.1145/348019.348234},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/GuptaH00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/HsiaoRP00,
author = {Michael S. Hsiao and
Elizabeth M. Rudnick and
Janak H. Patel},
title = {Dynamic state traversal for sequential circuit test generation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {548--565},
year = {2000},
url = {https://doi.org/10.1145/348019.348288},
doi = {10.1145/348019.348288},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/HsiaoRP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Hsiung00,
author = {Pao{-}Ann Hsiung},
title = {{CMAPS:} a cosynthesis methodology for application-oriented parallel
systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {1},
pages = {51--81},
year = {2000},
url = {https://doi.org/10.1145/329458.329465},
doi = {10.1145/329458.329465},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Hsiung00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/HwangW00,
author = {Chi{-}Hong Hwang and
Allen C.{-}H. Wu},
title = {A predictive system shutdown method for energy saving of event-driven
computation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {2},
pages = {226--241},
year = {2000},
url = {https://doi.org/10.1145/335043.335046},
doi = {10.1145/335043.335046},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/HwangW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Irwin00,
author = {Mary Jane Irwin},
title = {Editorial},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {265--266},
year = {2000},
url = {https://doi.org/10.1145/348019.348027},
doi = {10.1145/348019.348027},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Irwin00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/JhaD00,
author = {Pradip K. Jha and
Nikil D. Dutt},
title = {High-level library mapping for memories},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {566--603},
year = {2000},
url = {https://doi.org/10.1145/348019.348297},
doi = {10.1145/348019.348297},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/JhaD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LalgudiPP00,
author = {Kumar N. Lalgudi and
Marios C. Papaefthymiou and
Miodrag Potkonjak},
title = {Optimizing computations for effective block-processing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {604--630},
year = {2000},
url = {https://doi.org/10.1145/348019.348304},
doi = {10.1145/348019.348304},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LalgudiPP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LeupersB00,
author = {Rainer Leupers and
Steven Bashford},
title = {Graph-based code selection techniques for embedded processors},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {4},
pages = {794--814},
year = {2000},
url = {https://doi.org/10.1145/362652.362661},
doi = {10.1145/362652.362661},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LeupersB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LongIA00,
author = {David E. Long and
Mahesh A. Iyer and
Miron Abramovici},
title = {{FILL} and {FUNI:} algorithms to identify illegal states and sequentially
untestable faults},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {631--657},
year = {2000},
url = {https://doi.org/10.1145/348019.348311},
doi = {10.1145/348019.348311},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/LongIA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/MarculescuMP00,
author = {Diana Marculescu and
Radu Marculescu and
Massoud Pedram},
title = {Stochastic sequential machine synthesis with application to constrained
sequence generation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {658--681},
year = {2000},
url = {https://doi.org/10.1145/348019.348566},
doi = {10.1145/348019.348566},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/MarculescuMP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Marwedel00,
author = {Peter Marwedel},
title = {Guest Editorial},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {4},
pages = {749--751},
year = {2000},
url = {https://doi.org/10.1145/362652.362654},
doi = {10.1145/362652.362654},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Marwedel00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/MehtaS00,
author = {Dinesh P. Mehta and
Naveed A. Sherwani},
title = {On the use of flexible, rectilinear blocks to obtain minimum-area
floorplans in mixed block and cell designs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {1},
pages = {82--97},
year = {2000},
url = {https://doi.org/10.1145/329458.329470},
doi = {10.1145/329458.329470},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/MehtaS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PandaDN00,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
title = {On-chip vs. off-chip memory: the data partitioning problem in embedded
processor-based systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {682--704},
year = {2000},
url = {https://doi.org/10.1145/348019.348570},
doi = {10.1145/348019.348570},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/PandaDN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PeesHM00,
author = {Stefan Pees and
Andreas Hoffmann and
Heinrich Meyr},
title = {Retargetable compiled simulation of embedded processors using a machine
description language},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {4},
pages = {815--834},
year = {2000},
url = {https://doi.org/10.1145/362652.362662},
doi = {10.1145/362652.362662},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PeesHM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/RaimiHN00,
author = {Richard Raimi and
Ramin Hojati and
Kedar S. Namjoshi},
title = {Environment modeling and language universality},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {705--725},
year = {2000},
url = {https://doi.org/10.1145/348019.348572},
doi = {10.1145/348019.348572},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/RaimiHN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SantosHEEJ00,
author = {Luiz C. V. dos Santos and
Marc J. M. Heijligers and
C. A. J. van Eijk and
J. Van Eijnhoven and
Jochen A. G. Jess},
title = {A code-motion pruning technique for global scheduling},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {1},
pages = {1--38},
year = {2000},
url = {https://doi.org/10.1145/329458.329461},
doi = {10.1145/329458.329461},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/SantosHEEJ00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SapatnekarC00,
author = {Sachin S. Sapatnekar and
Weitong Chuang},
title = {Power-delay optimizations in gate sizing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {1},
pages = {98--114},
year = {2000},
url = {https://doi.org/10.1145/329458.329473},
doi = {10.1145/329458.329473},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/SapatnekarC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SudarsanamM00,
author = {Ashok Sudarsanam and
Sharad Malik},
title = {Simultaneous reference allocation in code generation for dual data
memory bank ASIPs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {2},
pages = {242--264},
year = {2000},
url = {https://doi.org/10.1145/335043.335047},
doi = {10.1145/335043.335047},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/SudarsanamM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Yan00,
author = {Jin{-}Tai Yan},
title = {Three-layer bubble-sorting-based nonManhattan channel routing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {726--734},
year = {2000},
url = {https://doi.org/10.1145/348019.350285},
doi = {10.1145/348019.350285},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/Yan00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/YangCHT00,
author = {Cheng{-}Hsing Yang and
Sao{-}Jie Chen and
Jan{-}Ming Ho and
Chia{-}Chun Tsai},
title = {Efficient routability check algorithms for segmented channel routing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {3},
pages = {735--747},
year = {2000},
url = {https://doi.org/10.1145/348019.348574},
doi = {10.1145/348019.348574},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/YangCHT00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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