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@article{DBLP:journals/tvlsi/AdyaM03,
author = {Saurabh N. Adya and
Igor L. Markov},
title = {Fixed-outline floorplanning: enabling hierarchical design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1120--1135},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817546},
doi = {10.1109/TVLSI.2003.817546},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AdyaM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AzadpourK03,
author = {M. A. Azadpour and
T. S. Kalkur},
title = {A clock interconnect extractor for multigigahertz frequencies incorporating
inductance effect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1143--1146},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817544},
doi = {10.1109/TVLSI.2003.817544},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AzadpourK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AziziNM03,
author = {Navid Azizi and
Farid N. Najm and
Andreas Moshovos},
title = {Low-leakage asymmetric-cell {SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {701--715},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816139},
doi = {10.1109/TVLSI.2003.816139},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AziziNM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BashirullahLC03,
author = {Rizwan Bashirullah and
Wentai Liu and
Ralph K. Cavin III},
title = {Current-mode signaling in deep submicrometer global interconnects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {406--417},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812366},
doi = {10.1109/TVLSI.2003.812366},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BashirullahLC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BeniniMMPS03,
author = {Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino and
Riccardo Scarsi},
title = {Scheduling battery usage in mobile systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1136--1143},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817555},
doi = {10.1109/TVLSI.2003.817555},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BeniniMMPS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhanjaR03,
author = {Sanjukta Bhanja and
N. Ranganathan},
title = {Switching activity estimation of {VLSI} circuits using Bayesian networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {558--567},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816144},
doi = {10.1109/TVLSI.2003.816144},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhanjaR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BlaauwSO03,
author = {David T. Blaauw and
Supamas Sirichotiyakul and
Chanhee Oh},
title = {Driver modeling and alignment for worst-case delay noise},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {157--166},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.808448},
doi = {10.1109/TVLSI.2002.808448},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BlaauwSO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaoHHKMOSS03,
author = {Yu Cao and
Chenming Hu and
Xuejue Huang and
Andrew B. Kahng and
Igor L. Markov and
Michael Oliver and
Dirk Stroobandt and
Dennis Sylvester},
title = {Improved a priori interconnect predictions and technology extrapolation
in the {GTX} system},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {3--14},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.808479},
doi = {10.1109/TVLSI.2002.808479},
timestamp = {Fri, 07 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CaoHHKMOSS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Chakrabarty03,
author = {Krishnendu Chakrabarty},
title = {A synthesis-for-transparency approach for hierarchical and system-on-a-chip
test},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {167--179},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810784},
doi = {10.1109/TVLSI.2003.810784},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Chakrabarty03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangRL03,
author = {Yen{-}Jen Chang and
Shanq{-}Jang Ruan and
Feipei Lai},
title = {Design and analysis of low-power cache using two-level filter scheme},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {568--580},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812292},
doi = {10.1109/TVLSI.2003.812292},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangRL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenMB03,
author = {Lauren Hui Chen and
Malgorzata Marek{-}Sadowska and
Forrest Brewer},
title = {Buffer delay change in the presence of power and ground noise},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {461--473},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812310},
doi = {10.1109/TVLSI.2003.812310},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenMB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenN03,
author = {T. Chen and
S. Naffziger},
title = {Comparison of adaptive body bias {(ABB)} and adaptive supply voltage
{(ASV)} for improving delay and leakage under the presence of process
variation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {888--899},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817120},
doi = {10.1109/TVLSI.2003.817120},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenN03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenWW03,
author = {Oscal T.{-}C. Chen and
Sandy Wang and
Yi{-}Wen Wu},
title = {Minimization of switching activities of partial products for designing
low-power multipliers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {418--433},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810788},
doi = {10.1109/TVLSI.2003.810788},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenWW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Christie03,
author = {Phillip Christie},
title = {Guest editorial: System-level interconnect prediction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {1--2},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810753},
doi = {10.1109/TVLSI.2003.810753},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Christie03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChristieG03,
author = {Phillip Christie and
Jos{\'{e}} Pineda de Gyvez},
title = {Prelayout interconnect yield prediction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {55--59},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.808461},
doi = {10.1109/TVLSI.2002.808461},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChristieG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CodrescuNMW03,
author = {Lucian Codrescu and
S. Nugent and
James D. Meindl and
D. Scott Wills},
title = {Modeling technology impact on cluster microprocessor performance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {909--920},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817512},
doi = {10.1109/TVLSI.2003.817512},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CodrescuNMW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DambreVSC03,
author = {Joni Dambre and
Peter Verplaetse and
Dirk Stroobandt and
Jan Van Campenhout},
title = {A comparison of various terminal-gate relationships for interconnect
prediction in {VLSI} circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {24--34},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.808454},
doi = {10.1109/TVLSI.2002.808454},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DambreVSC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DeB03,
author = {Vivek De and
Luca Benini},
title = {Guest editorial},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {753--754},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.818875},
doi = {10.1109/TVLSI.2003.818875},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DeB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DingM03,
author = {Li Ding and
Pinaki Mazumder},
title = {Simultaneous switching noise analysis using application specific device
modeling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1146--1152},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817548},
doi = {10.1109/TVLSI.2003.817548},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DingM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DoumarI03,
author = {Abderrahim Doumar and
Hideo Ito},
title = {Detecting, diagnosing, and tolerating faults in SRAM-based field programmable
gate arrays: a survey},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {386--405},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.801609},
doi = {10.1109/TVLSI.2002.801609},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DoumarI03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EjniouiR03,
author = {Abdel Ejnioui and
N. Ranganathan},
title = {Multiterminal net routing for partial crossbar-based multi-FPGA systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {71--78},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.800523},
doi = {10.1109/TVLSI.2002.800523},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EjniouiR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EjniouiR03a,
author = {Abdel Ejnioui and
N. Ranganathan},
title = {Routing on field-programmable switch matrices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {283--287},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810778},
doi = {10.1109/TVLSI.2003.810778},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EjniouiR03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ElboimKG03,
author = {Y. Elboim and
Avinoam Kolodny and
Ran Ginosar},
title = {A clock-tuning circuit for system-on-chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {616--626},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812371},
doi = {10.1109/TVLSI.2003.812371},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ElboimKG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FelicijanF03,
author = {T. Felicijan and
Stephen B. Furber},
title = {An asynchronous ternary logic signaling system},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1114--1119},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.819571},
doi = {10.1109/TVLSI.2003.819571},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FelicijanF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GrunHDN03,
author = {Peter Grun and
Ashok Halambi and
Nikil D. Dutt and
Alexandru Nicolau},
title = {RTGEN-an algorithm for automatic generation of reservation tables
from architectural descriptions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {731--737},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.813011},
doi = {10.1109/TVLSI.2003.813011},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GrunHDN03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuptaN03,
author = {Subodh Gupta and
Farid N. Najm},
title = {Energy and peak-current per-cycle estimation at {RTL}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {525--537},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.800534},
doi = {10.1109/TVLSI.2002.800534},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuptaN03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HadjiyiannisD03,
author = {George Hadjiyiannis and
Srinivas Devadas},
title = {Techniques for accurate performance evaluation in architecture exploration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {601--615},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812290},
doi = {10.1109/TVLSI.2003.812290},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HadjiyiannisD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HansonHAKB03,
author = {Heather Hanson and
M. S. Hrishikesh and
Vikas Agarwal and
Stephen W. Keckler and
Doug Burger},
title = {Static energy reduction techniques for microprocessor caches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {303--313},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812370},
doi = {10.1109/TVLSI.2003.812370},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HansonHAKB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HarrisN03,
author = {David M. Harris and
Sam Naffziger},
title = {Correction to "statistical clock skew modeling with data delay variations"},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {295--296},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.814663},
doi = {10.1109/TVLSI.2003.814663},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HarrisN03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeydariP03,
author = {Payam Heydari and
Massoud Pedram},
title = {Ground bounce in digital {VLSI} circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {180--193},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810785},
doi = {10.1109/TVLSI.2003.810785},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeydariP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HongW03,
author = {Jin{-}Hua Hong and
Cheng{-}Wen Wu},
title = {Cellular-array modular multiplier for fast {RSA} public-key cryptosystem
based on modified Booth's algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {474--484},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812308},
doi = {10.1109/TVLSI.2003.812308},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HongW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HossainVC03,
author = {Razak Hossain and
Fabrizio Viglione and
Marco Cavalli},
title = {Designing fast on-chip interconnects for deep submicrometer technologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {276--280},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810781},
doi = {10.1109/TVLSI.2003.810781},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HossainVC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Hsia03,
author = {Shih{-}Chang Hsia},
title = {Parallel {VLSI} design for a real-time video-impulse noise-reduction
processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {651--658},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816135},
doi = {10.1109/TVLSI.2003.816135},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Hsia03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuttonAL03,
author = {M. Hutton and
K. Adibsamii and
A. Leaver},
title = {Adaptive delay estimation for partitioning-driven {PLD} placement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {60--63},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.808424},
doi = {10.1109/TVLSI.2002.808424},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuttonAL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangA03,
author = {Sungbae Hwang and
Jacob A. Abraham},
title = {Test data compression and test time reduction using an embedded microprocessor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {853--862},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817140},
doi = {10.1109/TVLSI.2003.817140},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ImIGHS03,
author = {Hyunsik Im and
Takashi Inukai and
Hiroyuki Gomyo and
Toshiro Hiramoto and
Takayasu Sakurai},
title = {{VTCMOS} characteristics and its optimum conditions predicted by a
compact analytical model},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {755--761},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.814320},
doi = {10.1109/TVLSI.2003.814320},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ImIGHS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Ismail03,
author = {Yehea I. Ismail},
title = {Improved model-order reduction by using spacial information in moments},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {900--908},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817138},
doi = {10.1109/TVLSI.2003.817138},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Ismail03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoshiCFASYS03,
author = {Rajiv V. Joshi and
Ching{-}Te Chuang and
Samuel K. H. Fung and
Fari Assaderaghi and
Melanie Sherony and
I. Yang and
Ghavam V. Shahidi},
title = {{PD/SOI} {SRAM} performance in presence of gate-to-body tunneling
current},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1106--1113},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817552},
doi = {10.1109/TVLSI.2003.817552},
timestamp = {Fri, 07 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JoshiCFASYS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KarandikarS03,
author = {Shrirang K. Karandikar and
Sachin S. Sapatnekar},
title = {Technology mapping for {SOI} domino logic incorporating solutions
for the parasitic bipolar effect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1094--1105},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817137},
doi = {10.1109/TVLSI.2003.817137},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KarandikarS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KeshavarziRHD03,
author = {Ali Keshavarzi and
Kaushik Roy and
Charles F. Hawkins and
Vivek De},
title = {Multiple-parameter {CMOS} {IC} testing with increased sensitivity
for I\({}_{\mbox{DDQ}}\)},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {863--870},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812298},
doi = {10.1109/TVLSI.2003.812298},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KeshavarziRHD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimJKSLK03,
author = {Ki{-}Wook Kim and
Seong{-}Ook Jung and
Taewhan Kim and
Prashant Saxena and
C. L. Liu and
S.{-}M. S. Kang},
title = {Coupling delay optimization by temporal decorrelation using dual threshold
voltage technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {879--887},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817111},
doi = {10.1109/TVLSI.2003.817111},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimJKSLK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimJNLK03,
author = {Ki{-}Wook Kim and
Seong{-}Ook Jung and
Unni Narayanan and
C. L. Liu and
Sung{-}Mo Kang},
title = {Noise-aware interconnect power optimization in domino logic synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {79--89},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.801630},
doi = {10.1109/TVLSI.2002.801630},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimJNLK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimKK03,
author = {Chulwoo Kim and
Ki{-}Wook Kim and
Sung{-}Mo Kang},
title = {Energy-efficient skewed static logic with dual Vt: design and synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {64--70},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.800528},
doi = {10.1109/TVLSI.2002.800528},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimKK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimKK03a,
author = {Hong{-}Sik Kim and
YongJoon Kim and
Sungho Kang},
title = {Test-decompression mechanism using a variable-length multiple-polynomial
{LFSR}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {687--690},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812287},
doi = {10.1109/TVLSI.2003.812287},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimKK03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimL03,
author = {Kyung{-}Saeng Kim and
Kwyro Lee},
title = {Low-power and area-efficient {FIR} filter implementation suitable
for multiple taps},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {150--153},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.801570},
doi = {10.1109/TVLSI.2002.801570},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimP03,
author = {Joohee Kim and
Marios C. Papaefthymiou},
title = {Block-based multiperiod dynamic memory design for low data-retention
power},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1006--1018},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817524},
doi = {10.1109/TVLSI.2003.817524},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimSR03,
author = {Chris Hyung{-}Il Kim and
Hendrawan Soeleman and
Kaushik Roy},
title = {Ultra-low-power {DLMS} adaptive filter for hearing aid applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1058--1067},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.819573},
doi = {10.1109/TVLSI.2003.819573},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimSR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimZP03,
author = {Suhwan Kim and
Conrad H. Ziesler and
Marios C. Papaefthymiou},
title = {A true single-phase energy-recovery multiplier},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {194--207},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810795},
doi = {10.1109/TVLSI.2003.810795},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimZP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KittitornkunH03,
author = {Surin Kittitornkun and
Yu Hen Hu},
title = {Mapping deep nested do-loop {DSP} algorithms to large scale {FPGA}
array structures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {208--217},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.801622},
doi = {10.1109/TVLSI.2002.801622},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KittitornkunH03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KoKPKY03,
author = {Woo{-}Suk Ko and
Joon{-}Seok Kim and
Young{-}Cheol Park and
Tai{-}Ho Koh and
Dae Hee Youn},
title = {An efficient {DMT} modem for the {G.LITE} {ADSL} transceiver},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {997--1005},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817131},
doi = {10.1109/TVLSI.2003.817131},
timestamp = {Mon, 02 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KoKPKY03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Koranne03,
author = {Sandeep Koranne},
title = {Design of reconfigurable access wrappers for embedded core based SoC
test},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {955--960},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817128},
doi = {10.1109/TVLSI.2003.817128},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Koranne03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KursunF03,
author = {Volkan Kursun and
Eby G. Friedman},
title = {Domino logic with variable threshold voltage keeper},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1080--1093},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817515},
doi = {10.1109/TVLSI.2003.817515},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KursunF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KursunNDF03,
author = {Volkan Kursun and
Siva G. Narendra and
Vivek De and
Eby G. Friedman},
title = {Analysis of buck converters for on-chip integration with a dual supply
voltage microprocessor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {514--522},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812289},
doi = {10.1109/TVLSI.2003.812289},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KursunNDF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Lee03,
author = {Hanho Lee},
title = {High-speed {VLSI} architecture for parallel Reed-Solomon decoder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {288--294},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810782},
doi = {10.1109/TVLSI.2003.810782},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Lee03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeongL03,
author = {Monk{-}Ping Leong and
Philip Heng Wai Leong},
title = {A variable-radix digit-serial design methodology and its application
to the discrete cosine transform},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {90--104},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.811099},
doi = {10.1109/TVLSI.2003.811099},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeongL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiangJ03,
author = {Xuejun Liang and
Jack S. N. Jean},
title = {Mapping of generalized template matching onto reconfigurable computers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {485--498},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812306},
doi = {10.1109/TVLSI.2003.812306},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiangJ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LightbodyWW03,
author = {Gaye Lightbody and
Roger F. Woods and
Richard L. Walke},
title = {Design of a parameterizable silicon intellectual property core for
QR-based {RLS} filtering},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {659--678},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816142},
doi = {10.1109/TVLSI.2003.816142},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LightbodyWW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCL03,
author = {Jai{-}Ming Lin and
Yao{-}Wen Chang and
Shih{-}Ping Lin},
title = {Corner sequence - a P-admissible floorplan representation with a worst
case linear-time packing scheme},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {679--686},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816137},
doi = {10.1109/TVLSI.2003.816137},
timestamp = {Thu, 11 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuP03,
author = {Xun Liu and
Marios C. Papaefthymiou},
title = {Design of a 20-mb/s 256-state Viterbi decoder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {965--975},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817547},
doi = {10.1109/TVLSI.2003.817547},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LvHLW03,
author = {Tiehan Lv and
J{\"{o}}rg Henkel and
Haris Lekatsas and
Wayne H. Wolf},
title = {A dictionary-based en/decoding scheme for low-power data buses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {943--951},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817123},
doi = {10.1109/TVLSI.2003.817123},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LvHLW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LyuhK03,
author = {Chun{-}Gi Lyuh and
Taewhan Kim},
title = {High-level synthesis for low power based on network flow method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {364--375},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810796},
doi = {10.1109/TVLSI.2003.810796},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LyuhK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MamidipakaHD03,
author = {Mahesh Mamidipaka and
Daniel S. Hirschberg and
Nikil D. Dutt},
title = {Adaptive low-power address encoding techniques using self-organizing
lists},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {827--834},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.814325},
doi = {10.1109/TVLSI.2003.814325},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MamidipakaHD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Manoli03,
author = {Yiannos Manoli},
title = {Special section on the 2001 International Conference on Computer Design
{(ICCD)}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {301--302},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.814044},
doi = {10.1109/TVLSI.2003.814044},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Manoli03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MansourS03,
author = {Mohammad M. Mansour and
Naresh R. Shanbhag},
title = {{VLSI} architectures for {SISO-APP} decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {627--650},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816136},
doi = {10.1109/TVLSI.2003.816136},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MansourS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MansourS03a,
author = {Mohammad M. Mansour and
Naresh R. Shanbhag},
title = {High-throughput {LDPC} decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {976--996},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817545},
doi = {10.1109/TVLSI.2003.817545},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MansourS03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ManzakC03,
author = {Ali Manzak and
Chaitali Chakrabarti},
title = {Variable voltage task scheduling algorithms for minimizing energy/power},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {270--276},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810801},
doi = {10.1109/TVLSI.2003.810801},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ManzakC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MasselosMTSG03,
author = {Kostas Masselos and
Panagiotis Merakos and
S. Theoharis and
Thanos Stouraitis and
Constantinos E. Goutis},
title = {Power efficient data path synthesis of sum-of-products computations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {446--450},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812368},
doi = {10.1109/TVLSI.2003.812368},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MasselosMTSG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Maymandi-NejadS03,
author = {Mohammad Maymandi{-}Nejad and
Manoj Sachdev},
title = {A digitally programmable delay element: design and analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {871--878},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810787},
doi = {10.1109/TVLSI.2003.810787},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Maymandi-NejadS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/McGregorL03,
author = {John Patrick McGregor and
Ruby B. Lee},
title = {Architectural techniques for accelerating subword permutations with
repetitions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {325--335},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812318},
doi = {10.1109/TVLSI.2003.812318},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/McGregorL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Meyer-BaseS03,
author = {Uwe Meyer{-}B{\"{a}}se and
Thanos Stouraitis},
title = {New power-of-2 {RNS} scaling scheme for cell-based {IC} design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {280--283},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810799},
doi = {10.1109/TVLSI.2003.810799},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Meyer-BaseS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MilterK03,
author = {O. Milter and
Avinoam Kolodny},
title = {Crosstalk noise reduction in synthesized digital logic circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1153--1158},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817551},
doi = {10.1109/TVLSI.2003.817551},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MilterK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MoonASDB03,
author = {Joong{-}Seok Moon and
William C. Athas and
Sigfrid D. Soli and
Jeffrey T. Draper and
Peter A. Beerel},
title = {Voltage-pulse driven harmonic resonant rail drivers for low-power
applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {762--777},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.814323},
doi = {10.1109/TVLSI.2003.814323},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MoonASDB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MostafaEE03,
author = {M. A. I. Mostafa and
Sherif H. K. Embabi and
Mostafa A. I. Elmala},
title = {A 60-dB 246-MHz {CMOS} variable gain amplifier for subsampling {GSM}
receivers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {835--838},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.814326},
doi = {10.1109/TVLSI.2003.814326},
timestamp = {Thu, 21 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MostafaEE03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MukherjeeM03,
author = {Arindam Mukherjee and
Malgorzata Marek{-}Sadowska},
title = {Wave steering to integrate logic and physical syntheses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {105--120},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.811100},
doi = {10.1109/TVLSI.2003.811100},
timestamp = {Mon, 05 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MukherjeeM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MukhopadhyayNCAKR03,
author = {Saibal Mukhopadhyay and
Cassondra Neau and
R. T. Cakici and
Amit Agarwal and
Chris H. Kim and
Kaushik Roy},
title = {Gate leakage reduction for scaled devices using transistor stacking},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {716--730},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816145},
doi = {10.1109/TVLSI.2003.816145},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MukhopadhyayNCAKR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MurugavelR03,
author = {Ashok K. Murugavel and
N. Ranganathan},
title = {Petri net modeling of gate and interconnect delays for power estimation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {921--927},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817110},
doi = {10.1109/TVLSI.2003.817110},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MurugavelR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MurugavelR03a,
author = {Ashok K. Murugavel and
N. Ranganathan},
title = {A game theoretic approach for power optimization during behavioral
synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1031--1043},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.819566},
doi = {10.1109/TVLSI.2003.819566},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MurugavelR03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NahP03,
author = {Kyung{-}suc Nah and
Byeong{-}Ha Park},
title = {A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic
range and 2-dB gain steps for 3 {V} power supply},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {218--223},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810797},
doi = {10.1109/TVLSI.2003.810797},
timestamp = {Mon, 13 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NahP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Nicolaidis03,
author = {Michael Nicolaidis},
title = {Carry checking/parity prediction adders and ALUs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {121--128},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.800526},
doi = {10.1109/TVLSI.2002.800526},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Nicolaidis03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NunezJ03,
author = {Jos{\'{e}} Luis N{\'{u}}{\~{n}}ez and
Simon Jones},
title = {Gbit/s lossless data compression hardware},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {499--510},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812288},
doi = {10.1109/TVLSI.2003.812288},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NunezJ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PamunuwaZT03,
author = {Dinesh Pamunuwa and
Li{-}Rong Zheng and
Hannu Tenhunen},
title = {Maximizing throughput over parallel wire structures in the deep submicrometer
regime},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {224--243},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810800},
doi = {10.1109/TVLSI.2003.810800},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PamunuwaZT03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkMR03,
author = {Jongsun Park and
Khurram Muhammad and
Kaushik Roy},
title = {High-performance {FIR} filter design based on sharing multiplication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {244--253},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.800529},
doi = {10.1109/TVLSI.2002.800529},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkMR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PengPML03,
author = {Lu Peng and
Jih{-}Kwon Peir and
Qianrong Ma and
Konrad Lai},
title = {Address-free memory access based on program syntax correlation of
loads and stores},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {314--324},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812315},
doi = {10.1109/TVLSI.2003.812315},
timestamp = {Tue, 12 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PengPML03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PerriCC03,
author = {Stefania Perri and
Pasquale Corsonello and
Giuseppe Cocorullo},
title = {A high-speed energy-efficient 64-bit reconfigurable binary adder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {939--943},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817109},
doi = {10.1109/TVLSI.2003.817109},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PerriCC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PonomarevKEGK03,
author = {Dmitry V. Ponomarev and
Gurhan Kucuk and
Oguz Ergin and
Kanad Ghose and
Peter M. Kogge},
title = {Energy-efficient issue queue design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {789--800},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.814321},
doi = {10.1109/TVLSI.2003.814321},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PonomarevKEGK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PouwelseLS03,
author = {Johan A. Pouwelse and
Koen Langendoen and
Henk J. Sips},
title = {Application-directed voltage scaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {812--826},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.814324},
doi = {10.1109/TVLSI.2003.814324},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PouwelseLS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RaghunathanDJ03,
author = {Anand Raghunathan and
Sujit Dey and
Niraj K. Jha},
title = {High-level macro-modeling and estimation techniques for switching
activity and power consumption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {538--557},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812295},
doi = {10.1109/TVLSI.2003.812295},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RaghunathanDJ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RahmanDCR03,
author = {Arifur Rahman and
Shamik Das and
Anantha P. Chandrakasan and
Rafael Reif},
title = {Wiring requirement and three-dimensional integration technology for
field programmable gate arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {44--54},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810003},
doi = {10.1109/TVLSI.2003.810003},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RahmanDCR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RakhmatovVW03,
author = {Daler N. Rakhmatov and
Sarma B. K. Vrudhula and
Deborah A. Wallach},
title = {A model for battery lifetime analysis for organizing applications
on a pocket computer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1019--1030},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.819320},
doi = {10.1109/TVLSI.2003.819320},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RakhmatovVW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SakaiYMY03,
author = {Atsushi Sakai and
Takashi Yamada and
Yoshifumi Matsushita and
Hiroto Yasuura},
title = {Reduction of coupling effects by optimizing the 3-D configuration
of the routing grid},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {951--954},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817126},
doi = {10.1109/TVLSI.2003.817126},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SakaiYMY03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeoKP03,
author = {Jaewon Seo and
Taewhan Kim and
Preeti Ranjan Panda},
title = {Memory allocation and mapping in high-level synthesis - an integrated
approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {928--938},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817116},
doi = {10.1109/TVLSI.2003.817116},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeoKP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinghK03,
author = {Mandeep Singh and
Israel Koren},
title = {Fault-sensitivity analysis and reliability enhancement of analog-to-digital
converters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {839--852},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812376},
doi = {10.1109/TVLSI.2003.812376},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SinghK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinghMMM03,
author = {Amit Singh and
Arindam Mukherjee and
Luca Macchiarulo and
Malgorzata Marek{-}Sadowska},
title = {{PITIA:} an {FPGA} for throughput-intensive applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {354--363},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810780},
doi = {10.1109/TVLSI.2003.810780},
timestamp = {Mon, 05 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SinghMMM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinhaIC03,
author = {Amit Sinha and
Nathan Ickes and
Anantha P. Chandrakasan},
title = {Instruction level and operating system profiling for energy exposed
software},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1044--1057},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.819569},
doi = {10.1109/TVLSI.2003.819569},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SinhaIC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SolomonMROA03,
author = {Baruch Solomon and
Avi Mendelson and
Ronny Ronen and
Doron Orenstein and
Yoav Almog},
title = {Micro-operation cache: a power aware frontend for variable instruction
length {ISA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {801--811},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.814327},
doi = {10.1109/TVLSI.2003.814327},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SolomonMROA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongHMCKC03,
author = {Xiaoyu Song and
William N. N. Hung and
Alan Mishchenko and
Malgorzata Chrzanowska{-}Jeske and
Andrew A. Kennings and
Alan J. Coppola},
title = {Board-level multiterminal net assignment for the partial cross-bar
architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {511--514},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812322},
doi = {10.1109/TVLSI.2003.812322},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SongHMCKC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/StevensGR03,
author = {Ken S. Stevens and
Ran Ginosar and
Shai Rotem},
title = {Relative timing [asynchronous design]},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {129--140},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.801606},
doi = {10.1109/TVLSI.2002.801606},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/StevensGR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Stroobandt03,
author = {Dirk Stroobandt},
title = {A priori wire length distribution models with multiterminal nets},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {35--43},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810002},
doi = {10.1109/TVLSI.2003.810002},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Stroobandt03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThorpLT03,
author = {T. Thorp and
D. Liu and
P. Trivedi},
title = {Analysis of blocking dynamic circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {744--748},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816140},
doi = {10.1109/TVLSI.2003.816140},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ThorpLT03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThorpYS03,
author = {T. J. Thorp and
G. S. Yee and
Carl M. Sechen},
title = {Design and synthesis of dynamic circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {141--149},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.800518},
doi = {10.1109/TVLSI.2002.800518},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ThorpYS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VermeulenCNVM03,
author = {Frederik Vermeulen and
Francky Catthoor and
Lode Nachtergaele and
Diederik Verkest and
Hugo De Man},
title = {Power-efficient flexible processor architecture for embedded applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {376--385},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810779},
doi = {10.1109/TVLSI.2003.810779},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VermeulenCNVM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangC03,
author = {Ting{-}Yuan Wang and
Charlie Chung{-}Ping Chen},
title = {Thermal-ADI - a linear-time chip-level dynamic thermal-simulation
algorithm based on alternating-direction-implicit {(ADI)} method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {691--700},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812372},
doi = {10.1109/TVLSI.2003.812372},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangHC03,
author = {Chua{-}Chin Wang and
Ya{-}Hsin Hsueh and
Ying{-}Pei Chen},
title = {An area-saving decoder structure for ROMs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {581--589},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816134},
doi = {10.1109/TVLSI.2003.816134},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangHC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLWH03,
author = {Chua{-}Chin Wang and
Po{-}Ming Lee and
Jun{-}Jie Wang and
Chenn{-}Jung Huang},
title = {Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing
algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {737--740},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816143},
doi = {10.1109/TVLSI.2003.816143},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLWH03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangS03,
author = {Lei Wang and
Naresh R. Shanbhag},
title = {Energy-efficiency bounds for deep submicron {VLSI} systems in the
presence of noise},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {2},
pages = {254--269},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810783},
doi = {10.1109/TVLSI.2003.810783},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangS03a,
author = {Lei Wang and
Naresh R. Shanbhag},
title = {Low-power {MIMO} signal processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {434--445},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812367},
doi = {10.1109/TVLSI.2003.812367},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangS03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WildmanKWC03,
author = {Raymond A. Wildman and
Joshua I. Kramer and
Daniel S. Weile and
Phillip Christie},
title = {Multi-objective optimization of interconnect geometry},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {1},
pages = {15--23},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2002.808460},
doi = {10.1109/TVLSI.2002.808460},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WildmanKWC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuCCF03,
author = {Yu{-}Liang Wu and
Chak{-}Chung Cheung and
David Ihsin Cheng and
Hongbing Fan},
title = {Further improve circuit partitioning using {GBAW} logic perturbation
techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {451--460},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812369},
doi = {10.1109/TVLSI.2003.812369},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuCCF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuM03,
author = {Qinwei Xu and
Pinaki Mazumder},
title = {Equivalent-circuit interconnect modeling based on the fifth-order
differential quadrature methods},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {6},
pages = {1068--1079},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817522},
doi = {10.1109/TVLSI.2003.817522},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XuM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangK03,
author = {Byung{-}Do Yang and
Lee{-}Sup Kim},
title = {A low-power charge-recycling {ROM} architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {590--600},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816138},
doi = {10.1109/TVLSI.2003.816138},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangS03,
author = {Jin Yang and
Carl{-}Johan H. Seger},
title = {Introduction to generalized symbolic trajectory evaluation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {345--353},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812320},
doi = {10.1109/TVLSI.2003.812320},
timestamp = {Mon, 17 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZachariahC03,
author = {Sujit T. Zachariah and
Sreejit Chakravarty},
title = {Algorithm to extract two-node bridges},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {4},
pages = {741--744},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.816141},
doi = {10.1109/TVLSI.2003.816141},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZachariahC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhengS03,
author = {Yu Zheng and
Kenneth L. Shepard},
title = {On-chip oscilloscopes for noninvasive time-domain measurement of waveforms
in digital integrated circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {336--344},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812313},
doi = {10.1109/TVLSI.2003.812313},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhengS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Zyuban03,
author = {Victor V. Zyuban},
title = {Optimization of scannable latches for low energy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {778--788},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.814322},
doi = {10.1109/TVLSI.2003.814322},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Zyuban03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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