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@article{DBLP:journals/tvlsi/0003Z19,
author = {Xuan Dong and
Lihong Zhang},
title = {EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {854--863},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2883710},
doi = {10.1109/TVLSI.2018.2883710},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/0003Z19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/0011N00YM19,
author = {Bing Li and
Ji{-}Ping Na and
Wei Wang and
Jia Liu and
Qian Yang and
Pui{-}In Mak},
title = {A 13-bit 8-kS/s {\(\Delta\)}-{\(\Sigma\)} Readout {IC} Using {ZCB}
Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion
Step and a 65-dB {PSRR}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {843--853},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2895361},
doi = {10.1109/TVLSI.2019.2895361},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/0011N00YM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AfzalianND19,
author = {Amard Afzalian and
Hossein Miar Naimi and
Massoud Dousti},
title = {What Is the Maximum Achievable Oscillation Frequency in a Specified
{CMOS} Process?},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {587--600},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2880923},
doi = {10.1109/TVLSI.2018.2880923},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AfzalianND19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AhmadiSA19,
author = {Mehrnaz Ahmadi and
Sahand Salamat and
Bijan Alizadeh},
title = {A Dynamic Timing Error Avoidance Technique Using Prediction Logic
in High-Performance Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {734--737},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2881173},
doi = {10.1109/TVLSI.2018.2881173},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AhmadiSA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlamTF19,
author = {Md. Mahbub Alam and
Mark M. Tehranipoor and
Domenic Forte},
title = {Recycled {FPGA} Detection Using Exhaustive {LUT} Path Delay Characterization
and Voltage Scaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2897--2910},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2933278},
doi = {10.1109/TVLSI.2019.2933278},
timestamp = {Tue, 30 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlamTF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AliAC19,
author = {Muhammad Ali and
Mohammad A. Ahmed and
Malgorzata Chrzanowska{-}Jeske},
title = {Logical Effort Framework for CNFET-Based {VLSI} Circuits for Delay
and Area Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {573--586},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2880322},
doi = {10.1109/TVLSI.2018.2880322},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AliAC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Alioto19,
author = {Massimo Alioto},
title = {Editorial: {TVLSI} Keynote Papers Enriching Our Transactions With
Invited Contributions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1485},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2921855},
doi = {10.1109/TVLSI.2019.2921855},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Alioto19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AliotoAABBCCCCC19,
author = {Massimo Alioto and
Magdy S. Abadir and
Tughrul Arslan and
Chirn Chye Boon and
Andreas Burg and
Chip{-}Hong Chang and
Meng{-}Fan Chang and
Yao{-}Wen Chang and
Poki Chen and
Pasquale Corsonello and
Paolo Crovetti and
Shiro Dosho and
Rolf Drechsler and
Ibrahim Abe M. Elfadel and
Ruonan Han and
Masanori Hashimoto and
Chun{-}Huat Heng and
Deukhyoun Heo and
Tsung{-}Yi Ho and
Houman Homayoun and
Yuh{-}Shyan Hwang and
Ajay Joshi and
Rajiv V. Joshi and
Tanay Karnik and
Chulwoo Kim and
Tony Tae{-}Hyoung Kim and
Jaydeep Kulkarni and
Volkan Kursun and
Yoonmyung Lee and
Hai Helen Li and
Huawei Li and
Prabhat Mishra and
Baker Mohammad and
Mehran Mozaffari Kermani and
Makoto Nagata and
Koji Nii and
Partha Pratim Pande and
Bipul C. Paul and
Vasilis F. Pavlidis and
Jos{\'{e}} Pineda de Gyvez and
Ioannis Savidis and
Patrick Schaumont and
Fabio Sebastiano and
Anirban Sengupta and
Mingoo Seok and
Mircea R. Stan and
Mark M. Tehranipoor and
Aida Todri{-}Sanial and
Marian Verhelst and
Valerio Vignoli and
Xiaoqing Wen and
Jiang Xu and
Wei Zhang and
Zhengya Zhang and
Jun Zhou and
Mark Zwolinski and
Stacey Weber},
title = {Editorial {TVLSI} Positioning - Continuing and Accelerating an Upward
Trajectory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {253--280},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2886389},
doi = {10.1109/TVLSI.2018.2886389},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AliotoAABBCCCCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlsaiariG19,
author = {Uthman Alsaiari and
Fayez Gebali},
title = {Hardware Trojan Detection Using Reconfigurable Assertion Checkers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1575--1586},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2908964},
doi = {10.1109/TVLSI.2019.2908964},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlsaiariG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AnkitKSR19,
author = {Aayush Ankit and
Minsuk Koo and
Shreyas Sen and
Kaushik Roy},
title = {Powerline Communication for Enhanced Connectivity in Neuromorphic
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1897--1906},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2907096},
doi = {10.1109/TVLSI.2019.2907096},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AnkitKSR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaekC19,
author = {Donkyu Baek and
Naehyuck Chang},
title = {Runtime Power Management of Battery Electric Vehicles for Extended
Range With Consideration of Driving Time},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {549--559},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2880441},
doi = {10.1109/TVLSI.2018.2880441},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaekC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BalefFGG19,
author = {Hadi Ahmadi Balef and
Hamed Fatemi and
Kees Goossens and
Jos{\'{e}} Pineda de Gyvez},
title = {Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle
Error Prevention},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1206--1217},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2895972},
doi = {10.1109/TVLSI.2019.2895972},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BalefFGG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BambergO19,
author = {Lennart Bamberg and
Alberto Garc{\'{\i}}a Ortiz},
title = {Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for
Heterogeneous 3-D SoCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2317--2330},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2923633},
doi = {10.1109/TVLSI.2019.2923633},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BambergO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BanikRS19,
author = {Shukla Banik and
Suchismita Roy and
Bibhash Sen},
title = {Application-Dependent Testing of {FPGA} Interconnect Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2296--2304},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2925932},
doi = {10.1109/TVLSI.2019.2925932},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BanikRS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BasireddyCN19,
author = {Hareesh{-}Reddy Basireddy and
Karthikeya Challa and
Tooraj Nikoubin},
title = {Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage
Structures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1138--1147},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2889833},
doi = {10.1109/TVLSI.2018.2889833},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BasireddyCN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BathlaRC19,
author = {Shivani Bathla and
Rahul M. Rao and
Nitin Chandrachoodan},
title = {A Simulation-Based Metric to Guide Glitch Power Reduction in Digital
Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {376--386},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2876917},
doi = {10.1109/TVLSI.2018.2876917},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BathlaRC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BazrafshanTN19,
author = {Amir Bazrafshan and
Mohammad Taherzadeh{-}Sani and
Frederic Nabki},
title = {An Analog {LO} Harmonic Suppression Technique for {SDR} Receivers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {182--192},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2871868},
doi = {10.1109/TVLSI.2018.2871868},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BazrafshanTN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhardwajN19,
author = {Kshitij Bhardwaj and
Steven M. Nowick},
title = {A Continuous-Time Replication Strategy for Efficient Multicast in
Asynchronous NoCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {350--363},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2876856},
doi = {10.1109/TVLSI.2018.2876856},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhardwajN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhardwajRA19,
author = {Swati Bhardwaj and
Shashank Raghuraman and
Amit Acharyya},
title = {Simplex FastICA: An Accelerated and Low Complex Architecture Design
Methodology for {\textdollar}n{\textdollar} {D} FastICA},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1124--1137},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2886357},
doi = {10.1109/TVLSI.2018.2886357},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhardwajRA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BinghamM19,
author = {Ned Bingham and
Rajit Manohar},
title = {{QDI} Constant-Time Counters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {83--91},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2867289},
doi = {10.1109/TVLSI.2018.2867289},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BinghamM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BinghamM19a,
author = {Ned Bingham and
Rajit Manohar},
title = {Self-Timed Adaptive Digit-Serial Addition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2131--2141},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2918441},
doi = {10.1109/TVLSI.2019.2918441},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BinghamM19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BondalapatiN19,
author = {Pratheep Bondalapati and
Won Namgoong},
title = {Timing Jitter Distribution and Power Spectral Density of a Second-Order
Bang-Bang Digital {PLL} With Transport Delay Using Fokker-Planck Equations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {398--406},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2878665},
doi = {10.1109/TVLSI.2018.2878665},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BondalapatiN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaeKPK19,
author = {Joo{-}Hyung Chae and
Hyeongjun Ko and
Jihwan Park and
Suhwan Kim},
title = {A Quadrature Clock Corrector for {DRAM} Interfaces, With a Duty-Cycle
and Quadrature Phase Detector Based on a Relaxation Oscillator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {978--982},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2883730},
doi = {10.1109/TVLSI.2018.2883730},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaeKPK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangAHL19,
author = {Yi{-}An Chang and
Trio Adiono and
Amy Hamidah and
Shen{-}Iuan Liu},
title = {An On-Chip Relaxation Oscillator With Comparator Delay Compensation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {969--973},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2882376},
doi = {10.1109/TVLSI.2018.2882376},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangAHL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangDSCYL19,
author = {Kyungwook Chang and
Shidhartha Das and
Saurabh Sinha and
Brian Cline and
Greg Yeric and
Sung Kyu Lim},
title = {System-Level Power Delivery Network Analysis and Optimization for
Monolithic 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {888--898},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2897589},
doi = {10.1109/TVLSI.2019.2897589},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangDSCYL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangL19,
author = {Yi{-}An Chang and
Shen{-}Iuan Liu},
title = {A 13.4-MHz Relaxation Oscillator With Temperature Compensation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1725--1729},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2908204},
doi = {10.1109/TVLSI.2019.2908204},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangMWZDZX19,
author = {Liang Chang and
Xin Ma and
Zhaohao Wang and
Youguang Zhang and
Yufei Ding and
Weisheng Zhao and
Yuan Xie},
title = {{DASM:} Data-Streaming-Based Computing in Nonvolatile Memory Architecture
for Embedded System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2046--2059},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2912941},
doi = {10.1109/TVLSI.2019.2912941},
timestamp = {Tue, 07 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangMWZDZX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangMWZXZ19,
author = {Liang Chang and
Xin Ma and
Zhaohao Wang and
Youguang Zhang and
Yuan Xie and
Weisheng Zhao},
title = {{PXNOR-BNN:} In/With Spin-Orbit Torque {MRAM} Preset-XNOR Operation-Based
Binary Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2668--2679},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2926984},
doi = {10.1109/TVLSI.2019.2926984},
timestamp = {Tue, 07 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangMWZXZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaouraniRHR19,
author = {Panagiotis Chaourani and
Saul Rodriguez and
Per{-}Erik Hellstr{\"{o}}m and
Ana Rusu},
title = {Inductors in a Monolithic 3-D Process: Performance Analysis and Design
Guidelines},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {468--480},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2877132},
doi = {10.1109/TVLSI.2018.2877132},
timestamp = {Wed, 05 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaouraniRHR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChatterjeePMBRS19,
author = {Baibhab Chatterjee and
Priyadarshini Panda and
Shovan Maity and
Ayan Biswas and
Kaushik Roy and
Shreyas Sen},
title = {Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve
Extreme Energy Efficiency Through Mixed-Signal Neurons},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1365--1377},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2896611},
doi = {10.1109/TVLSI.2019.2896611},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChatterjeePMBRS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChattopadhyayGB19,
author = {Anupam Chattopadhyay and
Swaroop Ghosh and
Wayne P. Burleson and
Debdeep Mukhopadhyay},
title = {Guest Editorial Special Section on Security Challenges and Solutions
With Emerging Computing Technologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2469--2472},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2945850},
doi = {10.1109/TVLSI.2019.2945850},
timestamp = {Mon, 06 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChattopadhyayGB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChekuriKSM19,
author = {Venkata Chaitanya Krishna Chekuri and
Monodeep Kar and
Arvind Singh and
Saibal Mukhopadhyay},
title = {Autotuning of Integrated Inductive Voltage Regulator Using On-Chip
Delay Sensor to Tolerate Process and Passive Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1768--1778},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2912141},
doi = {10.1109/TVLSI.2019.2912141},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChekuriKSM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenCCS19,
author = {Shuo{-}Han Chen and
Yuan{-}Hao Chang and
Yu{-}Ming Chang and
Wei{-}Kuan Shih},
title = {mwJFS: {A} Multiwrite-Mode Journaling File System for {MLC} {NVRAM}
Storages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2060--2073},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2919907},
doi = {10.1109/TVLSI.2019.2919907},
timestamp = {Tue, 05 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenCCS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenCLY19,
author = {Chun{-}Chi Chen and
Chao{-}Lieh Chen and
Yi Lin and
Song{-}Quan You},
title = {An All-Digital Time-Domain Smart Temperature Sensor With a Cost-Efficient
Curvature Correction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {29--36},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2867215},
doi = {10.1109/TVLSI.2018.2867215},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenCLY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHBW19,
author = {Ting{-}Sheng Chen and
Kai{-}Ni Hou and
Win{-}Ken Beh and
An{-}Yeu Wu},
title = {Low-Complexity Compressed-Sensing-Based Watermark Cryptosystem and
Circuits Implementation for Wireless Sensor Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2485--2497},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2933722},
doi = {10.1109/TVLSI.2019.2933722},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHBW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHLK19,
author = {Jiann{-}Jong Chen and
Yuh{-}Shyan Hwang and
Jun{-}Yi Lin and
Yitsen Ku},
title = {A Dead-Beat-Controlled Fast-Transient-Response Buck Converter With
Active Pseudo-Current-Sensing Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1751--1759},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2908875},
doi = {10.1109/TVLSI.2019.2908875},
timestamp = {Tue, 12 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHLK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenZG19,
author = {Zhengyu Chen and
Hai Zhou and
Jie Gu},
title = {R-Accelerator: An RRAM-Based {CGRA} Accelerator With Logic Contraction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2655--2667},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2925937},
doi = {10.1109/TVLSI.2019.2925937},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenZG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChithiraV19,
author = {P. R. Chithira and
Vinita Vasudevan},
title = {Potential Critical Path Selection Based on a Time-Varying Statistical
Timing Analysis Framework},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1438--1449},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2893020},
doi = {10.1109/TVLSI.2019.2893020},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChithiraV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChiuL19,
author = {Yu{-}Kai Chiu and
Shen{-}Iuan Liu},
title = {A PVT-Tolerant {MDLL} Using a Frequency Calibrator and a Voltage Monitor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2698--2702},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2925820},
doi = {10.1109/TVLSI.2019.2925820},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChiuL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoiASKKJ19,
author = {Sara Choi and
Hong Keun Ahn and
Byungkyu Song and
Jung Pill Kim and
Seung{-}Hyuk Kang and
Seong{-}Ook Jung},
title = {A Decoder for Short {BCH} Codes With High Decoding Efficiency and
Low Power for Emerging Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {387--397},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2877147},
doi = {10.1109/TVLSI.2018.2877147},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoiASKKJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoiKKL19,
author = {Jiwoong Choi and
Boyeal Kim and
Hyun Kim and
Hyuk{-}Jae Lee},
title = {A High-Throughput Hardware Accelerator for Lossless Compression of
a {DDR4} Command Trace},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {92--102},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2869663},
doi = {10.1109/TVLSI.2018.2869663},
timestamp = {Wed, 22 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoiKKL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChuHH19,
author = {Shao{-}I Chu and
Chen{-}En Hsieh and
Yu{-}Jung Huang},
title = {Design of FSM-Based Function With Reduced Number of States in Integral
Stochastic Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1475--1479},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2892847},
doi = {10.1109/TVLSI.2019.2892847},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChuHH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CiprutF19,
author = {Albert Ciprut and
Eby G. Friedman},
title = {Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout
Regulators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1779--1789},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2914395},
doi = {10.1109/TVLSI.2019.2914395},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CiprutF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Cowan19,
author = {Christopher Cowan},
title = {Drafting in Self-Timed Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {810--820},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2884881},
doi = {10.1109/TVLSI.2018.2884881},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Cowan19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DeMP19,
author = {Partha De and
Chittaranjan Mandal and
Udaya Parampalli},
title = {Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power
and Timing Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1080--1092},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2896377},
doi = {10.1109/TVLSI.2019.2896377},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DeMP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DghaisSA19,
author = {Wael Dghais and
Malek Souilem and
Muhammad Alam},
title = {Mixed-Signal Overclocked {I/O} Buffers Model Abstraction for Signal
Integrity Assessment},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {691--699},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2885407},
doi = {10.1109/TVLSI.2018.2885407},
timestamp = {Fri, 27 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DghaisSA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DoZJSK19,
author = {Anh{-}Tuan Do and
Seyed Mohammad Ali Zeinolabedin and
Dongsuk Jeon and
Dennis Sylvester and
Tony Tae{-}Hyoung Kim},
title = {An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time
Neural Recording With 0.175{\(\mathrm{\mu}\)}W/Channel in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {126--137},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2875934},
doi = {10.1109/TVLSI.2018.2875934},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DoZJSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DodoBNT19,
author = {Samir Ben Dodo and
Rajendra Bishnoi and
Sarath Mohanachandran Nair and
Mehdi Baradaran Tahoori},
title = {A Spintronics Memory {PUF} for Resilience Against Cloning Counterfeit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2511--2522},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2931481},
doi = {10.1109/TVLSI.2019.2931481},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DodoBNT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DouglassK19,
author = {Andrew J. Douglass and
Sunil P. Khatri},
title = {Fast, Ring-Based Design of 3-D Stacked {DRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1731--1741},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2892740},
doi = {10.1109/TVLSI.2019.2892740},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DouglassK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EllaithyEZZ19,
author = {Dina M. Ellaithy and
Magdy A. El{-}Moursy and
Amal Zaki and
Abdelhalim Zekry},
title = {Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation
for Low-Power 3-D Graphics},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {790--798},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2889769},
doi = {10.1109/TVLSI.2018.2889769},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EllaithyEZZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ElnaggarCT19,
author = {Rana Elnaggar and
Krishnendu Chakrabarty and
Mehdi Baradaran Tahoori},
title = {Hardware Trojan Detection Using Changepoint-Based Anomaly Detection
Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2706--2719},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2925807},
doi = {10.1109/TVLSI.2019.2925807},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ElnaggarCT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ElsayedZAHES19,
author = {Omar Elsayed and
Jorge Zarate{-}Roldan and
Amr Abuellil and
Faisal Abdel{-}Latif Hussien and
Ahmed Eladawy and
Edgar S{\'{a}}nchez{-}Sinencio},
title = {Highly Linear Low-Power Wireless {RF} Receiver for {WSN}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1007--1016},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2890093},
doi = {10.1109/TVLSI.2018.2890093},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ElsayedZAHES19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EnomotoIKNA19,
author = {Ryuichi Enomoto and
Tetsuya Iizuka and
Takehisa Koga and
Toru Nakura and
Kunihiro Asada},
title = {A 16-bit 2.0-ps Resolution Two-Step {TDC} in 0.18-{\(\mathrm{\mu}\)}m
{CMOS} Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain
Calibration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {11--19},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2867505},
doi = {10.1109/TVLSI.2018.2867505},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EnomotoIKNA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangTYSY19,
author = {Yun Fang and
Zhong Tang and
Xiao{-}Peng Yu and
Zheng Shi and
Kiat Seng Yeo},
title = {A Reliability-Oriented Startup Analysis of Injection-Locked Frequency
Divider Based on Broken Symmetry Theory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2954--2958},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2932759},
doi = {10.1109/TVLSI.2019.2932759},
timestamp = {Thu, 13 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FangTYSY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangYP19,
author = {Xu Fang and
Yang Yu and
Xiyuan Peng},
title = {{TSV} Prebond Test Method Based on Switched Capacitors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {205--218},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2870482},
doi = {10.1109/TVLSI.2018.2870482},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FangYP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FletcherDM19,
author = {Benjamin J. Fletcher and
Shidhartha Das and
Terrence S. T. Mak},
title = {Design and Optimization of Inductive-Coupling Links for 3-D-ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {711--723},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2881075},
doi = {10.1109/TVLSI.2018.2881075},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FletcherDM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ForeroVRC19,
author = {Freddy Forero and
Hector Villacorta and
Michel Renovell and
V{\'{\i}}ctor H. Champac},
title = {Modeling and Detectability of Full Open Gate Defects in FinFET Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2180--2190},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2918768},
doi = {10.1109/TVLSI.2019.2918768},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ForeroVRC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FrustaciPCA19,
author = {Fabio Frustaci and
Stefania Perri and
Pasquale Corsonello and
Massimo Alioto},
title = {Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {964--968},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2881326},
doi = {10.1109/TVLSI.2018.2881326},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FrustaciPCA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuLW19,
author = {Jingyan Fu and
Zhiheng Liao and
Jinhui Wang},
title = {Memristor-Based Neuromorphic Hardware Improvement for Privacy-Preserving
{ANN}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2745--2754},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2923722},
doi = {10.1109/TVLSI.2019.2923722},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FuLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuLWWH19,
author = {Yupeng Fu and
Lianming Li and
Dongming Wang and
Xuan Wang and
Long He},
title = {28-GHz {CMOS} {VCO} With Capacitive Splitting and Transformer Feedback
Techniques for 5G Communication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2088--2095},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2914481},
doi = {10.1109/TVLSI.2019.2914481},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FuLWWH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GarridoGG19,
author = {Mario Garrido and
Jes{\'{u}}s Grajal and
Oscar Gustafsson},
title = {Optimum Circuits for Bit-Dimension Permutations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1148--1160},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2892322},
doi = {10.1109/TVLSI.2019.2892322},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GarridoGG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GeCZMM19,
author = {Xinyi Ge and
Yong Chen and
Xiaoteng Zhao and
Pui{-}In Mak and
Rui Paulo Martins},
title = {Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery
Circuit With a Second-Order Loop Filter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2223--2236},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2915769},
doi = {10.1109/TVLSI.2019.2915769},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GeCZMM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GeYZZZ19,
author = {Xiang Ge and
Fan Yang and
Hengliang Zhu and
Xuan Zeng and
Dian Zhou},
title = {An Efficient {FPGA} Implementation of Orthogonal Matching Pursuit
With Square-Root-Free {QR} Decomposition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {611--623},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2879884},
doi = {10.1109/TVLSI.2018.2879884},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GeYZZZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GolderDDGSR19,
author = {Anupam Golder and
Debayan Das and
Josef Danial and
Santosh Ghosh and
Shreyas Sen and
Arijit Raychowdhury},
title = {Practical Approaches Toward Deep-Learning-Based Cross-Device Power
Side-Channel Attack},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2720--2733},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2926324},
doi = {10.1109/TVLSI.2019.2926324},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GolderDDGSR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GongQW19,
author = {Yanping Gong and
Fengyu Qian and
Lei Wang},
title = {Design for Test and Hardware Security Utilizing Retention Loss of
Memristors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2536--2547},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2936573},
doi = {10.1109/TVLSI.2019.2936573},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GongQW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuanZS19,
author = {Tianchan Guan and
Xiaoyang Zeng and
Mingoo Seok},
title = {Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory
Capacity in Associative Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {757--768},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2884250},
doi = {10.1109/TVLSI.2018.2884250},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuanZS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GulerJ19,
author = {Abdullah Guler and
Niraj K. Jha},
title = {Three-Dimensional Monolithic FinFET-Based 8T {SRAM} Cell Design for
Enhanced Read Time and Low Leakage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {899--912},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2883525},
doi = {10.1109/TVLSI.2018.2883525},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GulerJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GunduK19,
author = {Anil Kumar Gundu and
Volkan Kursun},
title = {Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input-Output
Repeaters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1537--1547},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2902215},
doi = {10.1109/TVLSI.2019.2902215},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GunduK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuoLZL19,
author = {Jing Guo and
Shanshan Liu and
Lei Zhu and
Fabrizio Lombardi},
title = {A {CMOS} Majority Logic Gate and its Application to One-Step {ML}
Decodable Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2620--2628},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2924721},
doi = {10.1109/TVLSI.2019.2924721},
timestamp = {Wed, 10 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GuoLZL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HameedC19,
author = {Fazal Hameed and
Jer{\'{o}}nimo Castrill{\'{o}}n},
title = {A Novel Hybrid {DRAM/STT-RAM} Last-Level-Cache Architecture for Performance,
Energy, and Endurance Enhancement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2375--2386},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2918385},
doi = {10.1109/TVLSI.2019.2918385},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HameedC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeZWSZZ19,
author = {Yajuan He and
Jiubai Zhang and
Xiaoqing Wu and
Xin Si and
Shaowei Zhen and
Bo Zhang},
title = {A Half-Select Disturb-Free 11T {SRAM} Cell With Built-In Write/Read-Assist
Scheme for Ultralow-Voltage Operations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2344--2353},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2919104},
doi = {10.1109/TVLSI.2019.2919104},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HeZWSZZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HongNZTKPH19,
author = {Wookpyo Hong and
Bai Nguyen and
Zhiyuan Zhou and
Nghia Tang and
Jong{-}Hoon Kim and
Partha Pratim Pande and
Deukhyoun Heo},
title = {A Dual-Output Step-Down Switched-Capacitor Voltage Regulator With
a Flying Capacitor Crossing Technique for Enhanced Power Efficiency},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2861--2871},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2930892},
doi = {10.1109/TVLSI.2019.2930892},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HongNZTKPH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HongWWZ19,
author = {Qinghui Hong and
Qiujie Wu and
Xiaoping Wang and
Zhigang Zeng},
title = {Novel Nonlinear Function Shift Method for Generating Multiscroll Attractors
Using Memristor-Based Control Circuit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1174--1185},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2892786},
doi = {10.1109/TVLSI.2019.2892786},
timestamp = {Sun, 21 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HongWWZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsiehL19,
author = {Cheng{-}En Hsieh and
Shen{-}Iuan Liu},
title = {A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43
ppm/{\textdegree}C Temperature Coefficient},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {501--510},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2880477},
doi = {10.1109/TVLSI.2018.2880477},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsiehL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuhnFWD19,
author = {Sebastian Huhn and
Stefan Frehse and
Robert Wille and
Rolf Drechsler},
title = {Determining Application-Specific Knowledge for Improving Robustness
of Sequential Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {875--887},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2890601},
doi = {10.1109/TVLSI.2018.2890601},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuhnFWD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Hur19,
author = {Jae Young Hur},
title = {Contiguity Representation in Page Table for Memory Management Units},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {147--158},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2870913},
doi = {10.1109/TVLSI.2018.2870913},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Hur19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JafarzadehpourM19,
author = {Fereshteh Jafarzadehpour and
Amir Sabbagh Molahosseini and
Azadeh Alsadat Emrani Zarandi and
Leonel Sousa},
title = {Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2142--2155},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2919609},
doi = {10.1109/TVLSI.2019.2919609},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JafarzadehpourM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Jahanirad19,
author = {Hadi Jahanirad},
title = {{CC-SPRA:} Correlation Coefficients Approach for Signal Probability-Based
Reliability Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {927--939},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2886027},
doi = {10.1109/TVLSI.2018.2886027},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Jahanirad19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JaiswalCAR19,
author = {Akhilesh Jaiswal and
Indranil Chakraborty and
Amogh Agrawal and
Kaushik Roy},
title = {8T {SRAM} Cell as a Multibit Dot-Product Engine for Beyond Von Neumann
Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2556--2567},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2929245},
doi = {10.1109/TVLSI.2019.2929245},
timestamp = {Mon, 19 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JaiswalCAR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Jang19,
author = {Wooyoung Jang},
title = {Unaligned Burst-Aware Memory Subsystem},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2387--2400},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2922621},
doi = {10.1109/TVLSI.2019.2922621},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Jang19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JavvajiT19,
author = {Pavan Kumar Javvaji and
Spyros Tragoudas},
title = {On the Sensitization Probability of a Critical Path Considering Process
Variations and Path Correlations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1196--1205},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2893844},
doi = {10.1109/TVLSI.2019.2893844},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JavvajiT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiangWC19,
author = {Yushan Jiang and
Dong Wang and
Pak Kwong Chan},
title = {A Quiescent 407-nA Output-Capacitorless Low-Dropout Regulator With
0-100-mA Load Current Range},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1093--1104},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2890698},
doi = {10.1109/TVLSI.2018.2890698},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiangWC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoADSKC19,
author = {Kyeongrok Jo and
Seyong Ahn and
Jungho Do and
Taejoong Song and
Taewhan Kim and
Kyu{-}Myung Choi},
title = {Design Rule Evaluation Framework Using Automatic Cell Layout Generator
for Design Technology Co-Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1933--1946},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2910579},
doi = {10.1109/TVLSI.2019.2910579},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JoADSKC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoshiS19,
author = {Archit Joshi and
Mukul Sarkar},
title = {A Low-Pass Filter Bandwidth Adaptation Technique for Phase Interpolators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1790--1798},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2908757},
doi = {10.1109/TVLSI.2019.2908757},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JoshiS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KalaJMS19,
author = {S. Kala and
Babita R. Jose and
Jimson Mathew and
Nalesh Sivanandan},
title = {High-Performance {CNN} Accelerator on {FPGA} Using Unified Winograd-GEMM
Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2816--2828},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2941250},
doi = {10.1109/TVLSI.2019.2941250},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KalaJMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KangP19,
author = {Gyuseong Kang and
Jongsun Park},
title = {Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power
{SOT-MRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1343--1352},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2901291},
doi = {10.1109/TVLSI.2019.2901291},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KangP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KaurMS19,
author = {Amandeep Kaur and
Deepak Mishra and
Mukul Sarkar},
title = {A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic {ADC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {248--252},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2871341},
doi = {10.1109/TVLSI.2018.2871341},
timestamp = {Fri, 26 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KaurMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhaleghiOAHA19,
author = {Behnam Khaleghi and
Behzad Omidi and
Hussam Amrouch and
J{\"{o}}rg Henkel and
Hossein Asadi},
title = {Estimating and Mitigating Aging Effects in Routing Network of FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {651--664},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2886326},
doi = {10.1109/TVLSI.2018.2886326},
timestamp = {Fri, 14 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KhaleghiOAHA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhatavkarA19,
author = {Prathamesh Khatavkar and
Sankaran Aniruddhan},
title = {432 nW per Channel 130 nV/rtHz {ECG} Acquisition Front End With Multifrequency
Chopping},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2021--2032},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2910202},
doi = {10.1109/TVLSI.2019.2910202},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhatavkarA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhezeliMJ19,
author = {Maryam Rezaei Khezeli and
Mohammad Hossein Moaiyeri and
Ali Jalali},
title = {Comparative Analysis of Simultaneous Switching Noise Effects in {MWCNT}
Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {37--46},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2869761},
doi = {10.1109/TVLSI.2018.2869761},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhezeliMJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimCS19,
author = {Seongjong Kim and
Joao Pedro Cerqueira and
Mingoo Seok},
title = {A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based
In Situ Error Detection and Correction Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1886--1896},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2910792},
doi = {10.1109/TVLSI.2019.2910792},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimCS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimHM19,
author = {Dae{-}Hyun Kim and
Shu{-}Han Hsu and
Linda Milor},
title = {Optimization of Experimental Designs for System- Level Accelerated
Life Test in a Memory System Degraded by Time-Dependent Dielectric
Breakdown},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1640--1651},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2909086},
doi = {10.1109/TVLSI.2019.2909086},
timestamp = {Tue, 29 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimHM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimJLC19,
author = {Myeongjin Kim and
Wontaeck Jung and
Hyukjun Lee and
Eui{-}Young Chung},
title = {A Novel {NAND} Flash Memory Architecture for Maximally Exploiting
Plane-Level Parallelism},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1957--1961},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2905626},
doi = {10.1109/TVLSI.2019.2905626},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimJLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimJLLCK19,
author = {Jusung Kim and
Han{-}Shin Jo and
Kyoung{-}Jae Lee and
Dong{-}Ho Lee and
Dae{-}Hyun Choi and
Sangkil Kim},
title = {A Low-Complexity {I/Q} Imbalance Calibration Method for Quadrature
Modulator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {974--977},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2883758},
doi = {10.1109/TVLSI.2018.2883758},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimJLLCK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimKK19,
author = {Kwangmin Kim and
Seokjoon Kang and
Byungsub Kim},
title = {A Code Inversion Encoding Technique to Improve Read Margin of {A}
Cross-Point Phase Change Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1811--1818},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2909535},
doi = {10.1109/TVLSI.2019.2909535},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimLK19,
author = {Jihye Kim and
Sangjun Lee and
Sungho Kang},
title = {Test-Friendly Data-Selectable Self-Gating {(DSSG)}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1972--1976},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2916637},
doi = {10.1109/TVLSI.2019.2916637},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimLK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimSJ19,
author = {Suk Min Kim and
Byungkyu Song and
Seong{-}Ook Jung},
title = {Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage
for Low-Voltage and High-Density {DRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2413--2422},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2920630},
doi = {10.1109/TVLSI.2019.2920630},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimSJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KoYKLMCKJ19,
author = {Junyoung Ko and
Younghwi Yang and
Jisu Kim and
Cheon An Lee and
Young{-}Sun Min and
Jin{-}Young Chun and
Moosung Kim and
Seong{-}Ook Jung},
title = {Variation-Tolerant {WL} Driving Scheme for High-Capacity {NAND} Flash
Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1828--1839},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2912081},
doi = {10.1109/TVLSI.2019.2912081},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KoYKLMCKJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KokilaRN19,
author = {Kokila Jagadeesh and
N. Ramasubramanian and
Nagi Naganathan},
title = {Resource Efficient Metering Scheme for Protecting SoC {FPGA} Device
and IPs in IoT Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2284--2295},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2926788},
doi = {10.1109/TVLSI.2019.2926788},
timestamp = {Wed, 19 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KokilaRN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KoteshwaraDP19,
author = {Sandhya Koteshwara and
Amitabh Das and
Keshab K. Parhi},
title = {Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant
Authenticated Encryption Algorithms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1053--1066},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2894656},
doi = {10.1109/TVLSI.2019.2894656},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KoteshwaraDP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KraakTAHWCC19,
author = {Daniel Kraak and
Mottaqiallah Taouil and
Innocent Agbo and
Said Hamdioui and
Pieter Weckx and
Stefan Cosemans and
Francky Catthoor},
title = {Parametric and Functional Degradation Analysis of Complete 14-nm FinFET
{SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1308--1321},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2902881},
doi = {10.1109/TVLSI.2019.2902881},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KraakTAHWCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KulejKF19,
author = {Tomasz Kulej and
Fabian Khateb and
Luis Henrique de Carvalho Ferreira},
title = {A 0.3-V 37-nW 53-dB {SNDR} Asynchronous Delta-Sigma Modulator in 0.18-{\(\mathrm{\mu}\)}m
{CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {316--325},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2878625},
doi = {10.1109/TVLSI.2018.2878625},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KulejKF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KultalaVBJMKRZT19,
author = {Heikki Kultala and
Timo Viitanen and
Heikki Berg and
Pekka J{\"{a}}{\"{a}}skel{\"{a}}inen and
Joonas Multanen and
Mikko Kokkonen and
Kalle Raiskila and
Tommi Zetterman and
Jarmo Takala},
title = {LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio
Coprocessor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1029--1042},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2897508},
doi = {10.1109/TVLSI.2019.2897508},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KultalaVBJMKRZT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarBSSJB19,
author = {Chaudhry Indra Kumar and
Ishant Bhatia and
Arvind Kumar Sharma and
Deep Sehgal and
H. S. Jatana and
Anand Bulusu},
title = {A Physics-Based Variability-Aware Methodology to Estimate Critical
Charge for Near-Threshold Voltage Latches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2170--2179},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2910825},
doi = {10.1109/TVLSI.2019.2910825},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarBSSJB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarKB19,
author = {Rahul Kumar and
Brajesh Kumar Kaushik and
R. Balasubramanian},
title = {Multispectral Transmission Map Fusion Method and Architecture for
Image Dehazing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2693--2697},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2932033},
doi = {10.1109/TVLSI.2019.2932033},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarKB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KwonB19,
author = {Soon{-}Won Kwon and
Hyeon{-}Min Bae},
title = {A Fully Digital Semirotational Frequency Detection Algorithm for Bang-Bang
CDRs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2944--2948},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2940438},
doi = {10.1109/TVLSI.2019.2940438},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KwonB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Laflamme-MayerK19,
author = {Nicolas Laflamme{-}Mayer and
Gilbert Kowarzyk and
Yves Blaqui{\`{e}}re and
Yvon Savaria and
Mohamad Sawan},
title = {A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {304--315},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2876458},
doi = {10.1109/TVLSI.2018.2876458},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Laflamme-MayerK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LaiPL19,
author = {Bo{-}Cheng Lai and
Jyun{-}Wei Pan and
Chien{-}Yu Lin},
title = {Enhancing Utilization of SIMD-Like Accelerator for Sparse Convolutional
Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1218--1222},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2897052},
doi = {10.1109/TVLSI.2019.2897052},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LaiPL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeHLK19,
author = {Hayoung Lee and
Donghyun Han and
Seungtaek Lee and
Sungho Kang},
title = {Dynamic Built-In Redundancy Analysis for Memory Repair},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2365--2374},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2920999},
doi = {10.1109/TVLSI.2019.2920999},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeHLK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeKHK19,
author = {Wonyoung Lee and
Mincheol Kang and
Seokin Hong and
Soontae Kim},
title = {Interpage-Based Endurance-Enhancing Lower State Encoding for {MLC}
and {TLC} Flash Memory Storages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2033--2045},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2912228},
doi = {10.1109/TVLSI.2019.2912228},
timestamp = {Fri, 14 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeKHK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeL19,
author = {Tai{-}Cheng Lee and
Yih{-}Lang Li},
title = {Incremental Timing-Driven Placement With Approximated Signoff Wire
Delay and Regression-Based Cell Delay},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2434--2446},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2915254},
doi = {10.1109/TVLSI.2019.2915254},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLKK19,
author = {Daewoong Lee and
Dongil Lee and
Yong{-}Hun Kim and
Lee{-}Sup Kim},
title = {A 0.9-V 12-Gb/s Two-FIR Tap Direct {DFE} With Feedback-Signal Common-Mode
Control},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {724--728},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2882606},
doi = {10.1109/TVLSI.2018.2882606},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLL19,
author = {Shuenn{-}Yuh Lee and
Zhan{-}Xian Liao and
Chih{-}Hung Lee},
title = {Energy-Harvesting Circuits With a High-Efficiency Rectifier and a
Low Temperature Coefficient Bandgap Voltage Reference},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1760--1767},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2908670},
doi = {10.1109/TVLSI.2019.2908670},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeWW19,
author = {Ding{-}Yuan Lee and
Ching{-}Che Wang and
An{-}Yeu Wu},
title = {Bundle-Updatable SRAM-Based {TCAM} Design for OpenFlow-Compliant Packet
Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1450--1454},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2891507},
doi = {10.1109/TVLSI.2019.2891507},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeWW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LenkaB19,
author = {Manas Kumar Lenka and
Gaurab Banerjee},
title = {A Wideband Blocker-Tolerant Receiver With Frequency-Translational
Resistive Feedback},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {993--1006},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2895624},
doi = {10.1109/TVLSI.2019.2895624},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LenkaB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LenkaB19a,
author = {Manas Kumar Lenka and
Gaurab Banerjee},
title = {Corrections Corrections to "A Wideband Blocker-Tolerant Receiver With
Frequency-Translational Resistive Feedback"},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1238},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2902297},
doi = {10.1109/TVLSI.2019.2902297},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LenkaB19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LernerT19,
author = {Scott Lerner and
Baris Taskin},
title = {Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree
Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {1--10},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2874572},
doi = {10.1109/TVLSI.2018.2874572},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LernerT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LernerYT19,
author = {Scott Lerner and
Isikcan Yilmaz and
Baris Taskin},
title = {Custard: {ASIC} Workload-Aware Reliable Design for Multicore IoT Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {700--710},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2878664},
doi = {10.1109/TVLSI.2018.2878664},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LernerYT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiLY19,
author = {Tianwen Li and
Hongjin Liu and
Haigang Yang},
title = {Design and Characterization of {SEU} Hardened Circuits for SRAM-Based
{FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1276--1283},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2892838},
doi = {10.1109/TVLSI.2019.2892838},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiLY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LianLSDZJ19,
author = {Xiaocong Lian and
Zhenyu Liu and
Zhourui Song and
Jiwu Dai and
Wei Zhou and
Xiangyang Ji},
title = {High-Performance FPGA-Based {CNN} Accelerator With Block-Floating-Point
Arithmetic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1874--1885},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2913958},
doi = {10.1109/TVLSI.2019.2913958},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LianLSDZJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiangBLTNKWZY19,
author = {Yuan Liang and
Chirn Chye Boon and
Chenyang Li and
Xiao{-}Lan Tang and
Herman Jalli Ng and
Dietmar Kissinger and
Yong Wang and
Qingfeng Zhang and
Hao Yu},
title = {Design and Analysis of {\textdollar}D{\textdollar} -Band On-Chip Modulator
and Signal Source Based on Split-Ring Resonator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1513--1526},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2906680},
doi = {10.1109/TVLSI.2019.2906680},
timestamp = {Sun, 13 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiangBLTNKWZY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiangZLGDN19,
author = {Yuhua Liang and
Zhangming Zhu and
Xueqing Li and
Sumeet Kumar Gupta and
Suman Datta and
Vijaykrishnan Narayanan},
title = {Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2855--2860},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2932268},
doi = {10.1109/TVLSI.2019.2932268},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiangZLGDN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LimH19,
author = {ByongChan Lim and
Mark Horowitz},
title = {An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal
Design Verification},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {193--204},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2873387},
doi = {10.1109/TVLSI.2018.2873387},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LimH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCKL19,
author = {Ing{-}Chao Lin and
Da{-}Wei Chang and
Chen{-}Tai Kao and
Sheng{-}Xuan Lin},
title = {Infection-Based Dead Page Prediction in Hybrid Memory Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2401--2412},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2922660},
doi = {10.1109/TVLSI.2019.2922660},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCKL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinDLYCP19,
author = {Jai{-}Ming Lin and
You{-}Lun Deng and
Szu{-}Ting Li and
Bo{-}Heng Yu and
Li{-}Yen Chang and
Te{-}Wei Peng},
title = {Regularity-Aware Routability-Driven Macro Placement Methodology for
Mixed-Size Circuits With Obstacles},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {57--68},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2867833},
doi = {10.1109/TVLSI.2018.2867833},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinDLYCP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuCSUM19,
author = {Jianwei Liu and
Chi{-}Hang Chan and
Sai{-}Weng Sin and
Seng{-}Pan U and
Rui Paulo Martins},
title = {Accuracy-Enhanced Variance-Based Time-Skew Calibration Using {SAR}
as Window Detector},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {481--485},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2874772},
doi = {10.1109/TVLSI.2018.2874772},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuCSUM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuFKRO19,
author = {Weiqiang Liu and
Sailong Fan and
Ayesha Khalid and
Ciara Rafferty and
M{\'{a}}ire O'Neill},
title = {Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based
Cryptography on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2459--2463},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2922999},
doi = {10.1109/TVLSI.2019.2922999},
timestamp = {Wed, 22 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuFKRO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuL19,
author = {Shaohan Liu and
Dake Liu},
title = {A High-Flexible Low-Latency Memory-Based {FFT} Processor for 4G, WLAN,
and Future 5G},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {511--523},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2879675},
doi = {10.1109/TVLSI.2018.2879675},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuLLH19,
author = {Yidong Liu and
Leibo Liu and
Fabrizio Lombardi and
Jie Han},
title = {An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using
Stochastic Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2213--2221},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2920152},
doi = {10.1109/TVLSI.2019.2920152},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuLLH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuSSTSH19,
author = {Weicheng Liu and
Can Sitik and
Emre Salman and
Baris Taskin and
Savithri Sundareswaran and
Benjamin Huang},
title = {{SLECTS:} Slew-Driven Clock Tree Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {864--874},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2888958},
doi = {10.1109/TVLSI.2018.2888958},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuSSTSH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuAHGEAMH19,
author = {Ruikuan Lu and
A. K. M. Arifuzzman and
Md. Kamal Hossain and
Steven D. Gardner and
Sazia A. Eliza and
J. Iwan D. Alexander and
Yehia Massoud and
Mohammad Rafiqul Haider},
title = {A Low-Power Sensitive Integrated Sensor System for Thermal Flow Monitoring},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2949--2953},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2935790},
doi = {10.1109/TVLSI.2019.2935790},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuAHGEAMH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuWQZL19,
author = {Zhaojun Lu and
Qian Wang and
Gang Qu and
Haichun Zhang and
Zhenglin Liu},
title = {A Blockchain-Based Privacy-Preserving Authentication Scheme for VANETs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2792--2801},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2929420},
doi = {10.1109/TVLSI.2019.2929420},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuWQZL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuYL19,
author = {Chih{-}Wen Lu and
Ping{-}Yeh Yin and
Mu{-}Yong Lin},
title = {A 10-bit Two-Stage {R-DAC} With Isolating Source Followers for {TFT-LCD}
and {AMOLED} Column-Driver ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {326--336},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2876638},
doi = {10.1109/TVLSI.2018.2876638},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuYL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuoWHWCP19,
author = {Yuanyong Luo and
Yuxuan Wang and
Yajun Ha and
Zhongfeng Wang and
Siyuan Chen and
Hongbing Pan},
title = {Generalized Hyperbolic {CORDIC} and Its Logarithmic and Exponential
Computation With Arbitrary Fixed Base},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2156--2169},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2919557},
doi = {10.1109/TVLSI.2019.2919557},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuoWHWCP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuoWHWCP19a,
author = {Yuanyong Luo and
Yuxuan Wang and
Yajun Ha and
Zhongfeng Wang and
Siyuan Chen and
Hongbing Pan},
title = {Corrections to "Generalized Hyperbolic {CORDIC} and Its Logarithmic
and Exponential Computation With Arbitrary Fixed Base"},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2222},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2932174},
doi = {10.1109/TVLSI.2019.2932174},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuoWHWCP19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MahmoudAMSI19,
author = {Abdulqader Nael Mahmoud and
Mohammad Alhawari and
Baker Mohammad and
Hani H. Saleh and
Mohammed Ismail},
title = {A Gain-Controlled, Low-Leakage Dickson Charge Pump for Energy-Harvesting
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1114--1123},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2897046},
doi = {10.1109/TVLSI.2019.2897046},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MahmoudAMSI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MahnashiP19,
author = {Yaqub Mahnashi and
Fang Z. Peng},
title = {A Monolithic Voltage-Scalable Fibonacci Switched-Capacitor {DC-DC}
Converter With Intrinsic Parasitic Charge Recycling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1105--1113},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2893943},
doi = {10.1109/TVLSI.2019.2893943},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MahnashiP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MajumderHUR19,
author = {Md. Badruddoja Majumder and
Md Sakib Hasan and
Mesbah Uddin and
Garrett S. Rose},
title = {A Secure Integrity Checking System for Nanoelectronic Resistive {RAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {416--429},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2876693},
doi = {10.1109/TVLSI.2018.2876693},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MajumderHUR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MandalBPDPO19,
author = {Sumit K. Mandal and
Ganapati Bhat and
Chetan Arvind Patil and
Janardhan Rao Doppa and
Partha Pratim Pande and
{\"{U}}mit Y. Ogras},
title = {Dynamic Resource Management of Heterogeneous Mobile Platforms via
Imitation Learning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2842--2854},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2926106},
doi = {10.1109/TVLSI.2019.2926106},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MandalBPDPO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MannZPGARPVHC19,
author = {Randy W. Mann and
Meixiong Zhao and
Sanjay Parihar and
Qun Gao and
Ankur Arya and
Carl Radens and
Shesh Mani Pandey and
Joseph Versaggi and
Jack M. Higman and
Rick Carter},
title = {An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET
{SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1819--1827},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2907594},
doi = {10.1109/TVLSI.2019.2907594},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MannZPGARPVHC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MarranghelloCRR19,
author = {Felipe S. Marranghello and
Vinicius Callegaro and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Four-Level Forms for Memristive Material Implication Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1228--1232},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2890843},
doi = {10.1109/TVLSI.2019.2890843},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MarranghelloCRR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MartinsLHYMM19,
author = {Ricardo Martins and
Nuno Louren{\c{c}}o and
Nuno Horta and
Jun Yin and
Pui{-}In Mak and
Rui Paulo Martins},
title = {Many-Objective Sizing Optimization of a Class-C/D {VCO} for Ultralow-Power
IoT and Ultralow-Phase-Noise Cellular Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {69--82},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2872410},
doi = {10.1109/TVLSI.2018.2872410},
timestamp = {Tue, 20 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MartinsLHYMM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MatsuiT19,
author = {Chihiro Matsui and
Ken Takeuchi},
title = {Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource
Disaggregated Hybrid Storage With {SCM} and {NAND} Flash Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1799--1810},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2905852},
doi = {10.1109/TVLSI.2019.2905852},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MatsuiT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MelchertBLK19,
author = {Jackson Melchert and
Setareh Behroozi and
Jingjie Li and
Younghyun Kim},
title = {{SAADI-EC:} {A} Quality-Configurable Approximate Divider for Energy
Efficiency},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2680--2692},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2926083},
doi = {10.1109/TVLSI.2019.2926083},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MelchertBLK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MengZLH19,
author = {Xu Meng and
Lianhong Zhou and
Fujiang Lin and
Chun{-}Huat Heng},
title = {A Low-Noise Digital-to-Frequency Converter Based on Injection-Locked
Ring Oscillator and Rotated Phase Selection for Fractional- {\textdollar}N{\textdollar}
Frequency Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1378--1389},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2898258},
doi = {10.1109/TVLSI.2019.2898258},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MengZLH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MinKKK19,
author = {Jisu Min and
Cheol Kim and
Sung{-}Yong Kim and
Kee{-}Won Kwon},
title = {A Study of Read Margin Enhancement for 3T2R Nonvolatile {TCAM} Using
Adaptive Bias Training},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1840--1850},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2915358},
doi = {10.1109/TVLSI.2019.2915358},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MinKKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MishraMB19,
author = {Prabhat Mishra and
Debdeep Mukhopadhyay and
Swarup Bhunia},
title = {Guest Editorial: Special Section on Autonomous Intelligence for Security
and Privacy Analytics},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2703--2705},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2951850},
doi = {10.1109/TVLSI.2019.2951850},
timestamp = {Mon, 18 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MishraMB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Mohamed19,
author = {Mohamed Kouki},
title = {Model Order Reduction Method for Large-Scale {RC} Interconnect and
Implementation of Adaptive Digital {PI} Controller},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2447--2458},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2922219},
doi = {10.1109/TVLSI.2019.2922219},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Mohamed19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MoonSJ19,
author = {Suhong Moon and
Kwanghyun Shin and
Dongsuk Jeon},
title = {Enhancing Reliability of Analog Neural Network Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1455--1459},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2893256},
doi = {10.1109/TVLSI.2019.2893256},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MoonSJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MorrisonDYR19,
author = {Daniel Morrison and
Dennis Delic and
Mehmet Rasit Yuce and
Jean{-}Michel Redoute},
title = {Multistage Linear Feedback Shift Register Counters With Reduced Decoding
Logic in 130-nm {CMOS} for Large-Scale Array Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {103--115},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2872021},
doi = {10.1109/TVLSI.2018.2872021},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MorrisonDYR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MossBL19,
author = {Duncan J. M. Moss and
David Boland and
Philip H. W. Leong},
title = {A Two-Speed, Radix-4, Serial-Parallel Multiplier},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {769--777},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2883645},
doi = {10.1109/TVLSI.2018.2883645},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MossBL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MoudallalN19,
author = {Zahi Moudallal and
Farid N. Najm},
title = {Power Scheduling With Active {RC} Power Grids},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {444--457},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2877107},
doi = {10.1109/TVLSI.2018.2877107},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MoudallalN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MrazekSDSS19,
author = {Vojtech Mrazek and
Luk{\'{a}}s Sekanina and
Roland Dobai and
Marek S{\'{y}}s and
Petr Svenda},
title = {Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2734--2744},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2923848},
doi = {10.1109/TVLSI.2019.2923848},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MrazekSDSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MulaGD19,
author = {Subrahmanyam Mula and
Vinay Chakravarthi Gogineni and
Anindya Sundar Dhar},
title = {Robust Proportionate Adaptive Filter Architectures Under Impulsive
Noise},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1223--1227},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2892383},
doi = {10.1109/TVLSI.2019.2892383},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MulaGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MullerPBP19,
author = {Olivier Muller and
Adrien Prost{-}Boucle and
Alban Bourge and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot},
title = {Efficient Decompression of Binary Encoded Balanced Ternary Sequences},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1962--1966},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2906678},
doi = {10.1109/TVLSI.2019.2906678},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MullerPBP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MuzaffarE19,
author = {Shahzad Muzaffar and
Ibrahim M. Elfadel},
title = {A Domain-Specific Processor Microarchitecture for Energy-Efficient,
Dynamic IoT Communication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2074--2087},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2911393},
doi = {10.1109/TVLSI.2019.2911393},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MuzaffarE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NaSCKKJ19,
author = {Taehui Na and
Byungkyu Song and
Sara Choi and
Jung Pill Kim and
Seung{-}Hyuk Kang and
Seong{-}Ook Jung},
title = {Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge
Architecture for Resistive Nonvolatile Memory in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2548--2555},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2925931},
doi = {10.1109/TVLSI.2019.2925931},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NaSCKKJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NairBT19,
author = {Sarath Mohanachandran Nair and
Rajendra Bishnoi and
Mehdi Baradaran Tahoori},
title = {A Comprehensive Framework for Parametric Failure Modeling and Yield
Analysis of {STT-MRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1697--1710},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2904197},
doi = {10.1109/TVLSI.2019.2904197},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NairBT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NajafiJLR19,
author = {M. Hassan Najafi and
Devon Jenson and
David J. Lilja and
Marc D. Riedel},
title = {Performing Stochastic Computation Deterministically},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2925--2938},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2929354},
doi = {10.1109/TVLSI.2019.2929354},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NajafiJLR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NguyenCPZ19,
author = {Luong N. Nguyen and
Chia{-}Lin Cheng and
Milos Prvulovic and
Alenka G. Zajic},
title = {Creating a Backscattering Side Channel to Enable Detection of Dormant
Hardware Trojans},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1561--1574},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2906547},
doi = {10.1109/TVLSI.2019.2906547},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NguyenCPZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NguyenNKL19,
author = {Duy Thanh Nguyen and
Tuan Nghia Nguyen and
Hyun Kim and
Hyuk{-}Jae Lee},
title = {A High-Throughput and Power-Efficient {FPGA} Implementation of {YOLO}
{CNN} for Object Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1861--1873},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2905242},
doi = {10.1109/TVLSI.2019.2905242},
timestamp = {Wed, 22 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NguyenNKL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NoorJP19,
author = {Safwat Mostafa Noor and
Eugene John and
Manoj Panday},
title = {Design and Implementation of an Ultralow-Energy {FFT} {ASIC} for Processing
{ECG} in Cardiac Pacemakers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {983--987},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2883642},
doi = {10.1109/TVLSI.2018.2883642},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NoorJP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NorollahDBF19,
author = {Amin Norollah and
Danesh Derafshi and
Hakem Beitollahi and
Mahdi Fazeli},
title = {{RTHS:} {A} Low-Cost High-Performance Real-Time Hardware Sorter, Using
a Multidimensional Sorting Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1601--1613},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2912554},
doi = {10.1109/TVLSI.2019.2912554},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NorollahDBF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OmanaFMM19,
author = {Martin Oma{\~{n}}a and
Alessandro Fiore and
Marco Mongitore and
Cecilia Metra},
title = {Fault-Tolerant Inverters for Reliable Photovoltaic Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {20--28},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2874709},
doi = {10.1109/TVLSI.2018.2874709},
timestamp = {Sun, 20 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OmanaFMM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OshitaDK19,
author = {Takao Oshita and
Jonathan Douglas and
Arun Krishnamoorthy},
title = {High-Volume Testing and {DC} Offset Trimming Technique of On-Die Bandgap
Voltage Reference for SOCs and Microprocessors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {821--829},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2882567},
doi = {10.1109/TVLSI.2018.2882567},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OshitaDK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PanLSMX19,
author = {Jeng{-}Shyang Pan and
Chiou{-}Yng Lee and
Anissa Sghaier and
Zeghid Medien and
Jiafeng Xie},
title = {Novel Systolization of Subquadratic Space Complexity Multipliers Based
on Toeplitz Matrix-Vector Product Approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1614--1622},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2903289},
doi = {10.1109/TVLSI.2019.2903289},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PanLSMX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkR19,
author = {Shinwoong Park and
Sanjay Raman},
title = {Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal
Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {679--690},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2888593},
doi = {10.1109/TVLSI.2018.2888593},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PaulRLC19,
author = {Anindita Paul and
Jaime Ram{\'{\i}}rez{-}Angulo and
Antonio J. L{\'{o}}pez{-}Mart{\'{\i}}n and
Ram{\'{o}}n Gonz{\'{a}}lez Carvajal},
title = {{CMOS} First-Order All-Pass Filter With 2-Hz Pole Frequency},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {294--303},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2878017},
doi = {10.1109/TVLSI.2018.2878017},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PaulRLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PaulRLCR19,
author = {Anindita Paul and
Jaime Ram{\'{\i}}rez{-}Angulo and
Antonio J. L{\'{o}}pez{-}Mart{\'{\i}}n and
Ram{\'{o}}n Gonz{\'{a}}lez Carvajal and
Jos{\'{e}} Miguel Rocha{-}P{\'{e}}rez},
title = {Pseudo-Three-Stage Miller Op-Amp With Enhanced Small-Signal and Large-Signal
Performance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2246--2259},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2918235},
doi = {10.1109/TVLSI.2019.2918235},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PaulRLCR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PaulRT19,
author = {Anindita Paul and
Jaime Ram{\'{\i}}rez{-}Angulo and
Antonio Torralba},
title = {Analysis, Comparison, and Experimental Validation of a Class {AB}
Voltage Follower With Enhanced Bandwidth and Slew Rate},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1353--1364},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2903116},
doi = {10.1109/TVLSI.2019.2903116},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PaulRT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PaulinoFC19,
author = {Nuno Miguel Cardanha Paulino and
Jo{\~{a}}o Canas Ferreira and
Jo{\~{a}}o M. P. Cardoso},
title = {Dynamic Partial Reconfiguration of Customized Single-Row Accelerators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {116--125},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2874079},
doi = {10.1109/TVLSI.2018.2874079},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PaulinoFC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PengGBLZT19,
author = {Xizhu Peng and
Jinfeng Guo and
Qingqing Bao and
Zeyu Li and
Haoyu Zhuang and
He Tang},
title = {A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined
ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2568--2574},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2923704},
doi = {10.1109/TVLSI.2019.2923704},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PengGBLZT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PengHLZXWLCZ19,
author = {Chunyu Peng and
Jiati Huang and
Changyong Liu and
Qiang Zhao and
Songsong Xiao and
Xiulong Wu and
Zhiting Lin and
Junning Chen and
Xuan Zeng},
title = {Radiation-Hardened 14T {SRAM} Bitcell With Speed and Power Optimized
for Space Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {407--415},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2879341},
doi = {10.1109/TVLSI.2018.2879341},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PengHLZXWLCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PerachK19,
author = {Ben Perach and
Shahar Kvatinsky},
title = {An Asynchronous and Low-Power True Random Number Generator Using {STT-MTJ}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2473--2484},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2927816},
doi = {10.1109/TVLSI.2019.2927816},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PerachK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PhamTL19,
author = {Thinh Hung Pham and
Phong Tran and
Siew{-}Kei Lam},
title = {High-Throughput and Area-Optimized Architecture for rBRIEF Feature
Extraction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {747--756},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2881105},
doi = {10.1109/TVLSI.2018.2881105},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PhamTL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PicekHJB19,
author = {Stjepan Picek and
Annelie Heuser and
Alan Jovic and
Lejla Batina},
title = {A Systematic Evaluation of Profiling Through Focused Feature Selection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2802--2815},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2937365},
doi = {10.1109/TVLSI.2019.2937365},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PicekHJB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PilatoBRK19,
author = {Christian Pilato and
Kanad Basu and
Francesco Regazzoni and
Ramesh Karri},
title = {Black-Hat High-Level Synthesis: Myth or Reality?},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {913--926},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2884742},
doi = {10.1109/TVLSI.2018.2884742},
timestamp = {Tue, 31 Mar 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PilatoBRK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz19,
author = {Irith Pomeranz},
title = {Test Compaction by Test Removal Under Transparent Scan},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {496--500},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2878067},
doi = {10.1109/TVLSI.2018.2878067},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz19a,
author = {Irith Pomeranz},
title = {Extracting a Close-to-Minimum Multicycle Functional Broadside Test
Set From a Functional Test Sequence},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1428--1437},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2895386},
doi = {10.1109/TVLSI.2019.2895386},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz19b,
author = {Irith Pomeranz},
title = {Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple
Defects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1720--1724},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2900836},
doi = {10.1109/TVLSI.2019.2900836},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz19b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz19c,
author = {Irith Pomeranz},
title = {Extended Transparent-Scan},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2096--2104},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2916497},
doi = {10.1109/TVLSI.2019.2916497},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz19c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz19d,
author = {Irith Pomeranz},
title = {Padding of Multicycle Broadside and Skewed-Load Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2587--2595},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2924319},
doi = {10.1109/TVLSI.2019.2924319},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz19d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PourashrafRMCL19,
author = {Shirin Pourashraf and
Jaime Ram{\'{\i}}rez{-}Angulo and
Jose Maria Hinojo Montero and
Ram{\'{o}}n Gonz{\'{a}}lez Carvajal and
Antonio J. L{\'{o}}pez{-}Mart{\'{\i}}n},
title = {{\(\pm\)}0.25-V Class-AB {CMOS} Capacitance Multiplier and Precision
Rectifiers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {830--842},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2881249},
doi = {10.1109/TVLSI.2018.2881249},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PourashrafRMCL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QianQHCYGX19,
author = {Libo Qian and
Kefang Qian and
Xitao He and
Zhufei Chu and
Yidie Ye and
Shi Ge and
Yinshui Xia},
title = {Through-Silicon Via-Based Capacitor and Its Application in {LDO} Regulator
Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1947--1951},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2904200},
doi = {10.1109/TVLSI.2019.2904200},
timestamp = {Fri, 13 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/QianQHCYGX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QureshiKK19,
author = {Muhammad Avais Qureshi and
Hyeonggyu Kim and
Soontae Kim},
title = {A Restore-Free Mode for {MLC} {STT-RAM} Caches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1465--1469},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2899894},
doi = {10.1109/TVLSI.2019.2899894},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/QureshiKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RadhakrishnanYS19,
author = {Govind Radhakrishnan and
Youngki Yoon and
Manoj Sachdev},
title = {A Parametric {DFT} Scheme for STT-MRAMs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1685--1696},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2907549},
doi = {10.1109/TVLSI.2019.2907549},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RadhakrishnanYS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RahimipourZWSRS19,
author = {Somayeh Rahimipour and
Runjie Zhang and
Ke Wang and
Kevin Skadron and
Fakhrul Zaman Rokhani and
Mircea R. Stan},
title = {{MTTF} Enhancement Power-C4 Bump Placement Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1633--1639},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2904048},
doi = {10.1109/TVLSI.2019.2904048},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RahimipourZWSRS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RaiTRMWK19,
author = {Shubham Rai and
Jens Trommer and
Michael Raitza and
Thomas Mikolajick and
Walter M. Weber and
Akash Kumar},
title = {Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect
Transistors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {560--572},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2884646},
doi = {10.1109/TVLSI.2018.2884646},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RaiTRMWK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RajendranPKCD19,
author = {Murali Krishna Rajendran and
V. Priya and
Shourya Kansal and
Gajendranath Chowdary and
Ashudeb Dutta},
title = {A 100-mV-2.5-V Burst Mode Constant on-Time- Controlled Battery Charger
With 92{\%} Peak Efficiency and Integrated {FOCV} Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {430--443},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2878563},
doi = {10.1109/TVLSI.2018.2878563},
timestamp = {Mon, 08 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RajendranPKCD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RamboSE19,
author = {Eberle A. Rambo and
Yunsheng Shang and
Rolf Ernst},
title = {Providing Integrity in Real-Time Networks-on-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1907--1920},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2906471},
doi = {10.1109/TVLSI.2019.2906471},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RamboSE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RaniK19,
author = {Khushboo Rani and
Hemangee K. Kapoor},
title = {Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile
Buffers in On-Chip Interconnects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2191--2204},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2922471},
doi = {10.1109/TVLSI.2019.2922471},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RaniK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RehmanKCE19,
author = {Sami Ur Rehman and
Mohammad Mahdi Khafaji and
Corrado Carta and
Frank Ellinger},
title = {A 10-Gb/s 20-ps Delay-Range Digitally Controlled Differential Delay
Element in 45-nm {SOI} {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1233--1237},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2894736},
doi = {10.1109/TVLSI.2019.2894736},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RehmanKCE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RenaudDBM19,
author = {Guillaume Renaud and
Mamadou Diallo and
Manuel J. Barrag{\'{a}}n and
Salvador Mir},
title = {Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus
Generator for On-Chip Static Linearity Test of ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {281--293},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2876976},
doi = {10.1109/TVLSI.2018.2876976},
timestamp = {Wed, 28 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RenaudDBM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RestaLBGGM19,
author = {Giovanni V. Resta and
Alessandra Leonhardt and
Yashwanth Balaji and
Stefan De Gendt and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli},
title = {Devices and Circuits Using Novel 2-D Materials: {A} Perspective for
Future {VLSI} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1486--1503},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2914609},
doi = {10.1109/TVLSI.2019.2914609},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RestaLBGGM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReviriegoPU19,
author = {Pedro Reviriego and
Salvatore Pontarelli and
Anees Ullah},
title = {Error Detection and Correction in {SRAM} Emulated TCAMs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {486--490},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2877131},
doi = {10.1109/TVLSI.2018.2877131},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ReviriegoPU19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReviriegoUP19,
author = {Pedro Reviriego and
Anees Ullah and
Salvatore Pontarelli},
title = {{PR-TCAM:} Efficient {TCAM} Emulation on Xilinx FPGAs Using Partial
Reconfiguration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1952--1956},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2903980},
doi = {10.1109/TVLSI.2019.2903980},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ReviriegoUP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RienteMV19,
author = {Fabrizio Riente and
Daniel Melis and
Marco Vacca},
title = {Exploring the 3-D Integrability of Perpendicular Nanomagnet Logic
Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1711--1719},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2905686},
doi = {10.1109/TVLSI.2019.2905686},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RienteMV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Rodriguez-Montanes19,
author = {Rosa Rodr{\'{\i}}guez{-}Monta{\~{n}}{\'{e}}s and
Daniel Arum{\'{\i}} and
Joan Figueras},
title = {Postbond Test of Through-Silicon Vias With Resistive Open Defects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2596--2607},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2925971},
doi = {10.1109/TVLSI.2019.2925971},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Rodriguez-Montanes19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RohbaniGMMNMMT19,
author = {Nezam Rohbani and
Hiroaki Gau and
Sara Mohammadinejad and
Tapas Kumar Maiti and
Dondee Navarro and
Mitiko Miura{-}Mattausch and
Hans J{\"{u}}rgen Mattausch and
Hirotaka Takatsuka},
title = {Power Reduction and {BTI} Mitigation of Data-Cache Memory Based on
the Storage Management of Narrow-Width Values},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1675--1684},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2909488},
doi = {10.1109/TVLSI.2019.2909488},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RohbaniGMMNMMT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RoyAS19,
author = {Shirshendu Roy and
Debiprasad Priyabrata Acharya and
Ajit Kumar Sahoo},
title = {Low-Complexity Architecture of Orthogonal Matching Pursuit Based on
{QR} Decomposition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1623--1632},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2909754},
doi = {10.1109/TVLSI.2019.2909754},
timestamp = {Sun, 20 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RoyAS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RoyM19,
author = {Debapriya Basu Roy and
Debdeep Mukhopadhyay},
title = {High-Speed Implementation of {ECC} Scalar Multiplication in GF(p)
for Generic Montgomery Curves},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1587--1600},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2905899},
doi = {10.1109/TVLSI.2019.2905899},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RoyM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RyuPK19,
author = {Sungju Ryu and
Naebeom Park and
Jae{-}Joon Kim},
title = {Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the
Machine Learning Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {138--146},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2873716},
doi = {10.1109/TVLSI.2018.2873716},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RyuPK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SadhukhanDM19,
author = {Rajat Sadhukhan and
Nilanjan Datta and
Debdeep Mukhopadhyay},
title = {Power Efficiency of S-Boxes: From a Machine-Learning-Based Tool to
a Deterministic Model},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2829--2841},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2925421},
doi = {10.1109/TVLSI.2019.2925421},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SadhukhanDM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SaeedZWDK19,
author = {Samah Mohamed Saeed and
Alwin Zulehner and
Robert Wille and
Rolf Drechsler and
Ramesh Karri},
title = {Reversible Circuits: {IC/IP} Piracy Attacks and Countermeasures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2523--2535},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2934465},
doi = {10.1109/TVLSI.2019.2934465},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SaeedZWDK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SahaS19,
author = {Debasri Saha and
Susmita Sur{-}Kolay},
title = {Guided GA-Based Multiobjective Optimization of Placement and Assignment
of TSVs in 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1742--1750},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2908087},
doi = {10.1109/TVLSI.2019.2908087},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SahaS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SainiB19,
author = {Gaurav Saini and
Maryam Shojaei Baghini},
title = {A Generic Power Management Circuit for Energy Harvesters With Shared
Components Between the {MPPT} and Regulator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {535--548},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2885928},
doi = {10.1109/TVLSI.2018.2885928},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SainiB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SakibSS19,
author = {Ashiq A. Sakib and
Scott C. Smith and
Sudarshan K. Srinivasan},
title = {Formal Modeling and Verification of {PCHB} Asynchronous Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2911--2924},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2937087},
doi = {10.1109/TVLSI.2019.2937087},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SakibSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SalaminSAPMH19,
author = {Sami Salamin and
Victor M. van Santen and
Hussam Amrouch and
Narendra Parihar and
Souvik Mahapatra and
J{\"{o}}rg Henkel},
title = {Modeling the Interdependences Between Voltage Fluctuation and {BTI}
Aging},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1652--1665},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2899890},
doi = {10.1109/TVLSI.2019.2899890},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SalaminSAPMH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SandhuE19,
author = {Tejinder Singh Sandhu and
Kamal El{-}Sankary},
title = {Supply-Insensitive Digitally Controlled Delay Lines for 3-D {IC} Clock
Synchronization Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1480--1484},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2894104},
doi = {10.1109/TVLSI.2019.2894104},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SandhuE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SarkerKA19,
author = {Ausmita Sarker and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Hardware Constructions for Error Detection of Number-Theoretic Transform
Utilized in Secure Cryptographic Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {738--741},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2881097},
doi = {10.1109/TVLSI.2018.2881097},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SarkerKA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SayedBT19,
author = {Nour Sayed and
Rajendra Bishnoi and
Mehdi Baradaran Tahoori},
title = {Fast and Reliable {STT-MRAM} Using Nonuniform and Adaptive Error Detecting
and Correcting Scheme},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1329--1342},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2903592},
doi = {10.1109/TVLSI.2019.2903592},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SayedBT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShaoLFD19,
author = {Cuiping Shao and
Huiyun Li and
Jiayan Fang and
Qihua Deng},
title = {An Error Location and Correction Method for Memory Based on Data Similarity
Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2354--2364},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2920755},
doi = {10.1109/TVLSI.2019.2920755},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShaoLFD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShayanBSCK19,
author = {Mohammed Shayan and
Sukanta Bhattacharjee and
Yong{-}Ak Song and
Krishnendu Chakrabarty and
Ramesh Karri},
title = {Toward Secure Microfluidic Fully Programmable Valve Array Biochips},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2755--2766},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2924915},
doi = {10.1109/TVLSI.2019.2924915},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShayanBSCK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShiW19,
author = {Chuanjin Richard Shi and
Aili Wang},
title = {Analysis of Bitwise and Samplewise Switched Passive Charge Sharing
{SAR} ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {1977--1989},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2909671},
doi = {10.1109/TVLSI.2019.2909671},
timestamp = {Fri, 12 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShiW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShylendraBT19,
author = {Ahish Shylendra and
Swarup Bhunia and
Amit Ranjan Trivedi},
title = {An Intrinsic and Database-Free Authentication by Exploiting Process
Variation in Back-End Capacitors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1253--1261},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2903807},
doi = {10.1109/TVLSI.2019.2903807},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShylendraBT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SiastLD19,
author = {Jakub Siast and
Adam Luczak and
Marek Domanski},
title = {RingNet: {A} Memory-Oriented Network-On-Chip Designed for {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1284--1297},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2899575},
doi = {10.1109/TVLSI.2019.2899575},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SiastLD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SilvaLSG19,
author = {Rafael Sanchotene Silva and
Lucas Pereira Luiz and
M{\'{a}}rcio Cherem Schneider and
Carlos Galup{-}Montoro},
title = {A Test Chip for Characterization of the Series Association of MOSFETs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1967--1971},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2908338},
doi = {10.1109/TVLSI.2019.2908338},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SilvaLSG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SimicicWPRKG19,
author = {Marko Simicic and
Pieter Weckx and
Bertrand Parvais and
Philippe Roussel and
Ben Kaczer and
Georges G. E. Gielen},
title = {Understanding the Impact of Time-Dependent Random Variability on Analog
ICs: From Single Transistor Measurements to Circuit Simulations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {601--610},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2878841},
doi = {10.1109/TVLSI.2018.2878841},
timestamp = {Sun, 19 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SimicicWPRKG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinghR19,
author = {Jeetendra Singh and
Balwinder Raj},
title = {Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and
Temperature Impact on Store/Restore Energy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1322--1328},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2901032},
doi = {10.1109/TVLSI.2019.2901032},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SinghR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongZNZLYZ19,
author = {Wenqing Song and
Huayi Zhou and
Kai Niu and
Zaichen Zhang and
Li Li and
Xiaohu You and
Chuan Zhang},
title = {Efficient Successive Cancellation Stack Decoder for Polar Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2608--2619},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2925029},
doi = {10.1109/TVLSI.2019.2925029},
timestamp = {Thu, 02 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SongZNZLYZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SrivastavaM19,
author = {Nitish Kumar Srivastava and
Rajit Manohar},
title = {Operation-Dependent Frequency Scaling Using Desynchronization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {799--809},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2885335},
doi = {10.1109/TVLSI.2018.2885335},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SrivastavaM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunSZT19,
author = {Zeyu Sun and
Sheriff Sadiqbatcha and
Hengyang Zhao and
Sheldon X.{-}D. Tan},
title = {Saturation-Volume Estimation for Multisegment Copper Interconnect
Wires},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1666--1674},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2901824},
doi = {10.1109/TVLSI.2019.2901824},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SunSZT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TahaM19,
author = {Iman Y. Taha and
Mitra Mirhassani},
title = {A 24-GHz {DCO} With High-Amplitude Stabilization and Enhanced Startup
Time for Automotive Radar},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2260--2271},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2924018},
doi = {10.1109/TVLSI.2019.2924018},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TahaM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TangGMG19,
author = {Xifan Tang and
Edouard Giacomin and
Giovanni De Micheli and
Pierre{-}Emmanuel Gaillardon},
title = {{FPGA-SPICE:} {A} Simulation-Based Architecture Evaluation Framework
for FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {637--650},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2883923},
doi = {10.1109/TVLSI.2018.2883923},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TangGMG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TangJ19,
author = {Song{-}Nien Tang and
Fu{-}Chiang Jan},
title = {Energy-Efficient and Calibration-Aware Fourier-Domain {OCT} Imaging
Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1390--1403},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2894751},
doi = {10.1109/TVLSI.2019.2894751},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TangJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TangLFHC19,
author = {Yongkang Tang and
Shaoqing Li and
Liang Fang and
Xiao Hu and
Jihua Chen},
title = {Golden-Chip-Free Hardware Trojan Detection Through Quiescent Thermal
Maps},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2872--2883},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2933441},
doi = {10.1109/TVLSI.2019.2933441},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TangLFHC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThakkarTMA19,
author = {Arpan Thakkar and
Srinivas Theertham and
Peeyoosh Mirajkar and
Sankaran Aniruddhan},
title = {Techniques for Improved Continuous and Discrete Tuning Range in Millimeter-Wave
VCOs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {729--733},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2883355},
doi = {10.1109/TVLSI.2018.2883355},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ThakkarTMA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TidaZS19,
author = {Umamaheswara Rao Tida and
Cheng Zhuo and
Yiyu Shi},
title = {Single-Inductor-Multiple-Tier Regulation: TSV-Inductor-Based On-Chip
Buck Converters for 3-D {IC} Power Delivery},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2305--2316},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2919606},
doi = {10.1109/TVLSI.2019.2919606},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TidaZS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Tsai19,
author = {Jeng{-}Han Tsai},
title = {Design of a 5.3-GHz 31.3-dBm Fully Integrated {CMOS} Power Amplifier
Using Folded Splitting and Combining Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1527--1536},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2908956},
doi = {10.1109/TVLSI.2019.2908956},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Tsai19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/UdupiUSK19,
author = {Shrinidhi Udupi and
Joakim Urdahl and
Dominik Stoffel and
Wolfgang Kunz},
title = {Exploiting Hardware Unobservability for Low-Power Design and Safety
Analysis in Formal Verification-Driven Design Flows},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1262--1275},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2906820},
doi = {10.1109/TVLSI.2019.2906820},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/UdupiUSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/UllahUAL19,
author = {Inayat Ullah and
Zahid Ullah and
Umar Afzaal and
Jeong{-}A Lee},
title = {{DURE:} An Energy- and Resource-Efficient {TCAM} Architecture for
FPGAs With Dynamic Updates},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1298--1307},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2904105},
doi = {10.1109/TVLSI.2019.2904105},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/UllahUAL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/UlusanCIMK19,
author = {Hasan Ulusan and
Salar Chamanian and
Bedirhan Ilik and
Ali Muhtaroglu and
Haluk K{\"{u}}lah},
title = {Fully Implantable Cochlear Implant Interface Electronics With 51.2-
{\textdollar}{\textbackslash}mu{\textdollar} {W} Front-End Circuit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1504--1512},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2898873},
doi = {10.1109/TVLSI.2019.2898873},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/UlusanCIMK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/UsmaniKMSTH19,
author = {Mohammad A. Usmani and
Shahrzad Keshavarz and
Eric Matthews and
Lesley Shannon and
Russell Tessier and
Daniel E. Holcomb},
title = {Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {364--375},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2877438},
doi = {10.1109/TVLSI.2018.2877438},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/UsmaniKMSTH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VahdatKAP19,
author = {Shaghayegh Vahdat and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {{TOSAM:} An Energy-Efficient Truncation- and Rounding-Based Scalable
Approximate Multiplier},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1161--1173},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2890712},
doi = {10.1109/TVLSI.2018.2890712},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VahdatKAP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VashistKDG19,
author = {Abhishek Vashist and
Andrew Keats and
Sai Manoj Pudukotai Dinakarrao and
Amlan Ganguly},
title = {Securing a Wireless Network-on-Chip Against Jamming-Based Denial-of-Service
and Eavesdropping Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2781--2791},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2928960},
doi = {10.1109/TVLSI.2019.2928960},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VashistKDG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VatajeluN19,
author = {Elena Ioana Vatajelu and
Giorgio Di Natale},
title = {High-Entropy STT-MTJ-Based {TRNG}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {491--495},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2879439},
doi = {10.1109/TVLSI.2018.2879439},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VatajeluN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VigJJLO19,
author = {Saru Vig and
Rohan Juneja and
Guiyuan Jiang and
Siew{-}Kei Lam and
Changhai Ou},
title = {Framework for Fast Memory Authentication Using Dynamically Skewed
Integrity Tree},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2331--2343},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2923004},
doi = {10.1109/TVLSI.2019.2923004},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VigJJLO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VistaR19,
author = {John Vista and
Ashish Ranjan},
title = {A Simple Floating MOS-Memristor for High-Frequency Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1186--1195},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2890591},
doi = {10.1109/TVLSI.2018.2890591},
timestamp = {Fri, 21 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VistaR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WachterBRSAM19,
author = {Eduardo Weber W{\"{a}}chter and
Cedric de Bellefroid and
Basireddy Karunakar Reddy and
Amit Kumar Singh and
Bashir M. Al{-}Hashimi and
Geoff V. Merrett},
title = {Predictive Thermal Management for Energy-Efficient Execution of Concurrent
Applications on Heterogeneous Multicores},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1404--1415},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2896776},
doi = {10.1109/TVLSI.2019.2896776},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WachterBRSAM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WanKSS19,
author = {Tutu Wan and
Yasha Karimi and
Milutin Stanacevic and
Emre Salman},
title = {{AC} Computing Methodology for RF-Powered IoT Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1017--1028},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2894531},
doi = {10.1109/TVLSI.2019.2894531},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WanKSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangALONB19,
author = {Yuqi Wang and
Amira Aouina and
Hui Li and
Ian O'Connor and
Gabriela Nicolescu and
S{\'{e}}bastien Le Beux},
title = {Thermal-Aware Design Method for Laser Group Control in Nanophotonic
Interconnects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {742--746},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2888589},
doi = {10.1109/TVLSI.2018.2888589},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangALONB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangHT19,
author = {Xiaoxiao Wang and
Yueying Han and
Mark M. Tehranipoor},
title = {System-Level Counterfeit Detection Using On-Chip Ring Oscillator Array},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2884--2896},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2930532},
doi = {10.1109/TVLSI.2019.2930532},
timestamp = {Mon, 26 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangHT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangKKK19,
author = {Longfei Wang and
S. Karen Khatamifard and
Ulya R. Karpuzcu and
Sel{\c{c}}uk K{\"{o}}se},
title = {Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage
Regulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {229--242},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2871381},
doi = {10.1109/TVLSI.2018.2871381},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangKKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLJJS19,
author = {Qin Wang and
Zechen Liu and
Jianfei Jiang and
Naifeng Jing and
Weiguang Sheng},
title = {A New Cellular-Based Redundant {TSV} Structure for Clustered Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {458--467},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2876906},
doi = {10.1109/TVLSI.2018.2876906},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLJJS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLTS19,
author = {Chua{-}Chin Wang and
Pang{-}Yen Lou and
Tsung{-}Yi Tsai and
Hsiang{-}Yu Shih},
title = {74-dBc {SFDR} 71-MHz Four-Stage Pipeline ROM-Less {DDFS} Using Factorized
Second-Order Parabolic Equations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2464--2468},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2925574},
doi = {10.1109/TVLSI.2019.2925574},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLTS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangSFT19,
author = {Huanyu Wang and
Qihang Shi and
Domenic Forte and
Mark M. Tehranipoor},
title = {Probing Assessment Framework and Evaluation of Antiprobing Solutions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1239--1252},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2901449},
doi = {10.1109/TVLSI.2019.2901449},
timestamp = {Tue, 30 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangSFT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangSZEG19,
author = {Guanhua Wang and
Kexu Sun and
Qing Zhang and
Salam Elahmadi and
Ping Gui},
title = {A 43.6-dB {SNDR} 1-GS/s 3.2-mW {SAR} {ADC} With Background-Calibrated
Fine and Coarse Comparators in 28-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {1998--2007},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2912887},
doi = {10.1109/TVLSI.2019.2912887},
timestamp = {Thu, 15 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangSZEG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangTS19,
author = {Haomiao Wang and
Prabu Thiagaraj and
Oliver Sinnen},
title = {Harmonic-Summing Module of {SKA} on {FPGA} - Optimizing the Irregular
Memory Accesses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {624--636},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2882238},
doi = {10.1109/TVLSI.2018.2882238},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangTS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangWLSZ19,
author = {Hang Wang and
Tiancheng Wang and
Longjun Liu and
Hongbin Sun and
Nanning Zheng},
title = {Efficient Compression-Based Line Buffer Design for Image/Video Processing
Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2423--2433},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2921249},
doi = {10.1109/TVLSI.2019.2921249},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangWLSZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangXWGWQY19,
author = {Panni Wang and
Feng Xu and
Bo Wang and
Bin Gao and
Huaqiang Wu and
He Qian and
Shimeng Yu},
title = {Three-Dimensional nand Flash for Vector-Matrix Multiplication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {988--991},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2882194},
doi = {10.1109/TVLSI.2018.2882194},
timestamp = {Thu, 20 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangXWGWQY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WeinerWLSM19,
author = {Michael Weiner and
Wolfgang Wieser and
Emili Lupon and
Georg Sigl and
Salvador Manich},
title = {A Calibratable Detector for Invasive Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1067--1079},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2892408},
doi = {10.1109/TVLSI.2019.2892408},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WeinerWLSM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WenZZ19,
author = {Liang Wen and
Yuejun Zhang and
Xiaoyang Zeng},
title = {Column-Selection-Enabled 10T {SRAM} Utilizing Shared Diff-VDD Write
and Dropped-VDD Read for Power Reduction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1470--1474},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2898346},
doi = {10.1109/TVLSI.2019.2898346},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WenZZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WilliamsAJALC19,
author = {Christopher Williams and
Diaaeldin Abdelrahman and
Xiangdong Jia and
Abdullah Ibn Abbas and
Odile Liboiron{-}Ladouceur and
Glenn E. R. Cowan},
title = {Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel
Optical Links},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1548--1560},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2902503},
doi = {10.1109/TVLSI.2019.2902503},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WilliamsAJALC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WooY19,
author = {Jiyong Woo and
Shimeng Yu},
title = {Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for
Inference and Training of Neuromorphic System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2205--2212},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2917764},
doi = {10.1109/TVLSI.2019.2917764},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WooY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuLCX19,
author = {Jiaquan Wu and
Feiteng Li and
Zhijian Chen and
Xiaoyan Xiang},
title = {A 3.89-GOPS/mW Scalable Recurrent Neural Network Processor With Improved
Efficiency on Memory and Computation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2939--2943},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2927375},
doi = {10.1109/TVLSI.2019.2927375},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuLCX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuLR19,
author = {Cheng{-}Hung Wu and
Kuen{-}Jong Lee and
Sudhakar M. Reddy},
title = {An Efficient Diagnosis-Aware {ATPG} Procedure to Enhance Diagnosis
Resolution and Test Compaction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2105--2118},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2919233},
doi = {10.1109/TVLSI.2019.2919233},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuLR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuZCWLZ19,
author = {Bi Wu and
Beibei Zhang and
Yuanqing Cheng and
Ying Wang and
Dijun Liu and
Weisheng Zhao},
title = {An Adaptive Thermal-Aware {ECC} Scheme for Reliable {STT-MRAM} {LLC}
Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1851--1860},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2913207},
doi = {10.1109/TVLSI.2019.2913207},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuZCWLZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiaoNB19,
author = {Yao Xiao and
Shahin Nazarian and
Paul Bogdan},
title = {Self-Optimizing and Self-Programming Computing Systems: {A} Combined
Compiler, Complex Networks, and Machine Learning Approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1416--1427},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2897650},
doi = {10.1109/TVLSI.2019.2897650},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XiaoNB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XieLMM19,
author = {Jiafeng Xie and
Chiou{-}Yng Lee and
Pramod Kumar Meher and
Zhi{-}Hong Mao},
title = {Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers
Over {\textdollar}GF(2m){\textdollar} Based on Reordered Normal Basis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2119--2130},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2918836},
doi = {10.1109/TVLSI.2019.2918836},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XieLMM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiuWM19,
author = {Liming Xiu and
Xiangye Wei and
Yuhai Ma},
title = {A Full Digital Fractional-\emph{N} {TAF-FLL} for Digital Applications:
Demonstration of the Principle of a Frequency-Locked Loop Built on
Time-Average-Frequency},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {524--534},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2888625},
doi = {10.1109/TVLSI.2018.2888625},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XiuWM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuJQYWZZX19,
author = {Daiguo Xu and
Hequan Jiang and
Lei Qiu and
Xiaoquan Yu and
Jianan Wang and
Zhengping Zhang and
Can Zhu and
Shiliu Xu},
title = {A Linearity-Enhanced 10-Bit 160-MS/s {SAR} {ADC} With Low-Noise Comparator
Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {1990--1997},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2912504},
doi = {10.1109/TVLSI.2019.2912504},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XuJQYWZZX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuLNHZ19,
author = {Jiangtao Xu and
Wei Li and
Kaiming Nie and
Liqiang Han and
Xiyang Zhao},
title = {A Method to Reduce the Effect on Image Quality Caused by Resistance
of Column Bus},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {173--181},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2870858},
doi = {10.1109/TVLSI.2018.2870858},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XuLNHZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuS19,
author = {Siyuan Xu and
Benjamin Carri{\'{o}}n Sch{\"{a}}fer},
title = {Toward Self-Tunable Approximate Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {778--789},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2884848},
doi = {10.1109/TVLSI.2018.2884848},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XuS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XueSFWSYZH19,
author = {Pan Xue and
Yilei Shen and
Dan Fang and
Chenyang Wang and
Haijun Shao and
Ting Yi and
Xiaoyang Zeng and
Zhiliang Hong},
title = {A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian
Transmitter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {47--56},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2867079},
doi = {10.1109/TVLSI.2018.2867079},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XueSFWSYZH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangCGZZ19,
author = {Yintang Yang and
Ke Chen and
Huaxi Gu and
Bowen Zhang and
Lijing Zhu},
title = {TAONoC: {A} Regular Passive Optical Network-on-Chip Architecture Based
on Comb Switches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {954--963},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2885141},
doi = {10.1109/TVLSI.2018.2885141},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangCGZZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YazdanshenasB19,
author = {Sadegh Yazdanshenas and
Vaughn Betz},
title = {The Costs of Confidentiality in Virtualized FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2272--2283},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2919644},
doi = {10.1109/TVLSI.2019.2919644},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YazdanshenasB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YinCNH19,
author = {Xunzhao Yin and
Xiaoming Chen and
Michael T. Niemier and
Xiaobo Sharon Hu},
title = {Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {159--172},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2871119},
doi = {10.1109/TVLSI.2018.2871119},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YinCNH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YoshiokaSWKKIFS19,
author = {Kentaro Yoshioka and
Tomohiko Sugimoto and
Naoya Waki and
Sinnyoung Kim and
Daisuke Kurose and
Hirotomo Ishii and
Masanori Furuta and
Akihide Sai and
Hiroki Ishikuro and
Tetsuro Itakura},
title = {Digital Amplifier: {A} Power-Efficient and Process-Scaling Amplifier
for Switched Capacitor Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2575--2586},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2924686},
doi = {10.1109/TVLSI.2019.2924686},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YoshiokaSWKKIFS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuSF19,
author = {Tao{-}Chun Yu and
An{-}Jie Shih and
Shao{-}Yun Fang},
title = {Flip-Chip Routing With {I/O} Planning Considering Practical Pad Assignment
Constraints},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1921--1932},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2911006},
doi = {10.1109/TVLSI.2019.2911006},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YuSF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YunLIK19,
author = {Seong{-}Jin Yun and
Jiseong Lee and
Yun Chan Im and
Yong Sin Kim},
title = {A Digital {LDO} Regulator With a Self-Clocking Burst Logic for Ultralow
Power Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2237--2245},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2920910},
doi = {10.1109/TVLSI.2019.2920910},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YunLIK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZarubaB19,
author = {Florian Zaruba and
Luca Benini},
title = {The Cost of Application-Class Processing: Energy and Performance Analysis
of a Linux-Ready 1.7-GHz 64-Bit {RISC-V} Core in 22-nm {FDSOI} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2629--2640},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2926114},
doi = {10.1109/TVLSI.2019.2926114},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZarubaB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZengZD19,
author = {Wei Zeng and
Boyu Zhang and
Azadeh Davoodi},
title = {Analysis of Security of Split Manufacturing Using Machine Learning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2767--2780},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2929710},
doi = {10.1109/TVLSI.2019.2929710},
timestamp = {Thu, 02 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZengZD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZervakisKAZS19,
author = {Georgios Zervakis and
Konstantina Koliogeorgi and
Dimitrios Anagnostos and
Nikolaos Zompakis and
Kostas Siozios},
title = {{VADER:} Voltage-Driven Netlist Pruning for Cross-Layer Approximate
Arithmetic Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1460--1464},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2900160},
doi = {10.1109/TVLSI.2019.2900160},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZervakisKAZS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhanCK19,
author = {Chenchang Zhan and
Guigang Cai and
Wing{-}Hung Ki},
title = {A Transient-Enhanced Output-Capacitor-Free Low-Dropout Regulator With
Dynamic Miller Compensation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {243--247},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2867850},
doi = {10.1109/TVLSI.2018.2867850},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhanCK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhanCSL19,
author = {Xin Zhan and
Jianhao Chen and
Edgar S{\'{a}}nchez{-}Sinencio and
Peng Li},
title = {Power Management for Multicore Processors via Heterogeneous Voltage
Regulation and Machine Learning Enabled Adaptation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2641--2654},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2923911},
doi = {10.1109/TVLSI.2019.2923911},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhanCSL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangBP19,
author = {Yang Zhang and
Debajit Basak and
Kong{-}Pang Pun},
title = {Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter,
and {ISI}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {337--349},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2874259},
doi = {10.1109/TVLSI.2018.2874259},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangBP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangNKY19,
author = {Zhiming Zhang and
Laurent Njilla and
Charles A. Kamhoua and
Qiaoyan Yu},
title = {Thwarting Security Threats From Malicious {FPGA} Tools With Novel
FPGA-Oriented Moving Target Defense},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {3},
pages = {665--678},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2879878},
doi = {10.1109/TVLSI.2018.2879878},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangNKY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangPWDY19,
author = {Yuejun Zhang and
Zhao Pan and
Pengjun Wang and
Dailu Ding and
Qiaoyan Yu},
title = {A 0.1-pJ/b and {ACF} {\textless}0.04 Multiple-Valued {PUF} for Chip
Identification Using Bit-Line Sharing Strategy in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {5},
pages = {1043--1052},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2896142},
doi = {10.1109/TVLSI.2019.2896142},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangPWDY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouSLS19,
author = {Mi Zhou and
Zhuochao Sun and
Qiong Wei Low and
Liter Siek},
title = {Multiloop Control for Fast Transient {DC-DC} Converter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {1},
pages = {219--228},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2869430},
doi = {10.1109/TVLSI.2018.2869430},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouSLS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouSSCT19,
author = {Han Zhou and
Zeyu Sun and
Sheriff Sadiqbatcha and
Naehyuck Chang and
Sheldon X.{-}D. Tan},
title = {EM-Aware and Lifetime-Constrained Optimization for Multisegment Power
Grid Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {940--953},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2889079},
doi = {10.1109/TVLSI.2018.2889079},
timestamp = {Wed, 28 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouSSCT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuLLWL19,
author = {Congyi Zhu and
Renrong Liang and
Jun Lin and
Zhongfeng Wang and
Li Li},
title = {Analysis and Design of a Large Dither Injection Circuit for Improving
Linearity in Pipelined ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2008--2020},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2912421},
doi = {10.1109/TVLSI.2019.2912421},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuLLWL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZimmermannSTAS19,
author = {Lukas Zimmermann and
Alexander Scholz and
Mehdi Baradaran Tahoori and
Jasmin Aghassi{-}Hagmann and
Axel Sikora},
title = {Design and Evaluation of a Printed Analog-Based Differential Physical
Unclonable Function},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2498--2510},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2924081},
doi = {10.1109/TVLSI.2019.2924081},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZimmermannSTAS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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