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@article{DBLP:journals/tvlsi/AhmadiAKA24,
  author       = {Kasra Ahmadi and
                  Saeed Aghapour and
                  Mehran Mozaffari Kermani and
                  Reza Azarderakhsh},
  title        = {Efficient Error Detection Schemes for {ECSM} Window Method Benchmarked
                  on FPGAs},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {592--596},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3341147},
  doi          = {10.1109/TVLSI.2023.3341147},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/AhmadiAKA24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/AlshayaPP24,
  author       = {Abdulaziz Alshaya and
                  Sudhakar Pamarti and
                  Christos Papavassiliou},
  title        = {{FPGA} Crystal Oscillator Circuit Emulation Based on Wave Digital
                  Filter},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {103--115},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3305597},
  doi          = {10.1109/TVLSI.2023.3305597},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/AlshayaPP24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/AltoobajiHAAL24,
  author       = {Isa H. Altoobaji and
                  Ahmad Hassan and
                  Mohamed Ali and
                  Yves Audet and
                  Ahmed Lakhssassi},
  title        = {A Low-Power 0.68-Gbps Data Communication System for Capacitive Digital
                  Isolator With 1.9-ns Propagation Delay},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {952--956},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3344413},
  doi          = {10.1109/TVLSI.2023.3344413},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/AltoobajiHAAL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/AnZWYLGLTWHYFLLD24,
  author       = {Junjie An and
                  Zhidao Zhou and
                  Linfang Wang and
                  Wang Ye and
                  Weizeng Li and
                  Hanghang Gao and
                  Zhi Li and
                  Jinghui Tian and
                  Yan Wang and
                  Hongyang Hu and
                  Jinshan Yue and
                  Lingyan Fan and
                  Shibing Long and
                  Qi Liu and
                  Chunmeng Dou},
  title        = {Write-Verify-Free {MLC} {RRAM} Using Nonbinary Encoding for {AI} Weight
                  Storage at the Edge},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {283--290},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3318744},
  doi          = {10.1109/TVLSI.2023.3318744},
  timestamp    = {Tue, 13 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/AnZWYLGLTWHYFLLD24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/AnikDGK24,
  author       = {Md Toufiq Hasan Anik and
                  Jean{-}Luc Danger and
                  Sylvain Guilley and
                  Naghmeh Karimi},
  title        = {On the Resiliency of Protected Masked S-Boxes Against Template Attack
                  in the Presence of Temperature and Aging Misalignments},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {911--924},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3374257},
  doi          = {10.1109/TVLSI.2024.3374257},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/AnikDGK24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BaiXXWWZ24,
  author       = {Na Bai and
                  Xin Xiao and
                  Yaohua Xu and
                  Yi Wang and
                  Liang Wang and
                  Xinjie Zhou},
  title        = {Soft-Error-Aware {SRAM} With Multinode Upset Tolerance for Aerospace
                  Applications},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {128--136},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3328717},
  doi          = {10.1109/TVLSI.2023.3328717},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BaiXXWWZ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BaoHBX24,
  author       = {Tianyou Bao and
                  Pengzhou He and
                  Shi Bai and
                  Jiafeng Xie},
  title        = {{TINA:} TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based
                  {PQC}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {870--882},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3341037},
  doi          = {10.1109/TVLSI.2023.3341037},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BaoHBX24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/BroschPGS24,
  author       = {Manuel Brosch and
                  Matthias Probst and
                  Matthias Glaser and
                  Georg Sigl},
  title        = {A Masked Hardware Accelerator for Feed-Forward Neural Networks With
                  Fixed-Point Arithmetic},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {231--244},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3340553},
  doi          = {10.1109/TVLSI.2023.3340553},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BroschPGS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChangXJPWWZZ24,
  author       = {Ke Chang and
                  Qian Xing and
                  Guoliang Jia and
                  Yang Pu and
                  Yan Wang and
                  Yuxin Wang and
                  Yanlong Zhang and
                  Guohe Zhang},
  title        = {An Improved {DEM} for Multibit {DT} {\(\Sigma\)}{\(\Delta\)}Ms Based
                  on Poles Splitting Technique and Segmented {VQ}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {200--204},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3318230},
  doi          = {10.1109/TVLSI.2023.3318230},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChangXJPWWZZ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChangZYYLLZ24,
  author       = {Liang Chang and
                  Xin Zhao and
                  Ting Yue and
                  Xi Yang and
                  Chenglong Li and
                  Shuisheng Lin and
                  Jun Zhou},
  title        = {{IPOCIM:} Artificial Intelligent Architecture Design Space Exploration
                  With Scalable Ping-Pong Computing-in-Memory Macro},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {256--268},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3330648},
  doi          = {10.1109/TVLSI.2023.3330648},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChangZYYLLZ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChenDH24,
  author       = {Chao{-}Yu Chen and
                  Yan{-}Siou Dai and
                  Hao{-}Chiao Hong},
  title        = {A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding
                  Scheme and Analog Computing in Low-Leakage 8T {SRAM}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {848--859},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3368849},
  doi          = {10.1109/TVLSI.2024.3368849},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChenDH24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChenLSYXQJ24,
  author       = {Bofan Chen and
                  Zhiqun Li and
                  Wei Shi and
                  Yan Yao and
                  Zhi{-}Ying Xia and
                  Bing{-}Yan Qiu and
                  Hao Ji},
  title        = {A 6-18-GHz 6-bit Full-360{\textdegree} Vector-Sum Phase Shifter With
                  Low Error in 40-nm {CMOS}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {530--541},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3331508},
  doi          = {10.1109/TVLSI.2023.3331508},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChenLSYXQJ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChenYCWD24,
  author       = {Zhuojun Chen and
                  Wenhao Yang and
                  Jinghang Chen and
                  Zujun Wang and
                  Ding Ding},
  title        = {Improving Radiation Reliability of SRAM-Based Physical Unclonable
                  Function With Self-Healing and Pre-Irradiation Masking Techniques},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {372--381},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3332010},
  doi          = {10.1109/TVLSI.2023.3332010},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChenYCWD24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChoiHCS24,
  author       = {Sureum Choi and
                  Daejin Han and
                  Chanyeong Choi and
                  Yeongkyo Seo},
  title        = {Layout-Aware Area Optimization of Transposable {STT-MRAM} for a Processing-In-Memory
                  System},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {245--255},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3336804},
  doi          = {10.1109/TVLSI.2023.3336804},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChoiHCS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ChouCL24,
  author       = {Po{-}Yuan Chou and
                  Wei{-}Ming Chen and
                  Shen{-}Iuan Liu},
  title        = {A 16-Gb/s Baud-Rate {CDR} Circuit With One-Tap Speculative {DFE} and
                  Wide Frequency Capture Range},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {480--484},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3353197},
  doi          = {10.1109/TVLSI.2024.3353197},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChouCL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ClementsL24,
  author       = {Joseph Franklin Clements and
                  Yingjie Lao},
  title        = {Reliable Hardware Watermarks for Deep Learning Systems},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {752--762},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3360240},
  doi          = {10.1109/TVLSI.2024.3360240},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ClementsL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/DaiLZQHYW24,
  author       = {Yuan Dai and
                  Jingyuan Li and
                  Qilong Zhu and
                  Yunhui Qiu and
                  Yihan Hu and
                  Wenbo Yin and
                  Lingli Wang},
  title        = {{HETA:} {A} Heterogeneous Temporal {CGRA} Modeling and Design Space
                  Exploration via Bayesian Optimization},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {505--518},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3344536},
  doi          = {10.1109/TVLSI.2023.3344536},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/DaiLZQHYW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/EleftheriadisCK24,
  author       = {Charalampos Eleftheriadis and
                  Georgios Chatzitsompanis and
                  Georgios Karakonstantis},
  title        = {Enabling Voltage Over-Scaling in Multiplierless {DSP} Architectures
                  via Algorithm-Hardware Co-Design},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {219--230},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3308607},
  doi          = {10.1109/TVLSI.2023.3308607},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/EleftheriadisCK24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ErcanXZLYZ24,
  author       = {Renas Ercan and
                  Yunjia Xia and
                  Yunyi Zhao and
                  Rui C. V. Loureiro and
                  Shufan Yang and
                  Hubin Zhao},
  title        = {An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts
                  Detection},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {763--773},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3356161},
  doi          = {10.1109/TVLSI.2024.3356161},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ErcanXZLYZ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/FeylingMWLY24,
  author       = {Fredrik Feyling and
                  Hampus Malmberg and
                  Carsten Wulff and
                  Hans{-}Andrea Loeliger and
                  Trond Ytterdal},
  title        = {Design and Analysis of the Leapfrog Control-Bounded {A/D} Converter},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {79--88},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3320279},
  doi          = {10.1109/TVLSI.2023.3320279},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/FeylingMWLY24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/GhoshSCBSGVRKU24,
  author       = {Agnimesh Ghosh and
                  Andrei Spelman and
                  Tze Hin Cheung and
                  Dhanashree Boopathy and
                  Kari Stadius and
                  Manil Dev Gomony and
                  Mikko Valkama and
                  Jussi Ryyn{\"{a}}nen and
                  Marko Kosunen and
                  Vishnu Unnikrishnan},
  title        = {Reconfigurable Signal Processing and {DSP} Hardware Generator for
                  5G and Beyond Transmitters},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {4--15},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3326159},
  doi          = {10.1109/TVLSI.2023.3326159},
  timestamp    = {Fri, 08 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/GhoshSCBSGVRKU24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/GuptaLC24,
  author       = {Shourya Gupta and
                  Shuo Li and
                  Benton H. Calhoun},
  title        = {Scalable All-Analog LDOs With Reduced Input Offset Variability Using
                  Digital Synthesis Flow in 65-nm {CMOS}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {190--194},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3328978},
  doi          = {10.1109/TVLSI.2023.3328978},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/GuptaLC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/HaoWLZZLLPZZDLW24,
  author       = {Licai Hao and
                  Yaling Wang and
                  Yunlong Liu and
                  Shiyu Zhao and
                  Xinyi Zhang and
                  Yang Li and
                  Wenjuan Lu and
                  Chunyu Peng and
                  Qiang Zhao and
                  Yongliang Zhou and
                  Chenghu Dai and
                  Zhiting Lin and
                  Xiulong Wu},
  title        = {Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {883--896},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3357312},
  doi          = {10.1109/TVLSI.2024.3357312},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HaoWLZZLLPZZDLW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/HaoZDZLPZLW24,
  author       = {Licai Hao and
                  Xinyi Zhang and
                  Chenghu Dai and
                  Qiang Zhao and
                  Wenjuan Lu and
                  Chunyu Peng and
                  Yongliang Zhou and
                  Zhiting Lin and
                  Xiulong Wu},
  title        = {Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity
                  Design and Source-Isolation Technologies},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {597--608},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3342982},
  doi          = {10.1109/TVLSI.2023.3342982},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HaoZDZLPZLW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/HuLWL24,
  author       = {Xiao Hu and
                  Zhihao Li and
                  Zhongfeng Wang and
                  Xianhui Lu},
  title        = {{ALT:} Area-Efficient and Low-Latency {FPGA} Design for Torus Fully
                  Homomorphic Encryption},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {645--657},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3353374},
  doi          = {10.1109/TVLSI.2024.3353374},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HuLWL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/HuangR24,
  author       = {Yu{-}Kai Huang and
                  Saul Rodriguez},
  title        = {Noise Analysis and Design Methodology of Chopper Amplifiers With Analog
                  DC-Servo Loop for Biopotential Acquisition Applications},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {55--67},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3315417},
  doi          = {10.1109/TVLSI.2023.3315417},
  timestamp    = {Fri, 08 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HuangR24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/HuangWZY24,
  author       = {Pengcheng Huang and
                  Yaohua Wang and
                  Zhenyu Zhao and
                  Daheng Yue},
  title        = {{CAUTS:} Clock Tree Optimization via Skewed Cells With Complementary
                  Asymmetrical Uniform Transistor Sizing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {137--149},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3328592},
  doi          = {10.1109/TVLSI.2023.3328592},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HuangWZY24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/HuiLWLZM24,
  author       = {YaJuan Hui and
                  Qingzhen Li and
                  Leimin Wang and
                  Cheng Liu and
                  Deming Zhang and
                  Xiangshui Miao},
  title        = {In-Memory Wallace Tree Multipliers Based on Majority Gates Within
                  Voltage-Gated {SOT-MRAM} Crossbar Arrays},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {497--504},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3350151},
  doi          = {10.1109/TVLSI.2024.3350151},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HuiLWLZM24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/HyunJS24,
  author       = {Daijoon Hyun and
                  Younggwang Jung and
                  Youngsoo Shin},
  title        = {Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations
                  and Routing DRVs},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {823--834},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3364519},
  doi          = {10.1109/TVLSI.2024.3364519},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HyunJS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/JelcicovaKAS24,
  author       = {Zuzana Jelcicov{\'{a}} and
                  Evangelia Kasapaki and
                  Oskar Andersson and
                  Jens Spars{\o}},
  title        = {PeakEngine: {A} Deterministic On-the-Fly Pruning Neural Network Accelerator
                  for Hearing Instruments},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {150--163},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3300910},
  doi          = {10.1109/TVLSI.2023.3300910},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/JelcicovaKAS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/JiePDWZY24,
  author       = {Musha Ji'e and
                  Hongxin Peng and
                  Shukai Duan and
                  Lidan Wang and
                  Fengqing Zhang and
                  Dengwei Yan},
  title        = {Design and {FPGA} Implementation of Grid-Scroll Hamiltonian Conservative
                  Chaotic Flows With a Line Equilibrium},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {658--668},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3361889},
  doi          = {10.1109/TVLSI.2024.3361889},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/JiePDWZY24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/JoseKSTW24,
  author       = {Oliver Lexter July A. Jose and
                  Venkata Naveen Kolakaluri and
                  Ralph Gerard B. Sangalang and
                  Lean Karlo S. Tolentino and
                  Chua{-}Chin Wang},
  title        = {A 6.25-MHz 3.4-mW Single Clock {DPWM} Technique Using Matrix Shift
                  Array},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {972--976},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3367300},
  doi          = {10.1109/TVLSI.2024.3367300},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/JoseKSTW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/KimNOR24,
  author       = {Sunwoong Kim and
                  Cameron James Norris and
                  James I. Oelund and
                  Rob A. Rutenbar},
  title        = {Area-Efficient Iterative Logarithmic Approximate Multipliers for {IEEE}
                  754 and Posit Numbers},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {455--467},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3354726},
  doi          = {10.1109/TVLSI.2024.3354726},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/KimNOR24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/KimZTSL24,
  author       = {Jinwoo Kim and
                  Lingjun Zhu and
                  Hakki Mert Torun and
                  Madhavan Swaminathan and
                  Sung Kyu Lim},
  title        = {A {PPA} Study for Heterogeneous 3-D {IC} Options: Monolithic, Hybrid
                  Bonding, and Microbumping},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {401--412},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3342734},
  doi          = {10.1109/TVLSI.2023.3342734},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/KimZTSL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LanL24,
  author       = {Yi{-}Hao Lan and
                  Shen{-}Iuan Liu},
  title        = {A 0.079-pJ/b/dB 32-Gb/s 2{\texttimes} Half-Baud-Rate {CDR} Circuit
                  With Frequency Detector},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {704--713},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3330012},
  doi          = {10.1109/TVLSI.2023.3330012},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LanL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LaniusG24,
  author       = {Christian Lanius and
                  Tobias Gemmeke},
  title        = {Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory
                  Arrays for Genome Sequencing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {30--41},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3308262},
  doi          = {10.1109/TVLSI.2023.3308262},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LaniusG24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LiC24,
  author       = {Hongge Li and
                  Yuhao Chen},
  title        = {Hybrid Stochastic Number and Its Neural Network Computation},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {432--441},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3332170},
  doi          = {10.1109/TVLSI.2023.3332170},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LiFDSLZ24,
  author       = {Dengquan Li and
                  Tian Feng and
                  Jiale Ding and
                  Yi Shen and
                  Shubin Liu and
                  Zhangming Zhu},
  title        = {A Wideband Input Buffer Based on Cascade Complementary Source Follower},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {962--966},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3349564},
  doi          = {10.1109/TVLSI.2024.3349564},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiFDSLZ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LiWZSXCZL24,
  author       = {Zeju Li and
                  Qinfan Wang and
                  Zihan Zou and
                  Qiao Shen and
                  Na Xie and
                  Hao Cai and
                  Hao Zhang and
                  Bo Liu},
  title        = {Layer-Sensitive Neural Processing Architecture for Error-Tolerant
                  Applications},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {797--809},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3369648},
  doi          = {10.1109/TVLSI.2024.3369648},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiWZSXCZL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LiYWH24,
  author       = {Bin Li and
                  Yunfei Yan and
                  Yuanxin Wei and
                  Heru Han},
  title        = {Scalable and Parallel Optimization of the Number Theoretic Transform
                  Based on {FPGA}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {291--304},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3312423},
  doi          = {10.1109/TVLSI.2023.3312423},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiYWH24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LinCCTL24,
  author       = {Jia{-}Zhao Lin and
                  Po{-}Ta Chen and
                  Hung{-}Yuan Chin and
                  Pei{-}Yun Tsai and
                  Sz{-}Yuan Lee},
  title        = {Design and Implementation of a Real-Time Imaging Processor for Spaceborne
                  Synthetic Aperture Radar With Configurability},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {669--681},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3338476},
  doi          = {10.1109/TVLSI.2023.3338476},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LinCCTL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LiuCCWL24,
  author       = {Jun Liu and
                  Songren Cheng and
                  Tian Chen and
                  Xi Wu and
                  Huaguo Liang},
  title        = {A Self-Biased Current Reference Source-Based Pre-Bond {TSV} Test Solution},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {774--781},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3344272},
  doi          = {10.1109/TVLSI.2023.3344272},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiuCCWL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LiuKMS24,
  author       = {Si{-}Huang Liu and
                  Chia{-}Yi Kuo and
                  Yannan Mo and
                  Tao Su},
  title        = {An Area-Efficient, Conflict-Free, and Configurable Architecture for
                  Accelerating {NTT/INTT}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {519--529},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3336951},
  doi          = {10.1109/TVLSI.2023.3336951},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiuKMS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LiuMJWZLZLC24,
  author       = {Shiwei Liu and
                  Chen Mu and
                  Hao Jiang and
                  Yunzhengmao Wang and
                  Jinshan Zhang and
                  Feng Lin and
                  Keji Zhou and
                  Qi Liu and
                  Chixiao Chen},
  title        = {{HARDSEA:} Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory
                  Computing Accelerator for Dynamic Sparse Self-Attention in Transformer},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {269--282},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3337777},
  doi          = {10.1109/TVLSI.2023.3337777},
  timestamp    = {Thu, 14 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiuMJWZLZLC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LiuZWYZS24,
  author       = {Yiting Liu and
                  Hai Zhou and
                  Jia Wang and
                  Fan Yang and
                  Xuan Zeng and
                  Li Shang},
  title        = {Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary
                  Conditions},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {810--822},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3363666},
  doi          = {10.1109/TVLSI.2024.3363666},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiuZWYZS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LohG24,
  author       = {Johnson Loh and
                  Tobias Gemmeke},
  title        = {Stream Processing Architectures for Continuous {ECG} Monitoring Using
                  Subsampling- Based Classifiers},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {68--78},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3329360},
  doi          = {10.1109/TVLSI.2023.3329360},
  timestamp    = {Fri, 08 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LohG24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LuWAYLZQ24,
  author       = {Zhaojun Lu and
                  Xueyan Wang and
                  Md Tanvir Arafin and
                  Haoxiang Yang and
                  Zhenglin Liu and
                  Jiliang Zhang and
                  Gang Qu},
  title        = {An RRAM-Based Computing-in-Memory Architecture and Its Application
                  in Accelerating Transformer Inference},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {485--496},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3345651},
  doi          = {10.1109/TVLSI.2023.3345651},
  timestamp    = {Wed, 20 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LuWAYLZQ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/LuoLWTDZ24,
  author       = {Li Luo and
                  Bochang Li and
                  Lidan Wang and
                  Jinpei Tan and
                  Shukai Duan and
                  Chunxiang Zhu},
  title        = {Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for
                  In-Memory Computing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {835--847},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3370176},
  doi          = {10.1109/TVLSI.2024.3370176},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LuoLWTDZ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/MatsuiTTT24,
  author       = {Chihiro Matsui and
                  Kasidit Toprasertpong and
                  Shinichi Takagi and
                  Ken Takeuchi},
  title        = {FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory
                  Circuit Design for Neuromorphic Computing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {468--479},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3336379},
  doi          = {10.1109/TVLSI.2023.3336379},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/MatsuiTTT24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/MitrovicF24,
  author       = {Ana Mitrovic and
                  Eby G. Friedman},
  title        = {Thermal Exploration of {RSFQ} Integrated Circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {728--738},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3348452},
  doi          = {10.1109/TVLSI.2023.3348452},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/MitrovicF24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Mohanty24,
  author       = {Basant Kumar Mohanty},
  title        = {Memory-Efficient Multiplier-Less 2-D {DWT} Design Using Combined Convolution
                  and Lifting Schemes for Wireless Visual Sensors},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {695--703},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3367817},
  doi          = {10.1109/TVLSI.2024.3367817},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Mohanty24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/MowlaviGGS24,
  author       = {Siavash Mowlavi and
                  Stavros Giannakopoulos and
                  Alexander Grabowski and
                  Lars Svensson},
  title        = {A Review of {IC} Drivers for VCSELs in Datacom Applications},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {42--54},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3326876},
  doi          = {10.1109/TVLSI.2023.3326876},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/MowlaviGGS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/NolteTJHSWH24,
  author       = {Lars Nolte and
                  Tim Twardzik and
                  Camille Jalier and
                  Zhigang Huang and
                  Jiyuan Shi and
                  Thomas Wild and
                  Andreas Herkersdorf},
  title        = {{HW-FUTEX:} Hardware-Assisted Futex Syscall},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {16--29},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3317926},
  doi          = {10.1109/TVLSI.2023.3317926},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/NolteTJHSWH24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/NurmiAS24,
  author       = {Jari Nurmi and
                  Snorre Aunet and
                  Alireza Saberkari},
  title        = {Guest Editorial Selected Papers From {IEEE} Nordic Circuits and Systems
                  Conference (NorCAS) 2022},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {1--3},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3339268},
  doi          = {10.1109/TVLSI.2023.3339268},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/NurmiAS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/OrtegaTPBC24,
  author       = {Eduardo Ortega and
                  Jonti Talukdar and
                  Woohyun Paik and
                  Tyler K. Bletsch and
                  Krishnendu Chakrabarty},
  title        = {Rowhammer Vulnerability of DRAMs in 3-D Integration},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {967--971},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3368044},
  doi          = {10.1109/TVLSI.2024.3368044},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/OrtegaTPBC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/PeiML24,
  author       = {Likai Pei and
                  Xiaodong Meng and
                  Xing Li},
  title        = {A Novel Digital-Controlled Current-Mode Single-Inductor-Multiple-Output
                  Buck Converter With Individual Output Overload Protection},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {957--961},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3343763},
  doi          = {10.1109/TVLSI.2023.3343763},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/PeiML24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/PengL24,
  author       = {Hsi{-}Kai Peng and
                  Shen{-}Iuan Liu},
  title        = {A 12.93-16 Gb/s Reference-Less Baud-Rate {CDR} Circuit With One-Tap
                  {DFE} and Semirotational Frequency Detection},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {787--791},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3336020},
  doi          = {10.1109/TVLSI.2023.3336020},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/PengL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/PentapatiL24,
  author       = {Sai Pentapati and
                  Sung Kyu Lim},
  title        = {Heterogeneous Monolithic 3-D {IC} Designs: Challenges, {EDA} Solutions,
                  and Power, Performance, Cost Tradeoffs},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {413--421},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3347372},
  doi          = {10.1109/TVLSI.2023.3347372},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/PentapatiL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Pomeranz24,
  author       = {Irith Pomeranz},
  title        = {Testability Evaluation for Local Design Modifications},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {195--199},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3321572},
  doi          = {10.1109/TVLSI.2023.3321572},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Pomeranz24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Pomeranz24a,
  author       = {Irith Pomeranz},
  title        = {Bit-Complemented Test Data to Replace the Tail of a Fault Coverage
                  Curve},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {609--618},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3365355},
  doi          = {10.1109/TVLSI.2024.3365355},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Pomeranz24a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/RahmanB24,
  author       = {Md. Moshiur Rahman and
                  Swarup Bhunia},
  title        = {Practical Implementation of Robust State-Space Obfuscation for Hardware
                  {IP} Protection},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {333--346},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3307027},
  doi          = {10.1109/TVLSI.2023.3307027},
  timestamp    = {Sun, 03 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/RahmanB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/RathorSSM24,
  author       = {Vijaypal Singh Rathor and
                  Munesh Singh and
                  Kshira Sagar Sahoo and
                  Saraju P. Mohanty},
  title        = {GateLock: Input-Dependent Key-Based Locked Gates for {SAT} Resistant
                  Logic Locking},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {361--371},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3340350},
  doi          = {10.1109/TVLSI.2023.3340350},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/RathorSSM24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/RenaKP24,
  author       = {Rakesh Varma Rena and
                  Raviteja Kammari and
                  Vijay Shankar Pasupureddi},
  title        = {A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion
                  {RF} Front-End},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {552--563},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3342022},
  doi          = {10.1109/TVLSI.2023.3342022},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/RenaKP24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SamantarayER24,
  author       = {Aswini K. Samantaray and
                  Pranose J. Edavoor and
                  Amol D. Rahulkar},
  title        = {A Novel Design Approach and {VLSI} Architecture of Rationalized Bi-Orthogonal
                  Wavelet Filter Banks},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {619--632},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3342122},
  doi          = {10.1109/TVLSI.2023.3342122},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SamantarayER24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SeveroDANG24,
  author       = {Lucas Compassi Severo and
                  Tailize C. De{-}Oliveira and
                  Paulo C{\'{e}}sar Comassetto de Aguirre and
                  Wilhelmus A. M. Van Noije and
                  Alessandro Gon{\c{c}}alves Girardi},
  title        = {Variable Conversion Approach for Design Optimization of Low-Voltage
                  Low-Pass Filters},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {205--218},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3335877},
  doi          = {10.1109/TVLSI.2023.3335877},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SeveroDANG24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SongJCCYJ24,
  author       = {Changmin Song and
                  Hoyong Jung and
                  KyoungSeop Chang and
                  Kwanglae Cho and
                  Seungyong Yoon and
                  Young{-}Chan Jang},
  title        = {A 24-Gb/s {MIPI} {C-/D-PHY} Receiver Bridge Chip With Phase Error
                  Calibration Supporting FPGA-Based Frame Grabber},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {714--727},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3364839},
  doi          = {10.1109/TVLSI.2024.3364839},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SongJCCYJ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/TavakoliRQR24,
  author       = {Erfan Bank Tavakoli and
                  Michael Riera and
                  Masudul Hassan Quraishi and
                  Fengbo Ren},
  title        = {FSpGEMM: {A} Framework for Accelerating Sparse General Matrix-Matrix
                  Multiplication Using Gustavson's Algorithm on FPGAs},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {633--644},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3355499},
  doi          = {10.1109/TVLSI.2024.3355499},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/TavakoliRQR24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/TranDDHPH24,
  author       = {Thai{-}Ha Tran and
                  Duc{-}Thuan Dam and
                  Ba{-}Anh Dao and
                  Van{-}Phuc Hoang and
                  Cong{-}Kha Pham and
                  Trong{-}Thuc Hoang},
  title        = {Compacting Side-Channel Measurements With Amplitude Peak Location
                  Algorithm},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {573--586},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3339810},
  doi          = {10.1109/TVLSI.2023.3339810},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/TranDDHPH24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/UsamiYKASHB24,
  author       = {Kimiyoshi Usami and
                  Daiki Yokoyama and
                  Aika Kamei and
                  Hideharu Amano and
                  Kenta Suzuki and
                  Keizo Hiraga and
                  Kazuhiro Bessho},
  title        = {Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops
                  to Minimize Store Energy Under Process and Temperature Variations},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {89--102},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3318468},
  doi          = {10.1109/TVLSI.2023.3318468},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/UsamiYKASHB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/VegaSB24,
  author       = {Christopher Vega and
                  Patanjali SLPSK and
                  Swarup Bhunia},
  title        = {IOLock: An Input/Output Locking Scheme for Protection Against Reverse
                  Engineering Attacks},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {347--360},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3337310},
  doi          = {10.1109/TVLSI.2023.3337310},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/VegaSB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/WangXNCLZL24,
  author       = {Chenghan Wang and
                  Qinzhi Xu and
                  Chuanjun Nie and
                  He Cao and
                  Jianyun Liu and
                  Daoqing Zhang and
                  Zhiqiang Li},
  title        = {A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration
                  System},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {178--189},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3321933},
  doi          = {10.1109/TVLSI.2023.3321933},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/WangXNCLZL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/WangZLS24,
  author       = {Xingyu Wang and
                  Ruilin Zhang and
                  Kunyang Liu and
                  Hirofumi Shinohara},
  title        = {A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring
                  Static Inverter Selection and Noise Enhancement},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {564--572},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3328602},
  doi          = {10.1109/TVLSI.2023.3328602},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/WangZLS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/XieSCDD24,
  author       = {Chenjia Xie and
                  Zhuang Shao and
                  Zhichao Chen and
                  Yuan Du and
                  Li Du},
  title        = {An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal
                  Redundancy Reduction},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {4},
  pages        = {782--786},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3335232},
  doi          = {10.1109/TVLSI.2023.3335232},
  timestamp    = {Mon, 01 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/XieSCDD24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/XuWHWCL24,
  author       = {Dongdong Xu and
                  Xiang Wang and
                  Qiang Hao and
                  Jiqing Wang and
                  Shuangjie Cui and
                  Bo Liu},
  title        = {A High-Performance Transparent Memory Data Encryption and Authentication
                  Scheme Based on Ascon Cipher},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {925--937},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3372026},
  doi          = {10.1109/TVLSI.2024.3372026},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/XuWHWCL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/YanSGLWXSWH24,
  author       = {Run Yan and
                  Yin Su and
                  Hui Guo and
                  Yashuai L{\"{u}} and
                  Jin Wang and
                  Nong Xiao and
                  Li Shen and
                  Yongwen Wang and
                  Libo Huang},
  title        = {{MPRTA:} An Efficient Multilevel Parallel Mobile Accelerator for High-Performance
                  Ray Tracing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {396--400},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3334711},
  doi          = {10.1109/TVLSI.2023.3334711},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/YanSGLWXSWH24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/YanWCHNGW24,
  author       = {Aibin Yan and
                  Litao Wang and
                  Jie Cui and
                  Zhengfeng Huang and
                  Tianming Ni and
                  Patrick Girard and
                  Xiaoqing Wen},
  title        = {Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using
                  Magnetic Tunnel Junctions and {CMOS}},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {116--127},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3323562},
  doi          = {10.1109/TVLSI.2023.3323562},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/YanWCHNGW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/YangMXXWM24,
  author       = {Chen Yang and
                  Yishuo Meng and
                  Jiawei Xi and
                  Siwei Xiang and
                  Jianfei Wang and
                  Kuizhi Mei},
  title        = {{WRA-SS:} {A} High-Performance Accelerator Integrating Winograd With
                  Structured Sparsity for Convolutional Neural Networks},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {1},
  pages        = {164--177},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3330993},
  doi          = {10.1109/TVLSI.2023.3330993},
  timestamp    = {Sat, 13 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/YangMXXWM24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZareieEEF24,
  author       = {Mahsa Zareie and
                  Kamal El{-}Sankary and
                  Ezz I. El{-}Masry and
                  Ximing Fu},
  title        = {An Open-Loop {VCO-ADC} Based on a Linearized Current Control Technique},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {587--591},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3337205},
  doi          = {10.1109/TVLSI.2023.3337205},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZareieEEF24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZhangCMJLW24,
  author       = {Jingqi Zhang and
                  Zhiming Chen and
                  Mingzhi Ma and
                  Rongkun Jiang and
                  Hongshuo Li and
                  Weijiang Wang},
  title        = {High-Performance {ECC} Scalar Multiplication Architecture Based on
                  Comb Method and Low-Latency Window Recoding Algorithm},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {382--395},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3321772},
  doi          = {10.1109/TVLSI.2023.3321772},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZhangCMJLW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZhangCP24,
  author       = {Bo Zhang and
                  Zeming Cheng and
                  Massoud Pedram},
  title        = {Design of a High-Performance Iterative Barrett Modular Multiplier
                  for Crypto Systems},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {897--910},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3368002},
  doi          = {10.1109/TVLSI.2024.3368002},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZhangCP24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZhangLI24,
  author       = {Haoming Zhang and
                  Shuowei Li and
                  Tetsuya Iizuka},
  title        = {A Single Ring-Oscillator-Based Test Structure for Timing Characterization
                  of Dynamic Circuit},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {938--951},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3370862},
  doi          = {10.1109/TVLSI.2024.3370862},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZhangLI24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZhangQHX24,
  author       = {Yongqiang Zhang and
                  Jiao Qin and
                  Jie Han and
                  Guangjun Xie},
  title        = {Design of a Stochastic Computing Architecture for the Phansalkar Algorithm},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {442--454},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3348809},
  doi          = {10.1109/TVLSI.2023.3348809},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZhangQHX24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZhangRKAF24,
  author       = {Tao Zhang and
                  Md Latifur Rahman and
                  Hadi Mardani Kamali and
                  Kimia Zamiri Azar and
                  Farimah Farahmandi},
  title        = {SiPGuard: Run-Time System-in-Package Security Monitoring via Power
                  Noise Variation},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {305--318},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3322384},
  doi          = {10.1109/TVLSI.2023.3322384},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZhangRKAF24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZhangTF24,
  author       = {Tao Zhang and
                  Mark M. Tehranipoor and
                  Farimah Farahmandi},
  title        = {TrustGuard: Standalone FPGA-Based Security Monitoring Through Power
                  Side-Channel},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {2},
  pages        = {319--332},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3335876},
  doi          = {10.1109/TVLSI.2023.3335876},
  timestamp    = {Thu, 29 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZhangTF24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZhengCCGXC24,
  author       = {Xin Zheng and
                  Mingjun Cheng and
                  Jiasong Chen and
                  Huaien Gao and
                  Xiaoming Xiong and
                  Shuting Cai},
  title        = {{BSSE:} Design Space Exploration on the {BOOM} With Semi-Supervised
                  Learning},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {5},
  pages        = {860--869},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3368075},
  doi          = {10.1109/TVLSI.2024.3368075},
  timestamp    = {Fri, 17 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZhengCCGXC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZhengLDYSZSQZLWZ24,
  author       = {Yifei Zheng and
                  Boyu Li and
                  Qianheng Dong and
                  Yutao Ying and
                  Deyuan Song and
                  Jing Zhu and
                  Weifeng Sun and
                  Qinsong Qian and
                  Long Zhang and
                  Sheng Li and
                  Denggui Wang and
                  Jianjun Zhou},
  title        = {A 200-V Half-Bridge Monolithic GaN Power {IC} With High-Speed Level
                  Shifter and dV\({}_{\mbox{S}}\)/dt Noise Immunity Enhancement Structure},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {542--551},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2023.3335137},
  doi          = {10.1109/TVLSI.2023.3335137},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZhengLDYSZSQZLWZ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/ZhengYLLWZ24,
  author       = {Xiaoxiao Zheng and
                  Mao Ye and
                  Zhiwei Li and
                  Yao Li and
                  Qiuwei Wang and
                  Yiqiang Zhao},
  title        = {A {CMOS} {AFE} Array With {DC} Input Current Cancellation for {FMCW}
                  LiDAR},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {32},
  number       = {3},
  pages        = {422--431},
  year         = {2024},
  url          = {https://doi.org/10.1109/TVLSI.2024.3350870},
  doi          = {10.1109/TVLSI.2024.3350870},
  timestamp    = {Sat, 16 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ZhengYLLWZ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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