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@article{DBLP:journals/vlsisp/BlumeSN06,
  author       = {Holger Blume and
                  Thorsten von Sydow and
                  Tobias G. Noll},
  title        = {A Case Study for the Application of Deterministic and Stochastic Petri
                  Nets in the SoC Communication Domain},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {223--233},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7272-4},
  doi          = {10.1007/S11265-006-7272-4},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BlumeSN06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/BoryssenkoS06,
  author       = {A. O. Boryssenko and
                  D. H. Schaubert},
  title        = {Electromagnetics-Related Aspects of Signaling and Signal Processing
                  for {UWB} Short Range Radios},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {1},
  pages        = {89--104},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7282-2},
  doi          = {10.1007/S11265-006-7282-2},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BoryssenkoS06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/CengSHLAMB06,
  author       = {Jianjiang Ceng and
                  Weihua Sheng and
                  Manuel Hohenauer and
                  Rainer Leupers and
                  Gerd Ascheid and
                  Heinrich Meyr and
                  Gunnar Braun},
  title        = {Modeling Instruction Semantics in {ADL} Processor Descriptions for
                  {C} Compiler Retargeting},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {235--246},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7273-3},
  doi          = {10.1007/S11265-006-7273-3},
  timestamp    = {Sun, 22 Oct 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/CengSHLAMB06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ChengP06a,
  author       = {Chao Cheng and
                  Keshab K. Parhi},
  title        = {Hardware efficient fast computation of the discrete fourier transform},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {1},
  pages        = {105--106},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-8456-7},
  doi          = {10.1007/S11265-006-8456-7},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ChengP06a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/FengN06,
  author       = {Lei Feng and
                  Won Namgoong},
  title        = {An Analog/Digital Baseband Processor Design of a {UWB} Channelized
                  Receiver for Transmitted Reference Signals},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {1},
  pages        = {59--71},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7280-4},
  doi          = {10.1007/S11265-006-7280-4},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/FengN06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/HosemannF06,
  author       = {Michael Hosemann and
                  Gerhard P. Fettweis},
  title        = {On Enhancing SIMD-controlled DSPs for Performing Recursive Filtering},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {125--142},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7266-2},
  doi          = {10.1007/S11265-006-7266-2},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/HosemannF06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/LemaitreAD06,
  author       = {J{\'{e}}r{\^{o}}me Lemaitre and
                  Sylvain Alliot and
                  Ed F. Deprettere},
  title        = {Requirements for Interfacing IP-Components in Re-configurable Platforms},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {173--184},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7269-z},
  doi          = {10.1007/S11265-006-7269-Z},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/LemaitreAD06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/McallisterWWR06,
  author       = {John McAllister and
                  Roger F. Woods and
                  Richard L. Walke and
                  Darren Gerard Reilly},
  title        = {Multidimensional {DSP} Core Synthesis for {FPGA}},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {207--221},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7271-5},
  doi          = {10.1007/S11265-006-7271-5},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/McallisterWWR06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Namgoong06,
  author       = {Won Namgoong},
  title        = {Editorial},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {1},
  pages        = {5},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7276-0},
  doi          = {10.1007/S11265-006-7276-0},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Namgoong06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/PanainteBV06,
  author       = {Elena Moscu Panainte and
                  Koen Bertels and
                  Stamatis Vassiliadis},
  title        = {Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {161--172},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7268-0},
  doi          = {10.1007/S11265-006-7268-0},
  timestamp    = {Mon, 28 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/PanainteBV06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/PimentelV06,
  author       = {Andy D. Pimentel and
                  Stamatis Vassiliadis},
  title        = {Editorial},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {111},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7264-4},
  doi          = {10.1007/S11265-006-7264-4},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/PimentelV06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SaberiniaCST06,
  author       = {Ebrahim Saberinia and
                  K. C. Chang and
                  Gerald E. Sobelman and
                  Ahmed H. Tewfik},
  title        = {Implementation of a Multi-band Pulsed-OFDM Transceiver},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {1},
  pages        = {73--88},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7281-3},
  doi          = {10.1007/S11265-006-7281-3},
  timestamp    = {Wed, 01 Sep 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SaberiniaCST06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SalminenKHRLK06,
  author       = {Erno Salminen and
                  Tero Kangas and
                  Timo D. H{\"{a}}m{\"{a}}l{\"{a}}inen and
                  Jouni Riihim{\"{a}}ki and
                  Vesa Lahtinen and
                  Kimmo Kuusilinna},
  title        = {{HIBI} Communication Network for System-on-Chip},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {185--205},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7270-6},
  doi          = {10.1007/S11265-006-7270-6},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SalminenKHRLK06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SchulteGJMMV06,
  author       = {Michael J. Schulte and
                  John Glossner and
                  Sanjay Jinturkar and
                  Mayan Moudgill and
                  Suman Mamidi and
                  Stamatis Vassiliadis},
  title        = {A Low-Power Multithreaded Processor for Software Defined Radio},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {143--159},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7267-1},
  doi          = {10.1007/S11265-006-7267-1},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SchulteGJMMV06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/TakalaP06,
  author       = {Jarmo Takala and
                  Konsta Punkka},
  title        = {Scalable {FFT} Processors and Pipelined Butterfly Units},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {113--123},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7265-3},
  doi          = {10.1007/S11265-006-7265-3},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/TakalaP06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/TeichB06,
  author       = {J{\"{u}}rgen Teich and
                  Shuvra S. Bhattacharyya},
  title        = {Analysis of Dataflow Programs with Interval-limited Data-rates},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {2-3},
  pages        = {247--258},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7274-2},
  doi          = {10.1007/S11265-006-7274-2},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/TeichB06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/TiuraniemiSRO06,
  author       = {Sakari Tiuraniemi and
                  Lucian{-}Vasile Stoica and
                  Alberto Rabbachin and
                  Ian J. Oppermann},
  title        = {A {VLSI} Implementation of Low Power, Low Data Rate {UWB} Transceiver
                  for Location and Tracking Applications},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {1},
  pages        = {43--58},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7279-x},
  doi          = {10.1007/S11265-006-7279-X},
  timestamp    = {Tue, 30 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsisp/TiuraniemiSRO06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/YeungC06,
  author       = {On Wa Yeung and
                  Keith M. Chugg},
  title        = {An Iterative Algorithm and Low Complexity Hardware Architecture for
                  Fast Acquisition of Long {PN} Codes in {UWB} Systems},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {1},
  pages        = {25--42},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7278-y},
  doi          = {10.1007/S11265-006-7278-Y},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/YeungC06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ZhangGWW06,
  author       = {Honglei Zhang and
                  Dennis Goeckel and
                  Shuangqing Wei and
                  Moe Z. Win},
  title        = {Rapid Hybrid Acquisition of Ultra-Wideband Signals},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {43},
  number       = {1},
  pages        = {7--23},
  year         = {2006},
  url          = {https://doi.org/10.1007/s11265-006-7277-z},
  doi          = {10.1007/S11265-006-7277-Z},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ZhangGWW06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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