Search dblp for Publications

export results for "toc:db/conf/coolchips/coolchips2019.bht:"

 download as .bib file

@inproceedings{DBLP:conf/coolchips/0001CKKK19,
  author       = {Masayuki Sato and
                  Yongcheng Chen and
                  Haruya Kikuchi and
                  Kazuhiko Komatsu and
                  Hiroaki Kobayashi},
  title        = {Perceptron-based Cache Bypassing for Way-Adaptable Caches},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721331},
  doi          = {10.1109/COOLCHIPS.2019.8721331},
  timestamp    = {Fri, 09 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/0001CKKK19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/AgungAET19,
  author       = {Mulya Agung and
                  Muhammad Alfian Amrizal and
                  Ryusuke Egawa and
                  Hiroyuki Takizawa},
  title        = {The Impacts of Locality and Memory Congestion-aware Thread Mapping
                  on Energy Consumption of Modern {NUMA} Systems},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721346},
  doi          = {10.1109/COOLCHIPS.2019.8721346},
  timestamp    = {Mon, 26 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/AgungAET19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/GianelliINGT19,
  author       = {Alberto Gianelli and
                  Nick Iliev and
                  Shamma Nasrin and
                  Mariagrazia Graziano and
                  Amit Ranjan Trivedi},
  title        = {Low Power Speaker Identification using Look Up-free Gaussian Mixture
                  Model in {CMOS}},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721354},
  doi          = {10.1109/COOLCHIPS.2019.8721354},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/GianelliINGT19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/GollapudiYG19,
  author       = {Ravi Theja Gollapudi and
                  Gokturk Yuksek and
                  Kanad Ghose},
  title        = {Cache-Aware Dynamic Classification and Scheduling for Linux},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721355},
  doi          = {10.1109/COOLCHIPS.2019.8721355},
  timestamp    = {Tue, 04 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/GollapudiYG19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/ItsuboTM19,
  author       = {Tomoya Itsubo and
                  Mineto Tsukada and
                  Hiroki Matsutani},
  title        = {Performance and Cost Evaluations of Online Sequential Learning and
                  Unsupervised Anomaly Detection Core},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721337},
  doi          = {10.1109/COOLCHIPS.2019.8721337},
  timestamp    = {Tue, 04 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/ItsuboTM19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/NakamuraOKOONIS19,
  author       = {Ken Nakamura and
                  Yuya Omori and
                  Daisuke Kobayashi and
                  Tatsuya Osawa and
                  Takayuki Onishi and
                  Koyo Nitta and
                  Hiroe Iwasaki and
                  Atsushi Shimizu},
  title        = {Low Delay 4K 120fps {HEVC} Decoder with Parallel Processing Architecture},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721335},
  doi          = {10.1109/COOLCHIPS.2019.8721335},
  timestamp    = {Tue, 04 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/NakamuraOKOONIS19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/OgawaIIVCWSOG19,
  author       = {Eri Ogawa and
                  Kazuaki Ishizaki and
                  Hiroshi Inoue and
                  Swagath Venkataramani and
                  Jungwook Choi and
                  Wei Wang and
                  Vijayalakshmi Srinivasan and
                  Moriyoshi Ohara and
                  Kailash Gopalakrishnan},
  title        = {A Compiler for Deep Neural Network Accelerators to Generate Optimized
                  Code for a Wide Range of Data Parameters from a Hand-crafted Computation
                  Kernel},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721357},
  doi          = {10.1109/COOLCHIPS.2019.8721357},
  timestamp    = {Thu, 23 Dec 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/coolchips/OgawaIIVCWSOG19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/SasakiMMD19,
  author       = {Shinichi Sasaki and
                  Asuka Maki and
                  Daisuke Miyashita and
                  Jun Deguchi},
  title        = {Post Training Weight Compression with Distribution-based Filter-wise
                  Quantization Step},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721356},
  doi          = {10.1109/COOLCHIPS.2019.8721356},
  timestamp    = {Tue, 04 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/SasakiMMD19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/ShirotaSK19,
  author       = {Yusuke Shirota and
                  Satoshi Shirai and
                  Tatsunori Kanai},
  title        = {Hybrid Access in Storage-class Memory-aware Low Power Virtual Memory
                  System},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721344},
  doi          = {10.1109/COOLCHIPS.2019.8721344},
  timestamp    = {Tue, 04 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/ShirotaSK19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/TanabeKSM19,
  author       = {Ken Tanabe and
                  Hiroshi Kubota and
                  Akihide Sai and
                  Nobu Matsumoto},
  title        = {Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel
                  Resolution LiDAR},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721340},
  doi          = {10.1109/COOLCHIPS.2019.8721340},
  timestamp    = {Tue, 04 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/TanabeKSM19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/TanakaYMH19,
  author       = {Kyosuke Tanaka and
                  Hayato Yamaki and
                  Shinobu Miwa and
                  Hiroki Honda},
  title        = {Multi-Level Packet Processing Caches},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721336},
  doi          = {10.1109/COOLCHIPS.2019.8721336},
  timestamp    = {Tue, 04 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/TanakaYMH19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/TokusashiMA19,
  author       = {Yuta Tokusashi and
                  Hiroki Matsutani and
                  Hideharu Amano},
  title        = {Key-value Store Chip Design for Low Power Consumption},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721352},
  doi          = {10.1109/COOLCHIPS.2019.8721352},
  timestamp    = {Tue, 04 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/TokusashiMA19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/WittigHMF19,
  author       = {Robert Wittig and
                  Mattis Hasler and
                  Emil Mat{\'{u}}s and
                  Gerhard P. Fettweis},
  title        = {Statistical Access Interval Prediction for Tightly Coupled Memory
                  Systems},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721304},
  doi          = {10.1109/COOLCHIPS.2019.8721304},
  timestamp    = {Tue, 04 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/WittigHMF19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/YamauchiMA19,
  author       = {Yugo Yamauchi and
                  Kazusa Musha and
                  Hideharu Amano},
  title        = {Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud},
  booktitle    = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/CoolChips.2019.8721333},
  doi          = {10.1109/COOLCHIPS.2019.8721333},
  timestamp    = {Tue, 04 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/YamauchiMA19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/coolchips/2019,
  title        = {{IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2019, Yokohama, Japan, April 17-19, 2019},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://ieeexplore.ieee.org/xpl/conhome/8713395/proceeding},
  isbn         = {978-1-7281-1749-2},
  timestamp    = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/coolchips/2019.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.