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@inproceedings{DBLP:conf/fpga/Ababei09,
author = {Cristinel Ababei},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Parallel placement for FPGAs revisited},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {280},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508186},
doi = {10.1145/1508128.1508186},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Ababei09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AbdallahEA09,
author = {Mohammed A. S. Abdallah and
Omar S. Elkeelany and
Ali T. Alouani},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Simultaneous multi-channel data acquisition with variable sampling
frequencies using a scalable adaptive synchronous controller},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {281},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508188},
doi = {10.1145/1508128.1508188},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/AbdallahEA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Anderson09,
author = {Jason Helge Anderson},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Emerging application domains: research challenges and opportunities
for FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {1--2},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508129},
doi = {10.1145/1508128.1508129},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Anderson09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BeattyAK09,
author = {Timothy F. Beatty and
Eric E. Aubanel and
Kenneth B. Kent},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Customizable bit-width in an OpenMP-based circuit design tool},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {278},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508181},
doi = {10.1145/1508128.1508181},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/BeattyAK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Bittner09,
author = {Ray Bittner},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Bus mastering {PCI} express in an {FPGA}},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {273--276},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508176},
doi = {10.1145/1508128.1508176},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Bittner09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BrownBGR09,
author = {Michael Brown and
Cyrus Bazeghi and
Matthew R. Guthaus and
Jose Renau},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Measuring and modeling variabilityusing low-cost FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {286},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508204},
doi = {10.1145/1508128.1508204},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/BrownBGR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CarverPF09,
author = {Jeffrey M. Carver and
Richard Neil Pittman and
Alessandro Forin},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Automatic bus macro placement for partially reconfigurable {FPGA}
designs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {269--272},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508175},
doi = {10.1145/1508128.1508175},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/CarverPF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CevreroAPBLIS09,
author = {Alessandro Cevrero and
Panagiotis Athanasopoulos and
Hadi Parandeh{-}Afshar and
Philip Brisk and
Yusuf Leblebici and
Paolo Ienne and
Maurizio Skerlj},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {3D configuration caching for 2D FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {286},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508205},
doi = {10.1145/1508128.1508205},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/CevreroAPBLIS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChauLHCYPCW09,
author = {Thomas C. P. Chau and
Philip Heng Wai Leong and
Sam M. H. Ho and
Brian P. W. Chan and
Steve C. L. Yuen and
Kong{-}Pang Pun and
Oliver C. S. Choy and
Xinan Wang},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A comparison of via-programmable gate array logic cell circuits},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {53--62},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508137},
doi = {10.1145/1508128.1508137},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChauLHCYPCW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Chaudhuri09,
author = {Sumanta Chaudhuri},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Diagonal tracks in FPGAs: a performance evaluation},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {245--248},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508167},
doi = {10.1145/1508128.1508167},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Chaudhuri09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChenTCTFDC09,
author = {Deming Chen and
Russell Tessier and
Kaustav Banerjee and
Mojy C. Chian and
Andr{\'{e}} DeHon and
Shinobu Fujita and
James Hutchby and
Steve Trimberger},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {{CMOS} vs Nano: comrades or rivals?},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {121--122},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508147},
doi = {10.1145/1508128.1508147},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChenTCTFDC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChoMOK09,
author = {Junguk Cho and
Shahnam Mirzaei and
Jason Oberg and
Ryan Kastner},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Fpga-based face detection system using Haar classifiers},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {103--112},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508144},
doi = {10.1145/1508128.1508144},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ChoMOK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChongP09,
author = {Yee Jern Chong and
Sri Parameswaran},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Flexible multi-mode embedded floating-point unit for field programmable
gate arrays},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {171--180},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508155},
doi = {10.1145/1508128.1508155},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ChongP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CongGH09,
author = {Jason Cong and
Karthik Gururaj and
Guoling Han},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Synthesis of reconfigurable high-performance multicore systems},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {201--208},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508159},
doi = {10.1145/1508128.1508159},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/CongGH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CongGLLZZZ09,
author = {Jason Cong and
Karthik Gururaj and
Bin Liu and
Chunyue Liu and
Yi Zou and
Zhiru Zhang and
Sheng Zhou},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Revisiting bitwidth optimizations},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {278},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508182},
doi = {10.1145/1508128.1508182},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/CongGLLZZZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DemertziDHGW09,
author = {Melina Demertzi and
Pedro C. Diniz and
Mary W. Hall and
Anna C. Gilbert and
Yi Wang},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Computation reuse in domain-specific optimization of signal recognition},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {281},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508190},
doi = {10.1145/1508128.1508190},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DemertziDHGW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DemirsoyL09,
author = {S{\"{u}}leyman Sirri Demirsoy and
Martin Langhammer},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Cholesky decomposition using fused datapath synthesis},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {241--244},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508166},
doi = {10.1145/1508128.1508166},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DemirsoyL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DittmannWM09,
author = {Florian Dittmann and
Elmar Weber and
Norma Montealegre},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Implementation of the reconfiguration port scheduling on the erlangen
slot machine},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {282},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508192},
doi = {10.1145/1508128.1508192},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DittmannWM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DongCC09,
author = {Chen Dong and
Scott Chilstedt and
Deming Chen},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {{FPCNA:} a field programmable carbon nanotube array},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {161--170},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508154},
doi = {10.1145/1508128.1508154},
timestamp = {Mon, 27 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/DongCC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FaviC09,
author = {Claudio Favi and
Edoardo Charbon},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A 17ps time-to-digital converter implemented in 65nm {FPGA} technology},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {113--120},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508145},
doi = {10.1145/1508128.1508145},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FaviC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FrancisM09,
author = {Rosemary M. Francis and
Simon W. Moore},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {FPGAs with time-division multiplexed wiring: an architectural exploration
and area analysis},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {285},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508199},
doi = {10.1145/1508128.1508199},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FrancisM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FriedmanCEYEH09,
author = {Stephen Friedman and
Allan Carroll and
Brian Van Essen and
Benjamin Ylvisaker and
Carl Ebeling and
Scott Hauck},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {{SPR:} an architecture-adaptive {CGRA} mapping tool},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {191--200},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508158},
doi = {10.1145/1508128.1508158},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FriedmanCEYEH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GulatiKL09,
author = {Kanupriya Gulati and
Sunil P. Khatri and
Peng Li},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Closed-loop modeling of power and temperature profiles of FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {287},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508207},
doi = {10.1145/1508128.1508207},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/GulatiKL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HaselmanMLHMD09,
author = {Michael Haselman and
Robert Miyaoka and
Thomas K. Lewellen and
Scott Hauck and
Wendy McDougald and
Don Dewitt},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {FPGA-based front-end electronics for positron emission tomography},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {93--102},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508143},
doi = {10.1145/1508128.1508143},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/HaselmanMLHMD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HoL09,
author = {Johnny Tsung Lin Ho and
Guy G. Lemieux},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {PERG-Rx: a hardware pattern-matching engine supporting limited regular
expressions},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {257--260},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508171},
doi = {10.1145/1508128.1508171},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HoL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JangWJCCMB09,
author = {Stephen Jang and
Dennis Wu and
Mark Jarvin and
Billy Chan and
Kevin Chung and
Alan Mishchenko and
Robert K. Brayton},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {SmartOpt: an industrial strength framework for logic synthesis},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {237--240},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508165},
doi = {10.1145/1508128.1508165},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JangWJCCMB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JiangP09,
author = {Weirong Jiang and
Viktor K. Prasanna},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Large-scale wire-speed packet classification on FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {219--228},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508162},
doi = {10.1145/1508128.1508162},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JiangP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JinKPJ09,
author = {Seunghun Jin and
Dongkyun Kim and
Thien Cong Pham and
Jae Wook Jeon},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {{FPGA} implementation of real-time skin color detection with mean-based
surface flattening},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {283},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508194},
doi = {10.1145/1508128.1508194},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JinKPJ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KasapBL09,
author = {Server Kasap and
Khaled Benkrid and
Ying Liu},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A high performance fpga-based implementation of position specific
iterated blast},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {249--252},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508169},
doi = {10.1145/1508128.1508169},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KasapBL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KenningsVKPF09,
author = {Andrew A. Kennings and
Kristofer Vorwerk and
Arun Kundu and
Val Pevzner and
Andy Fox},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {{FPGA} technology mapping with encoded libraries andstaged priority
cuts},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {143--150},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508151},
doi = {10.1145/1508128.1508151},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KenningsVKPF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KochBT09,
author = {Dirk Koch and
Christian Beckhoff and
J{\"{u}}rgen Teich},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A communication architecture for complex runtime reconfigurable systems
and its implementation on spartan-3 FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {253--256},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508170},
doi = {10.1145/1508128.1508170},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KochBT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LeRB09,
author = {Roto Le and
Sherief Reda and
R. Iris Bahar},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {High-performance, cost-effective heterogeneous 3D {FPGA} architectures},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {286},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508203},
doi = {10.1145/1508128.1508203},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LeRB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LeiQP09,
author = {Lei Chen and
Zhiquan Zhang and
Zhiping Wen},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A novel {BIST} approach for testing input/output buffers in FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {285},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508200},
doi = {10.1145/1508128.1508200},
timestamp = {Wed, 06 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LeiQP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LewisACVLLP09,
author = {David M. Lewis and
Elias Ahmed and
David Cashman and
Tim Vanderhoek and
Christopher Lane and
Andy Lee and
Philip Pan},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Architectural enhancements in Stratix-III\({}^{\mbox{TM}}\) and Stratix-IV\({}^{\mbox{TM}}\)},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {33--42},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508135},
doi = {10.1145/1508128.1508135},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LewisACVLLP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LiH09,
author = {Xinyu Li and
Omar Hammami},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Small scale multiprocessor soft {IP} {(SSM} {IP):} single {FPGA} chip
area and performance evaluation},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {278},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508180},
doi = {10.1145/1508128.1508180},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LiH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LinR09,
author = {Edward C. Lin and
Rob A. Rutenbar},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A multi-fpga 10x-real-time high-speed search engine for a 5000-word
vocabulary speech recognizer},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {83--92},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508141},
doi = {10.1145/1508128.1508141},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LinR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LingBZS09,
author = {Andrew C. Ling and
Stephen Dean Brown and
Jianwen Zhu and
Sean Safarpour},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Towards automated ECOs in FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {3--12},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508131},
doi = {10.1145/1508128.1508131},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LingBZS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LingOBQCWZSMGMDG09,
author = {Liu Ling and
Neal Oliver and
Bhushan Chitlur and
Qigang Wang and
Alvin Chen and
Wenbo Shen and
Zhihong Yu and
Arthur Sheiman and
Ian McCallum and
Joseph Grecco and
Henry Mitchel and
Dong Liu and
Prabhat Gupta},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {High-performance, energy-efficient platforms using in-socket {FPGA}
accelerators},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {261--264},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508172},
doi = {10.1145/1508128.1508172},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LingOBQCWZSMGMDG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LuuKJCYFR09,
author = {Jason Luu and
Ian Kuon and
Peter Jamieson and
Ted Campbell and
Andy Gean Ye and
Wei Mark Fang and
Jonathan Rose},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {{VPR} 5.0: {FPGA} cad and architecture exploration tools with single-driver
routing, heterogeneity and process scaling},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {133--142},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508150},
doi = {10.1145/1508128.1508150},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/LuuKJCYFR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LyC09,
author = {Daniel Le Ly and
Paul Chow},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A high-performance {FPGA} architecture for restricted boltzmann machines},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {73--82},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508140},
doi = {10.1145/1508128.1508140},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LyC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MaitiS09,
author = {Abhranil Maiti and
Patrick Schaumont},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Impact and compensation of correlated process variation on ring oscillator
based puf},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {285},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508201},
doi = {10.1145/1508128.1508201},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/MaitiS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MarksP09,
author = {Paul E. Marks and
Cameron D. Patterson},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Data streaming and simd support for the microblaze architecture},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {277},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508179},
doi = {10.1145/1508128.1508179},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MarksP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MishchenkoBJJ09,
author = {Alan Mishchenko and
Robert K. Brayton and
Jie{-}Hong Roland Jiang and
Stephen Jang},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Scalable don't-care-based logic optimization and resynthesis},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {151--160},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508152},
doi = {10.1145/1508128.1508152},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MishchenkoBJJ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MittalZB09,
author = {Gaurav Mittal and
David Zaretsky and
Prithviraj Banerjee},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Streaming implementation of a sequential decompression algorithm on
an {FPGA}},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {283},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508195},
doi = {10.1145/1508128.1508195},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MittalZB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/OstadzadehMSB09,
author = {Sayyed Arash Ostadzadeh and
Roel Meeuws and
Kamana Sigdel and
Koen Bertels},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A clustering framework for task partitioning based on function-level
data usage analysis},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {279},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508183},
doi = {10.1145/1508128.1508183},
timestamp = {Thu, 09 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/OstadzadehMSB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PottathuparambilS09,
author = {Robin Pottathuparambil and
Ron Sass},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A parallel/vectorized double-precision exponential core to accelerate
computational science applications},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {285},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508198},
doi = {10.1145/1508128.1508198},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/PottathuparambilS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PusK09,
author = {Viktor Pus and
Jan Korenek},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Fast and scalable packet classification using perfect hash functions},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {229--236},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508163},
doi = {10.1145/1508128.1508163},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/PusK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PutnamEBDMSSW09,
author = {Andrew Putnam and
Susan J. Eggers and
Dave Bennett and
Eric Dellinger and
Jeff Mason and
Henry Styles and
Prasanna Sundararajan and
Ralph Wittig},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Performance and power of cache-based reconfigurable computing},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {281},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508189},
doi = {10.1145/1508128.1508189},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/PutnamEBDMSSW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RubinD09,
author = {Raphael Rubin and
Andr{\'{e}} DeHon},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Choose-your-own-adventure routing: lightweight load-time defect avoidance},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {23--32},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508133},
doi = {10.1145/1508128.1508133},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RubinD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SheldonV09,
author = {David Sheldon and
Frank Vahid},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Making good points: application-specific pareto-point generation for
design space exploration using statistical methods},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {123--132},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508149},
doi = {10.1145/1508128.1508149},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SheldonV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SmithWD09,
author = {Alastair M. Smith and
Steven J. E. Wilton and
Joydip Das},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Wirelength modeling for homogeneous and heterogeneous {FPGA} architectural
development},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {181--190},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508156},
doi = {10.1145/1508128.1508156},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SmithWD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SunLGWLL09,
author = {Yanteng Sun and
Peng Li and
Guochang Gu and
Yuan Wen and
Yuan Liu and
Dong Liu},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {HMMer acceleration using systolic array based reconfigurable architecture},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {282},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508193},
doi = {10.1145/1508128.1508193},
timestamp = {Mon, 31 Oct 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SunLGWLL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TeehanLG09,
author = {Paul Teehan and
Guy G. Lemieux and
Mark R. Greenstreet},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect
in 65nm FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {43--52},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508136},
doi = {10.1145/1508128.1508136},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TeehanLG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ThomasHL09,
author = {David B. Thomas and
Lee W. Howes and
Wayne Luk},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A comparison of CPUs, GPUs, FPGAs, and massively parallel processor
arrays for random number generation},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {63--72},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508139},
doi = {10.1145/1508128.1508139},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ThomasHL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TumeoPPFS09,
author = {Antonino Tumeo and
Christian Pilato and
Gianluca Palermo and
Fabrizio Ferrandi and
Donatella Sciuto},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {{HW/SW} methodologies for synchronization in {FPGA} multiprocessors},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {265--268},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508174},
doi = {10.1145/1508128.1508174},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TumeoPPFS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/VavourasPP09,
author = {Michalis Vavouras and
Kyprianos Papadimitriou and
Ioannis Papaefstathiou},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Implementation of a genetic algorithm on a virtex-ii pro {FPGA}},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {287},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508206},
doi = {10.1145/1508128.1508206},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/VavourasPP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangCWKSCSSDSW09,
author = {Perry H. Wang and
Jamison D. Collins and
Christopher T. Weaver and
Belliappa Kuttanna and
Shahram Salamian and
Gautham N. Chinya and
Ethan Schuchman and
Oliver Schilling and
Thorsten Doil and
Sebastian Steibl and
Hong Wang},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Intel{\textregistered} atom\({}^{\mbox{TM}}\) processor core made
FPGA-synthesizable},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {209--218},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508160},
doi = {10.1145/1508128.1508160},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WangCWKSCSSDSW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangGA09,
author = {Qiang Wang and
Subodh Gupta and
Jason Helge Anderson},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Clock power reduction for virtex-5 FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {13--22},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508132},
doi = {10.1145/1508128.1508132},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WangGA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangSZJL09,
author = {Zuo Wang and
Feng Shi and
Qi Zuo and
Weixing Ji and
Mengxiao Liu},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {N-port memory mapping for LUT-based FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {279},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508185},
doi = {10.1145/1508128.1508185},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WangSZJL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YamawakiI09,
author = {Akira Yamawaki and
Masahiko Iwane},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {An intermediate hardware model with load/store unit for {C} to {FPGA}},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {279},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508184},
doi = {10.1145/1508128.1508184},
timestamp = {Thu, 29 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/YamawakiI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YanWC09,
author = {Like Yan and
Gang Wang and
Tianzhou Chen},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {The input-aware dynamic adaptation of area and performance for reconfigurable
accelerator},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {281},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508191},
doi = {10.1145/1508128.1508191},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YanWC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YiannacourasSR09,
author = {Peter Yiannacouras and
J. Gregory Steffan and
Jonathan Rose},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Soft vector processors vs {FPGA} custom hardware: measuring and reducing
the gap},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {277},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508178},
doi = {10.1145/1508128.1508178},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YiannacourasSR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YuL09,
author = {JIanDe Yu and
Jinmei Lai},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {A novel minloop {SB} design to improve {FPGA} routability},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {286},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508202},
doi = {10.1145/1508128.1508202},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YuL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZhangGSW09,
author = {Bowei Zhang and
Guochang Gu and
Lin Sun and
Yanxia Wu},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {32-bit floating-point {FPGA} gaussian elimination},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {283--284},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508196},
doi = {10.1145/1508128.1508196},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ZhangGSW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpga/2009,
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128},
doi = {10.1145/1508128},
isbn = {978-1-60558-410-2},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/2009.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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