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@article{DBLP:journals/jsa/AhmadAA10,
author = {Balal Ahmad and
Ali Ahmadinia and
Tughrul Arslan},
title = {High level modeling and automated generation of heterogeneous SoC
architectures with optimized custom reconfigurable cores and on-chip
communication media},
journal = {J. Syst. Archit.},
volume = {56},
number = {11},
pages = {597--615},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.014},
doi = {10.1016/J.SYSARC.2010.07.014},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/AhmadAA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/AhmadKAR10,
author = {Afandi Ahmad and
Benjamin Krill and
Abbes Amira and
Hassan Rabah},
title = {Efficient architectures for 3D {HWT} using dynamic partial reconfiguration},
journal = {J. Syst. Archit.},
volume = {56},
number = {8},
pages = {305--316},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.02.001},
doi = {10.1016/J.SYSARC.2010.02.001},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/AhmadKAR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/AliM10,
author = {Usman Ali and
Mohammad Bilal Malik},
title = {Hardware/software co-design of a real-time kernel based tracking system},
journal = {J. Syst. Archit.},
volume = {56},
number = {8},
pages = {317--326},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.04.008},
doi = {10.1016/J.SYSARC.2010.04.008},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/AliM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/ArenoET10,
author = {Matthew Areno and
Brandon Eames and
Joshua Templin},
title = {A Force-Directed Scheduling based architecture generation algorithm
and design tool for FPGAs},
journal = {J. Syst. Archit.},
volume = {56},
number = {2-3},
pages = {124--135},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.01.001},
doi = {10.1016/J.SYSARC.2010.01.001},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/ArenoET10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/AsaduzzamanSR10,
author = {Abu Asaduzzaman and
Fadi N. Sibai and
Manira Rani},
title = {Improving cache locking performance of modern embedded systems via
the addition of a miss table at the {L2} cache level},
journal = {J. Syst. Archit.},
volume = {56},
number = {4-6},
pages = {151--162},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.02.002},
doi = {10.1016/J.SYSARC.2010.02.002},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/AsaduzzamanSR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/AsherH10,
author = {Yosi Ben{-}Asher and
Jawad Haj{-}Yihia},
title = {Computing the correct Increment of Induction Pointers with application
to loop unrolling},
journal = {J. Syst. Archit.},
volume = {56},
number = {12},
pages = {654--666},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.09.006},
doi = {10.1016/J.SYSARC.2010.09.006},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/AsherH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/AtocheRS10,
author = {Alejandro Castillo Atoche and
Deni Torres Rom{\'{a}}n and
Yuriy Shkvarko},
title = {Towards real time implementation of reconstructive signal processing
algorithms using systolic arrays coprocessors},
journal = {J. Syst. Archit.},
volume = {56},
number = {8},
pages = {327--339},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.05.004},
doi = {10.1016/J.SYSARC.2010.05.004},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/AtocheRS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/BakloutiAMDA10,
author = {Mouna Baklouti and
Yassine Aydi and
Philippe Marquet and
Jean{-}Luc Dekeyser and
Mohamed Abid},
title = {Scalable mpNoC for massively parallel systems - Design and implementation
on {FPGA}},
journal = {J. Syst. Archit.},
volume = {56},
number = {7},
pages = {278--292},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.04.001},
doi = {10.1016/J.SYSARC.2010.04.001},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/BakloutiAMDA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/Ben-AsherRS10,
author = {Yosi Ben{-}Asher and
Nadav Rotem and
Eddie Shochat},
title = {Finding the best compromise in compiling compound loops to Verilog},
journal = {J. Syst. Archit.},
volume = {56},
number = {9},
pages = {474--486},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.001},
doi = {10.1016/J.SYSARC.2010.07.001},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/Ben-AsherRS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/BeuxBNBLP10,
author = {S{\'{e}}bastien Le Beux and
Guy Bois and
Gabriela Nicolescu and
Youcef Bouchebaba and
Michel Langevin and
Pierre G. Paulin},
title = {Combining mapping and partitioning exploration for NoC-based embedded
systems},
journal = {J. Syst. Archit.},
volume = {56},
number = {7},
pages = {223--232},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.03.005},
doi = {10.1016/J.SYSARC.2010.03.005},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/BeuxBNBLP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/BravoS10,
author = {Ignacio Bravo Mu{\~{n}}oz and
Marco D. Santambrogio},
title = {Design flows and system architectures for adaptive computing on reconfigurable
platforms},
journal = {J. Syst. Archit.},
volume = {56},
number = {11},
pages = {543--544},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.10.007},
doi = {10.1016/J.SYSARC.2010.10.007},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/BravoS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/BrizuelaIF10,
author = {Jose Brizuela and
Alberto Iba{\~{n}}ez and
Carlos Fritsch},
title = {{NDE} system for railway wheel inspection in a standard {FPGA}},
journal = {J. Syst. Archit.},
volume = {56},
number = {11},
pages = {616--622},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.015},
doi = {10.1016/J.SYSARC.2010.07.015},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/BrizuelaIF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/BrunelliGRN10,
author = {Claudio Brunelli and
Fabio Garzia and
Davide Rossi and
Jari Nurmi},
title = {A coarse-grain reconfigurable architecture for multimedia applications
supporting subword and floating-point calculations},
journal = {J. Syst. Archit.},
volume = {56},
number = {1},
pages = {38--47},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.11.003},
doi = {10.1016/J.SYSARC.2009.11.003},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/BrunelliGRN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/ChenHCKC10,
author = {Da{-}Ren Chen and
Chiun{-}Chieh Hsu and
You{-}Shyang Chen and
Chi{-}Jung Kuo and
Lin{-}Chih Chen},
title = {Transition-aware {DVS} algorithm for real-time systems using tree
structure analysis},
journal = {J. Syst. Archit.},
volume = {56},
number = {8},
pages = {352--367},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.05.003},
doi = {10.1016/J.SYSARC.2010.05.003},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/ChenHCKC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/ClaverAALC10,
author = {Jos{\'{e}} M. Claver and
P. Agust{\'{\i}} and
Miguel Arevalillo{-}Herr{\'{a}}ez and
Germ{\'{a}}n Le{\'{o}}n and
Manel Canseco},
title = {A reconfigurable platform for evaluating the performance of QoS networks},
journal = {J. Syst. Archit.},
volume = {56},
number = {4-6},
pages = {191--207},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.03.004},
doi = {10.1016/J.SYSARC.2010.03.004},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/ClaverAALC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/DongZHYL10,
author = {Jianbo Dong and
Lei Zhang and
Yinhe Han and
Guihai Yan and
Xiaowei Li},
title = {Performance-asymmetry-aware scheduling for Chip Multiprocessors with
static core coupling},
journal = {J. Syst. Archit.},
volume = {56},
number = {10},
pages = {534--542},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.09.003},
doi = {10.1016/J.SYSARC.2010.09.003},
timestamp = {Tue, 23 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/DongZHYL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/DykenD10,
author = {Jason Van Dyken and
Jos{\'{e}} G. Delgado{-}Frias},
title = {{FPGA} schemes for minimizing the power-throughput trade-off in executing
the Advanced Encryption Standard algorithm},
journal = {J. Syst. Archit.},
volume = {56},
number = {2-3},
pages = {116--123},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.12.001},
doi = {10.1016/J.SYSARC.2009.12.001},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/DykenD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/FazlaliSZB10,
author = {Mahmood Fazlali and
Mojtaba Sabeghi and
Ali Zakerolhosseini and
Koen Bertels},
title = {Efficient task scheduling for runtime reconfigurable systems},
journal = {J. Syst. Archit.},
volume = {56},
number = {11},
pages = {623--632},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.016},
doi = {10.1016/J.SYSARC.2010.07.016},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/FazlaliSZB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/FloresAA10,
author = {Antonio Flores and
Manuel E. Acacio and
Juan L. Arag{\'{o}}n},
title = {Exploiting address compression and heterogeneous interconnects for
efficient message management in tiled CMPs},
journal = {J. Syst. Archit.},
volume = {56},
number = {9},
pages = {429--441},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.05.006},
doi = {10.1016/J.SYSARC.2010.05.006},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/FloresAA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/FuWWY10,
author = {Chen Fu and
Dongxin Wen and
Xiaoqun Wang and
Xiao{-}Zong Yang},
title = {Hardware transactional memory: {A} high performance parallel programming
model},
journal = {J. Syst. Archit.},
volume = {56},
number = {8},
pages = {384--391},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.06.006},
doi = {10.1016/J.SYSARC.2010.06.006},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/FuWWY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/Gonzalez-AlberquillaCPT10,
author = {Rodr{\'{\i}}go Gonz{\'{a}}lez{-}Alberquilla and
Fernando Castro and
Luis Pi{\~{n}}uel and
Francisco Tirado},
title = {Stack filter: Reducing {L1} data cache power consumption},
journal = {J. Syst. Archit.},
volume = {56},
number = {12},
pages = {685--695},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.10.002},
doi = {10.1016/J.SYSARC.2010.10.002},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/Gonzalez-AlberquillaCPT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/GregertsenS10,
author = {Kristoffer Nyborg Gregertsen and
Amund Skavhaug},
title = {Implementing the new Ada 2005 timing event and execution time control
features on the {AVR32} architecture},
journal = {J. Syst. Archit.},
volume = {56},
number = {10},
pages = {509--522},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.08.001},
doi = {10.1016/J.SYSARC.2010.08.001},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/GregertsenS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/GuanLQYYL10,
author = {Haibing Guan and
Bo Liu and
Zhengwei Qi and
Yindong Yang and
Hongbo Yang and
Alei Liang},
title = {CoDBT: {A} multi-source dynamic binary translator using hardware-software
collaborative techniques},
journal = {J. Syst. Archit.},
volume = {56},
number = {10},
pages = {500--508},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.008},
doi = {10.1016/J.SYSARC.2010.07.008},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/GuanLQYYL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/GuoP10,
author = {Hui Guo and
Sri Parameswaran},
title = {Shifted gray encoding to reduce instruction memory address bus switching
for low-power embedded systems},
journal = {J. Syst. Archit.},
volume = {56},
number = {4-6},
pages = {180--190},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.03.003},
doi = {10.1016/J.SYSARC.2010.03.003},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/GuoP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/GutierrezTV10,
author = {Roberto Gutierrez and
Vicente Torres{-}Carot and
Javier Valls{-}Coquillat},
title = {FPGA-implementation of atan(Y/X) based on logarithmic transformation
and LUT-based techniques},
journal = {J. Syst. Archit.},
volume = {56},
number = {11},
pages = {588--596},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.013},
doi = {10.1016/J.SYSARC.2010.07.013},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/GutierrezTV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/HuangHS10,
author = {Chun{-}Hsian Huang and
Pao{-}Ann Hsiung and
Jih{-}Sheng Shen},
title = {UML-based hardware/software co-design platform for dynamically partially
reconfigurable network security systems},
journal = {J. Syst. Archit.},
volume = {56},
number = {2-3},
pages = {88--102},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.11.007},
doi = {10.1016/J.SYSARC.2009.11.007},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/HuangHS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/HuangHS10a,
author = {Chun{-}Hsian Huang and
Pao{-}Ann Hsiung and
Jih{-}Sheng Shen},
title = {Model-based platform-specific co-design methodology for dynamically
partially reconfigurable systems with hardware virtualization and
preemption},
journal = {J. Syst. Archit.},
volume = {56},
number = {11},
pages = {545--560},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.007},
doi = {10.1016/J.SYSARC.2010.07.007},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/HuangHS10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/HwangL10,
author = {Yuan{-}Shin Hwang and
Jia{-}Jhe Li},
title = {On reducing load/store latencies of cache accesses},
journal = {J. Syst. Archit.},
volume = {56},
number = {1},
pages = {1--15},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.10.001},
doi = {10.1016/J.SYSARC.2009.10.001},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/HwangL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/ImS10,
author = {Soojun Im and
Dongkun Shin},
title = {ComboFTL: Improving performance and lifespan of {MLC} flash memory
using {SLC} flash buffer},
journal = {J. Syst. Archit.},
volume = {56},
number = {12},
pages = {641--653},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.09.005},
doi = {10.1016/J.SYSARC.2010.09.005},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/ImS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/Kornaros10,
author = {George Kornaros},
title = {A soft multi-core architecture for edge detection and data analysis
of microarray images},
journal = {J. Syst. Archit.},
volume = {56},
number = {1},
pages = {48--62},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.11.004},
doi = {10.1016/J.SYSARC.2009.11.004},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/Kornaros10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/KrastevaTR10,
author = {Yana Esteves Krasteva and
Eduardo de la Torre and
Teresa Riesgo},
title = {Reconfigurable Networks on Chip: DRNoC architecture},
journal = {J. Syst. Archit.},
volume = {56},
number = {7},
pages = {293--302},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.04.003},
doi = {10.1016/J.SYSARC.2010.04.003},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/KrastevaTR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/KuXG10,
author = {Anderson Kuei{-}An Ku and
Jingling Xue and
Yong Guan},
title = {Gather/scatter hardware support for accelerating Fast Fourier Transform},
journal = {J. Syst. Archit.},
volume = {56},
number = {12},
pages = {667--684},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.09.007},
doi = {10.1016/J.SYSARC.2010.09.007},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/KuXG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/KwakJ10,
author = {Jong Wook Kwak and
Young Tae Jeon},
title = {Compressed tag architecture for low-power embedded cache systems},
journal = {J. Syst. Archit.},
volume = {56},
number = {9},
pages = {419--428},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.04.010},
doi = {10.1016/J.SYSARC.2010.04.010},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/KwakJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/LangeM10,
author = {Sebastian Lange and
Martin Middendorf},
title = {Multi-level reconfigurable architectures in the switch model},
journal = {J. Syst. Archit.},
volume = {56},
number = {2-3},
pages = {103--115},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.11.008},
doi = {10.1016/J.SYSARC.2009.11.008},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/LangeM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/LeeS10,
author = {Gyungho Lee and
Yixin Shi},
title = {Erratum to "Access region cache with register guided memory reference
partitioning" [Journal of Systems Architecture 55 {(2009)} 434-445]},
journal = {J. Syst. Archit.},
volume = {56},
number = {1},
pages = {75},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.11.002},
doi = {10.1016/J.SYSARC.2009.11.002},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/LeeS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/LeeYH10,
author = {Ser{-}Hoon Lee and
Yeo{-}Chan Yoon and
Sun{-}Young Hwang},
title = {Communication-aware task assignment algorithm for MPSoC using shared
memory},
journal = {J. Syst. Archit.},
volume = {56},
number = {7},
pages = {233--241},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.03.001},
doi = {10.1016/J.SYSARC.2010.03.001},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/LeeYH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/LiJLSL10,
author = {Tao Li and
Wu Jigang and
Siew Kei Lam and
Thambipillai Srikanthan and
Xicheng Lu},
title = {Selecting profitable custom instructions for reconfigurable processors},
journal = {J. Syst. Archit.},
volume = {56},
number = {8},
pages = {340--351},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.04.004},
doi = {10.1016/J.SYSARC.2010.04.004},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/LiJLSL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/Lotfi-KamranRDAN10,
author = {Pejman Lotfi{-}Kamran and
Amir{-}Mohammad Rahmani and
Masoud Daneshtalab and
Ali Afzali{-}Kusha and
Zainalabedin Navabi},
title = {{EDXY} - {A} low cost congestion-aware routing algorithm for network-on-chips},
journal = {J. Syst. Archit.},
volume = {56},
number = {7},
pages = {256--264},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.05.002},
doi = {10.1016/J.SYSARC.2010.05.002},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/Lotfi-KamranRDAN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/MeunierPR10,
author = {Quentin L. Meunier and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot and
Jean{-}Louis Roch},
title = {Hardware/software support for adaptive work-stealing in on-chip multiprocessor},
journal = {J. Syst. Archit.},
volume = {56},
number = {8},
pages = {392--406},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.06.007},
doi = {10.1016/J.SYSARC.2010.06.007},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/MeunierPR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/MoadeliSVM10,
author = {Mahmoud Moadeli and
Alireza Shahrabi and
Wim Vanderbauwhede and
Partha P. Maji},
title = {An analytical performance model for the Spidergon NoC with virtual
channels},
journal = {J. Syst. Archit.},
volume = {56},
number = {1},
pages = {16--26},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.10.002},
doi = {10.1016/J.SYSARC.2009.10.002},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/MoadeliSVM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/Morales-VelazquezRORC10,
author = {Luis Morales{-}Velazquez and
Ren{\'{e}} de Jes{\'{u}}s Romero{-}Troncoso and
Roque Alfredo Osornio{-}Rios and
Gilberto Herrera Ruiz and
Eduardo Cabal{-}Yepez},
title = {Open-architecture system based on a reconfigurable hardware-software
multi-agent platform for {CNC} machines},
journal = {J. Syst. Archit.},
volume = {56},
number = {9},
pages = {407--418},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.04.009},
doi = {10.1016/J.SYSARC.2010.04.009},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/Morales-VelazquezRORC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/NogueiraP10,
author = {Lu{\'{\i}}s Nogueira and
Lu{\'{\i}}s Miguel Pinho},
title = {A capacity sharing and stealing strategy for open real-time systems},
journal = {J. Syst. Archit.},
volume = {56},
number = {4-6},
pages = {163--179},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.02.003},
doi = {10.1016/J.SYSARC.2010.02.003},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/NogueiraP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/ParkS10,
author = {Hyunchul Park and
Dongkun Shin},
title = {Buffer flush and address mapping scheme for flash memory solid-state
disk},
journal = {J. Syst. Archit.},
volume = {56},
number = {4-6},
pages = {208--220},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.03.006},
doi = {10.1016/J.SYSARC.2010.03.006},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/ParkS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/PedrazaCCBMRCH10,
author = {C{\'{e}}sar Pedraza and
Emilio Castillo and
Javier Castillo and
Jos{\'{e}} Luis Bosque and
Jos{\'{e}} Ignacio Mart{\'{\i}}nez and
Oscar David Robles and
Javier Cano and
Pablo Huerta},
title = {Content-based image retrieval algorithm acceleration in a low-cost
reconfigurable {FPGA} cluster},
journal = {J. Syst. Archit.},
volume = {56},
number = {11},
pages = {633--640},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.017},
doi = {10.1016/J.SYSARC.2010.07.017},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/PedrazaCCBMRCH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/PisupatiB10,
author = {Bhanu Pisupati and
Geoffrey Brown},
title = {Embedded software debugging using virtual filesystem abstractions},
journal = {J. Syst. Archit.},
volume = {56},
number = {10},
pages = {487--499},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.005},
doi = {10.1016/J.SYSARC.2010.07.005},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/PisupatiB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/Pulido10,
author = {Juan Antonio G{\'{o}}mez Pulido},
title = {From systems to networks on chip: {A} promising research area in the
Hardware/Software co-design},
journal = {J. Syst. Archit.},
volume = {56},
number = {7},
pages = {221--222},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.05.001},
doi = {10.1016/J.SYSARC.2010.05.001},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/Pulido10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/Pulido10a,
author = {Juan Antonio G{\'{o}}mez Pulido},
title = {Recent advances in Hardware/Software co-design},
journal = {J. Syst. Archit.},
volume = {56},
number = {8},
pages = {303--304},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.06.008},
doi = {10.1016/J.SYSARC.2010.06.008},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/Pulido10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/RosAG10,
author = {Alberto Ros and
Manuel E. Acacio and
Jos{\'{e}} M. Garc{\'{\i}}a},
title = {A scalable organization for distributed directories},
journal = {J. Syst. Archit.},
volume = {56},
number = {2-3},
pages = {77--87},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.11.006},
doi = {10.1016/J.SYSARC.2009.11.006},
timestamp = {Wed, 31 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/RosAG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/SeoCYK10,
author = {Young{-}Ho Seo and
Hyun{-}Jun Choi and
Ji{-}Sang Yoo and
Dong{-}Wook Kim},
title = {An architecture of a high-speed digital hologram generator based on
{FPGA}},
journal = {J. Syst. Archit.},
volume = {56},
number = {1},
pages = {27--37},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.11.001},
doi = {10.1016/J.SYSARC.2009.11.001},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/SeoCYK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/ShabbirKSMC10,
author = {Ahsan Shabbir and
Akash Kumar and
Sander Stuijk and
Bart Mesman and
Henk Corporaal},
title = {CA-MPSoC: An automated design flow for predictable multi-processor
architectures for multiple applications},
journal = {J. Syst. Archit.},
volume = {56},
number = {7},
pages = {265--277},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.03.007},
doi = {10.1016/J.SYSARC.2010.03.007},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/ShabbirKSMC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/ShinHC10,
author = {Keoncheol Shin and
Hwansoo Han and
Kwang{-}Moo Choe},
title = {Composition-based Cache simulation for structure reorganization},
journal = {J. Syst. Archit.},
volume = {56},
number = {2-3},
pages = {136--149},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.01.002},
doi = {10.1016/J.SYSARC.2010.01.002},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/ShinHC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/SinghSKJ10,
author = {Amit Kumar Singh and
Thambipillai Srikanthan and
Akash Kumar and
Wu Jigang},
title = {Communication-aware heuristics for run-time task mapping on NoC-based
MPSoC platforms},
journal = {J. Syst. Archit.},
volume = {56},
number = {7},
pages = {242--255},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.04.007},
doi = {10.1016/J.SYSARC.2010.04.007},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/SinghSKJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/TangL10,
author = {Minghua Tang and
Xiaola Lin},
title = {Quarter Load Threshold {(QLT)} flow control for wormhole switching
in mesh-based Network-on-Chip},
journal = {J. Syst. Archit.},
volume = {56},
number = {9},
pages = {452--462},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.05.012},
doi = {10.1016/J.SYSARC.2010.05.012},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/TangL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/TomasiBVDV10,
author = {Matteo Tomasi and
Francisco Barranco and
Mauricio Vanegas and
Javier D{\'{\i}}az and
Eduardo Ros Vidal},
title = {Fine grain pipeline architecture for high performance phase-based
optical flow computation},
journal = {J. Syst. Archit.},
volume = {56},
number = {11},
pages = {577--587},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.012},
doi = {10.1016/J.SYSARC.2010.07.012},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/TomasiBVDV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/VanegasTDV10,
author = {Mauricio Vanegas and
Matteo Tomasi and
Javier D{\'{\i}}az and
Eduardo Ros Vidal},
title = {Multi-port abstraction layer for {FPGA} intensive memory exploitation
applications},
journal = {J. Syst. Archit.},
volume = {56},
number = {9},
pages = {442--451},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.05.007},
doi = {10.1016/J.SYSARC.2010.05.007},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/VanegasTDV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/VelascoMFLB10,
author = {Manel Velasco and
Pau Mart{\'{\i}} and
Josep M. Fuertes and
Camilo Lozoya and
Scott A. Brandt},
title = {Experimental evaluation of slack management in real-time control systems:
Coordinated vs. self-triggered approach},
journal = {J. Syst. Archit.},
volume = {56},
number = {1},
pages = {63--74},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2009.11.005},
doi = {10.1016/J.SYSARC.2009.11.005},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/VelascoMFLB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/VoigtBT10,
author = {Sven{-}Ole Voigt and
Malte Baesler and
Thomas Teufel},
title = {Dynamically reconfigurable dataflow architecture for high-performance
digital signal processing},
journal = {J. Syst. Archit.},
volume = {56},
number = {11},
pages = {561--576},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.07.010},
doi = {10.1016/J.SYSARC.2010.07.010},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/VoigtBT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/YaoLGWL10,
author = {Jianguo Yao and
Xue Liu and
Zonghua Gu and
Xiaorui Wang and
Jian Li},
title = {Online adaptive utilization control for real-time embedded multiprocessor
systems},
journal = {J. Syst. Archit.},
volume = {56},
number = {9},
pages = {463--473},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.06.002},
doi = {10.1016/J.SYSARC.2010.06.002},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/YaoLGWL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/YounAPKC10,
author = {Jonghee M. Youn and
Minwook Ahn and
Yunheung Paek and
Jongwung Kim and
Jeonghun Cho},
title = {Two versions of architectures for dynamic implied addressing mode},
journal = {J. Syst. Archit.},
volume = {56},
number = {8},
pages = {368--383},
year = {2010},
url = {https://doi.org/10.1016/j.sysarc.2010.05.014},
doi = {10.1016/J.SYSARC.2010.05.014},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/YounAPKC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/XuZ10,
title = {Specification and verification of dynamic evolution of software architectures},
journal = {J. Syst. Archit.},
volume = {56},
number = {10},
pages = {523--533},
year = {2010},
note = {Withdrawn.},
url = {https://doi.org/10.1016/j.sysarc.2010.08.005},
doi = {10.1016/J.SYSARC.2010.08.005},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/XuZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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