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@article{DBLP:journals/tcad/AcharNZ98,
author = {Ramachandra Achar and
Michel S. Nakhla and
Qi{-}Jun Zhang},
title = {Full-wave analysis of high-speed interconnects using complex frequency
hopping},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {997--1016},
year = {1998},
url = {https://doi.org/10.1109/43.728920},
doi = {10.1109/43.728920},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AcharNZ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertCKMM98,
author = {Charles J. Alpert and
Tony F. Chan and
Andrew B. Kahng and
Igor L. Markov and
Pep Mulet},
title = {Faster minimization of linear wirelength for global placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {1},
pages = {3--13},
year = {1998},
url = {https://doi.org/10.1109/43.673628},
doi = {10.1109/43.673628},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertCKMM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertHK98,
author = {Charles J. Alpert and
Jen{-}Hsin Huang and
Andrew B. Kahng},
title = {Multilevel circuit partitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {8},
pages = {655--667},
year = {1998},
url = {https://doi.org/10.1109/43.712098},
doi = {10.1109/43.712098},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertHK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AnandSK98,
author = {M. B. Anand and
Hideki Shibata and
Masakazu Kakumu},
title = {Multiobjective optimization of {VLSI} interconnect parameters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1252--1261},
year = {1998},
url = {https://doi.org/10.1109/43.736565},
doi = {10.1109/43.736565},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AnandSK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ArtsBE98,
author = {Harm Arts and
Michel R. C. M. Berkelaar and
Koen van Eijk},
title = {Computing observability don't cares efficiently through polarization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {7},
pages = {573--581},
year = {1998},
url = {https://doi.org/10.1109/43.709395},
doi = {10.1109/43.709395},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ArtsBE98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Axelrad98,
author = {Valery Axelrad},
title = {Grid quality and its influence on accuracy and convergence in device
simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {149--157},
year = {1998},
url = {https://doi.org/10.1109/43.681264},
doi = {10.1109/43.681264},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Axelrad98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BalboniCPQS98,
author = {Alessandro Balboni and
Claudio Costi and
Massimo Pellencin and
Andrea Quadrini and
Donatella Sciuto},
title = {Clock skew reduction in {ASIC} logic design: a methodology for clock
tree management},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {4},
pages = {344--356},
year = {1998},
url = {https://doi.org/10.1109/43.703824},
doi = {10.1109/43.703824},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BalboniCPQS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeckS98,
author = {James E. Beck and
Daniel P. Siewiorek},
title = {Automatic configuration of embedded multicomputer systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {84--95},
year = {1998},
url = {https://doi.org/10.1109/43.681259},
doi = {10.1109/43.681259},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeckS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeerelMM98,
author = {Peter A. Beerel and
Chris J. Myers and
Teresa H. Meng},
title = {Covering conditions and algorithms for the synthesis of speed-independent
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {3},
pages = {205--219},
year = {1998},
url = {https://doi.org/10.1109/43.700719},
doi = {10.1109/43.700719},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeerelMM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Beetem98,
author = {John F. Beetem},
title = {Rebel: a clustering algorithm for look-up table FPGA's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {444--451},
year = {1998},
url = {https://doi.org/10.1109/43.703938},
doi = {10.1109/43.703938},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Beetem98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeniniMPM98,
author = {Luca Benini and
Enrico Macii and
Massimo Poncino and
Giovanni De Micheli},
title = {Telescopic units: a new paradigm for performance optimization of {VLSI}
designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {3},
pages = {220--232},
year = {1998},
url = {https://doi.org/10.1109/43.700720},
doi = {10.1109/43.700720},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeniniMPM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeniniVM98,
author = {Luca Benini and
Patrick Vuillod and
Giovanni De Micheli},
title = {Iterative remapping for logic circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {948--964},
year = {1998},
url = {https://doi.org/10.1109/43.728916},
doi = {10.1109/43.728916},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeniniVM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BohmayrBLRS98,
author = {Walter Bohmayr and
Alexander Burenkov and
J{\"{u}}rgen Lorenz and
Heiner Ryssel and
Siegfried Selberherr},
title = {Monte Carlo simulation of silicon amorphization during ion implantation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1236--1243},
year = {1998},
url = {https://doi.org/10.1109/43.736563},
doi = {10.1109/43.736563},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BohmayrBLRS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrandBS98,
author = {Daniel Brand and
Reinaldo A. Bergamaschi and
Leon Stok},
title = {Don't cares in synthesis: theoretical pitfalls and practical solutions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {4},
pages = {285--304},
year = {1998},
url = {https://doi.org/10.1109/43.703819},
doi = {10.1109/43.703819},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrandBS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrasenS98,
author = {Daniel R. Brasen and
Gabriele Saucier},
title = {Using cone structures for circuit partitioning into {FPGA} packages},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {7},
pages = {592--600},
year = {1998},
url = {https://doi.org/10.1109/43.709397},
doi = {10.1109/43.709397},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrasenS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BuiM98,
author = {Thang Nguyen Bui and
Byung Ro Moon},
title = {{GRCA:} a hybrid genetic algorithm for circuit ratio-cut partitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {3},
pages = {193--204},
year = {1998},
url = {https://doi.org/10.1109/43.700718},
doi = {10.1109/43.700718},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BuiM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BurnsF98,
author = {Jeffrey L. Burns and
Jack A. Feldman},
title = {C5M-a control-logic layout synthesis system for high-performance microprocessors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {1},
pages = {14--23},
year = {1998},
url = {https://doi.org/10.1109/43.673629},
doi = {10.1109/43.673629},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BurnsF98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CallandMPRV98,
author = {Pierre{-}Yves Calland and
Anne Mignotte and
Olivier Peyran and
Yves Robert and
Fr{\'{e}}d{\'{e}}ric Vivien},
title = {Retiming DAGs [direct acyclic graph]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1319--1325},
year = {1998},
url = {https://doi.org/10.1109/43.736571},
doi = {10.1109/43.736571},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/CallandMPRV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Chakrabarty98,
author = {Krishnendu Chakrabarty},
title = {Zero-aliasing space compaction using linear compactors with bounded
overhead},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {452--457},
year = {1998},
url = {https://doi.org/10.1109/43.703941},
doi = {10.1109/43.703941},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Chakrabarty98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChakrabartyM98,
author = {Krishnendu Chakrabarty and
Brian T. Murray},
title = {Design of built-in test generator circuits using width compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {1044--1051},
year = {1998},
url = {https://doi.org/10.1109/43.728923},
doi = {10.1109/43.728923},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChakrabartyM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChatterjeePK98,
author = {Mitrajit Chatterjee and
Dhiraj K. Pradhan and
Wolfgang Kunz},
title = {{LOT:} Logic Optimization with Testability. New transformations for
logic synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {386--399},
year = {1998},
url = {https://doi.org/10.1109/43.703921},
doi = {10.1109/43.703921},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChatterjeePK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenG98,
author = {Chih{-}Ang Chen and
Sandeep K. Gupta},
title = {Efficient {BIST} {TPG} design and test set compaction via input reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {8},
pages = {692--705},
year = {1998},
url = {https://doi.org/10.1109/43.712101},
doi = {10.1109/43.712101},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenL98,
author = {Hsiao{-}Feng Steven Chen and
D. T. Lee},
title = {On crossing minimization problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {406--418},
year = {1998},
url = {https://doi.org/10.1109/43.703928},
doi = {10.1109/43.703928},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengCIH98,
author = {Yuhua Cheng and
Kai Chen and
Kiyotaka Imai and
Chenming Hu},
title = {A unified {MOSFET} channel charge model for device modeling in circuit
simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {8},
pages = {641--644},
year = {1998},
url = {https://doi.org/10.1109/43.712096},
doi = {10.1109/43.712096},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengCIH98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengCWM98,
author = {David Ihsin Cheng and
Kwang{-}Ting Cheng and
Deborah C. Wang and
Malgorzata Marek{-}Sadowska},
title = {A hybrid methodology for switching activities estimation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {4},
pages = {357--366},
year = {1998},
url = {https://doi.org/10.1109/43.703825},
doi = {10.1109/43.703825},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChengCWM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengRTRK98,
author = {Yi{-}Kan Cheng and
Prasun Raha and
Chin{-}Chi Teng and
Elyse Rosenbaum and
Sung{-}Mo Kang},
title = {{ILLIADS-T:} an electrothermal timing simulator for temperature-sensitive
reliability diagnosis of {CMOS} {VLSI} chips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {8},
pages = {668--681},
year = {1998},
url = {https://doi.org/10.1109/43.712099},
doi = {10.1109/43.712099},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengRTRK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoS98,
author = {Jun Dong Cho and
Majid Sarrafzadeh},
title = {Four-bend top-down global routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {793--802},
year = {1998},
url = {https://doi.org/10.1109/43.720316},
doi = {10.1109/43.720316},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChoS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChuW98,
author = {Chris C. N. Chu and
Martin D. F. Wong},
title = {A matrix synthesis approach to thermal placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1166--1174},
year = {1998},
url = {https://doi.org/10.1109/43.736189},
doi = {10.1109/43.736189},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChuW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongKL98,
author = {Jason Cong and
Andrew B. Kahng and
Kwok{-}Shing Leung},
title = {Efficient algorithms for the minimum shortest path Steiner arborescence
problem with applications to {VLSI} physical design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {1},
pages = {24--39},
year = {1998},
url = {https://doi.org/10.1109/43.673630},
doi = {10.1109/43.673630},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongKL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongW98,
author = {Jason Cong and
Chang Wu},
title = {An efficient algorithm for performance-optimal {FPGA} technology mapping
with retiming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {738--748},
year = {1998},
url = {https://doi.org/10.1109/43.720312},
doi = {10.1109/43.720312},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ConnCHMVW98,
author = {Andrew R. Conn and
Paula K. Coulman and
Ruud A. Haring and
Gregory L. Morrill and
Chandramouli Visweswariah and
Chai Wah Wu},
title = {JiffyTune: circuit optimization using time-domain sensitivities},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1292--1309},
year = {1998},
url = {https://doi.org/10.1109/43.736569},
doi = {10.1109/43.736569},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ConnCHMVW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DabholkarCPR98,
author = {Vinay Dabholkar and
Sreejit Chakravarty and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Techniques for minimizing power dissipation in scan and combinational
circuits during test application},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1325--1333},
year = {1998},
url = {https://doi.org/10.1109/43.736572},
doi = {10.1109/43.736572},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DabholkarCPR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasdanG98,
author = {Ali Dasdan and
Rajesh K. Gupta},
title = {Faster maximum and minimum mean cycle algorithms for system-performance
analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {889--899},
year = {1998},
url = {https://doi.org/10.1109/43.728912},
doi = {10.1109/43.728912},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DasdanG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasguptaK98,
author = {Aurobindo Dasgupta and
Ramesh Karri},
title = {High-reliability, low-energy microarchitecture synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1273--1280},
year = {1998},
url = {https://doi.org/10.1109/43.736567},
doi = {10.1109/43.736567},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DasguptaK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasguptaSB98,
author = {Parthasarathi Dasgupta and
Susmita Sur{-}Kolay and
Bhargab B. Bhattacharya},
title = {A unified approach to topology generation and optimal sizing of floorplans},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {126--135},
year = {1998},
url = {https://doi.org/10.1109/43.681262},
doi = {10.1109/43.681262},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DasguptaSB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DaveJ98,
author = {Bharat P. Dave and
Niraj K. Jha},
title = {{COHRA:} hardware-software cosynthesis of hierarchical heterogeneous
distributed embedded systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {900--919},
year = {1998},
url = {https://doi.org/10.1109/43.728913},
doi = {10.1109/43.728913},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DaveJ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DeyGP98,
author = {Sujit Dey and
Vijay Gangaram and
Miodrag Potkonjak},
title = {A controller redesign technique to enhance testability of controller-data
path circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {157--168},
year = {1998},
url = {https://doi.org/10.1109/43.681265},
doi = {10.1109/43.681265},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DeyGP98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DickJ98,
author = {Robert P. Dick and
Niraj K. Jha},
title = {{MOGAC:} a multiobjective genetic algorithm for hardware-software
cosynthesis of distributed embedded systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {920--935},
year = {1998},
url = {https://doi.org/10.1109/43.728914},
doi = {10.1109/43.728914},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DickJ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DingTP98,
author = {Chih{-}Shun Ding and
Chi{-}Ying Tsui and
Massoud Pedram},
title = {Gate-level power estimation using tagged probabilistic simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1099--1107},
year = {1998},
url = {https://doi.org/10.1109/43.736184},
doi = {10.1109/43.736184},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DingTP98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DingWHP98,
author = {Chih{-}Shun Ding and
Qing Wu and
Cheng{-}Ta Hsieh and
Massoud Pedram},
title = {Stratified random sampling for power estimation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {6},
pages = {465--471},
year = {1998},
url = {https://doi.org/10.1109/43.703828},
doi = {10.1109/43.703828},
timestamp = {Tue, 12 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DingWHP98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Dmitriev-Zdorov98,
author = {Vladimir B. Dmitriev{-}Zdorov},
title = {Multicycle generalization. {A} new way to improve the convergence
of waveform relaxation for circuit simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {435--443},
year = {1998},
url = {https://doi.org/10.1109/43.703936},
doi = {10.1109/43.703936},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Dmitriev-Zdorov98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerB98,
author = {Rolf Drechsler and
Bernd Becker},
title = {Ordered Kronecker functional decision diagrams-a data structure for
representation and manipulation of Boolean functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {965--973},
year = {1998},
url = {https://doi.org/10.1109/43.728917},
doi = {10.1109/43.728917},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerSS98,
author = {Rolf Drechsler and
Martin Sauerhoff and
Detlef Sieling},
title = {The complexity of the inclusion operation on OFDD's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {457--459},
year = {1998},
url = {https://doi.org/10.1109/43.703943},
doi = {10.1109/43.703943},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerSS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FukudaN98,
author = {Koichi Fukuda and
Kenji Nishi},
title = {An interpolated flux scheme for cellular automaton device simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {7},
pages = {553--560},
year = {1998},
url = {https://doi.org/10.1109/43.709393},
doi = {10.1109/43.709393},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FukudaN98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GharaybehBA98,
author = {Marwan A. Gharaybeh and
Michael L. Bushnell and
Vishwani D. Agrawal},
title = {The path-status graph with application to delay fault simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {4},
pages = {324--332},
year = {1998},
url = {https://doi.org/10.1109/43.703822},
doi = {10.1109/43.703822},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GharaybehBA98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GharaybehBA98a,
author = {Marwan A. Gharaybeh and
Michael L. Bushnell and
Vishwani D. Agrawal},
title = {A parallel-vector concurrent-fault simulator and generation of single-input-change
tests for path-delay faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {873--876},
year = {1998},
url = {https://doi.org/10.1109/43.720322},
doi = {10.1109/43.720322},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GharaybehBA98a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhoshRJ98,
author = {Indradeep Ghosh and
Anand Raghunathan and
Niraj K. Jha},
title = {A design-for-testability technique for register-transfer level circuits
using control/data flow extraction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {8},
pages = {706--723},
year = {1998},
url = {https://doi.org/10.1109/43.712102},
doi = {10.1109/43.712102},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhoshRJ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GoldbergVBS98,
author = {Evguenii I. Goldberg and
Tiziano Villa and
Robert K. Brayton and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Theory and algorithms for face hypercube embedding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {6},
pages = {472--488},
year = {1998},
url = {https://doi.org/10.1109/43.703829},
doi = {10.1109/43.703829},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GoldbergVBS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GongC98,
author = {Yiming Gong and
Sreejit Chakravarty},
title = {Locating bridging faults using dynamically computed stuck-at fault
dictionaries},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {876--887},
year = {1998},
url = {https://doi.org/10.1109/43.720323},
doi = {10.1109/43.720323},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GongC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiaoRP98,
author = {Michael S. Hsiao and
Elizabeth M. Rudnick and
Janak H. Patel},
title = {Application of genetically engineered finite-state-machine sequences
to sequential circuit {ATPG}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {3},
pages = {239--254},
year = {1998},
url = {https://doi.org/10.1109/43.700722},
doi = {10.1109/43.700722},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiaoRP98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehP98,
author = {Cheng{-}Ta Hsieh and
Massoud Pedram},
title = {Microprocessor power estimation using profile-driven program synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1080--1089},
year = {1998},
url = {https://doi.org/10.1109/43.736182},
doi = {10.1109/43.736182},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiehP98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangAT98,
author = {Kaiyuan Huang and
Vinod K. Agarwal and
Krishnaiyan Thulasiraman},
title = {Diagnosis of clustered faults and wafer testing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {136--148},
year = {1998},
url = {https://doi.org/10.1109/43.681263},
doi = {10.1109/43.681263},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangAT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuttonRGC98,
author = {Michael D. Hutton and
Jonathan Rose and
Jerry P. Grossman and
Derek G. Corneil},
title = {Characterization and parameterized generation of synthetic combinational
benchmark circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {985--996},
year = {1998},
url = {https://doi.org/10.1109/43.728919},
doi = {10.1109/43.728919},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuttonRGC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HwangHW98,
author = {Shih{-}Arn Hwang and
Jin{-}Hua Hong and
Cheng{-}Wen Wu},
title = {Sequential circuit fault simulation using logic emulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {8},
pages = {724--736},
year = {1998},
url = {https://doi.org/10.1109/43.712103},
doi = {10.1109/43.712103},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HwangHW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JenS98,
author = {Steve H. Jen and
Bing J. Sheu},
title = {A compact and unified {MOS} {DC} current model with highly continuous
conductances for low-voltage ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {169--172},
year = {1998},
url = {https://doi.org/10.1109/43.681266},
doi = {10.1109/43.681266},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JenS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungerLM98,
author = {Michael J{\"{u}}nger and
Sebastian Leipert and
Petra Mutzel},
title = {A note on computing a maximal planar subgraph using PQ-trees},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {7},
pages = {609--612},
year = {1998},
url = {https://doi.org/10.1109/43.709399},
doi = {10.1109/43.709399},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungerLM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngS98,
author = {Andrew B. Kahng and
Majid Sarrafzadeh},
title = {Guest Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {1},
pages = {1--2},
year = {1998},
url = {https://doi.org/10.1109/TCAD.1998.673627},
doi = {10.1109/TCAD.1998.673627},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KalavadeS98,
author = {Asawaree Kalavade and
P. A. Subrahmanyam},
title = {Hardware/software partitioning for multifunction systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {819--837},
year = {1998},
url = {https://doi.org/10.1109/43.720318},
doi = {10.1109/43.720318},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KalavadeS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KayP98,
author = {Rony Kay and
Lawrence T. Pileggi},
title = {{EWA:} efficient wiring-sizing algorithm for signal nets and clock
nets},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {1},
pages = {40--49},
year = {1998},
url = {https://doi.org/10.1109/43.673631},
doi = {10.1109/43.673631},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KayP98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KernsY98,
author = {Kevin J. Kerns and
Andrew T. Yang},
title = {Preservation of passivity during {RLC} network reduction via split
congruence transformations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {7},
pages = {582--591},
year = {1998},
url = {https://doi.org/10.1109/43.709396},
doi = {10.1109/43.709396},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KernsY98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KidambiTMB98,
author = {M. K. Kidambi and
Akhilesh Tyagi and
Mohammed R. Madani and
Magdy A. Bayoumi},
title = {Three-dimensional defect sensitivity modeling for open circuits in
{ULSI} structures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {4},
pages = {366--371},
year = {1998},
url = {https://doi.org/10.1109/43.703826},
doi = {10.1109/43.703826},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KidambiTMB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimD98,
author = {Juho Kim and
David Hung{-}Chang Du},
title = {Performance optimization by gate sizing and path sensitization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {459--462},
year = {1998},
url = {https://doi.org/10.1109/43.703945},
doi = {10.1109/43.703945},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimJT98,
author = {Taewhan Kim and
William Jao and
Steven W. K. Tjiang},
title = {Circuit optimization using carry-save-adder cells},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {974--984},
year = {1998},
url = {https://doi.org/10.1109/43.728918},
doi = {10.1109/43.728918},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimJT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KishinevskyKLST98,
author = {Michael Kishinevsky and
Alex Kondratyev and
Luciano Lavagno and
Alexander Saldanha and
Alexander Taubin},
title = {Partial-scan delay fault testing of asynchronous circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1184--1199},
year = {1998},
url = {https://doi.org/10.1109/43.736191},
doi = {10.1109/43.736191},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KishinevskyKLST98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KondoOT98,
author = {Masaki Kondo and
Hidetoshi Onodera and
Keikichi Tamaru},
title = {Model-adaptable {MOSFET} parameter-extraction method using an intermediate
model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {400--405},
year = {1998},
url = {https://doi.org/10.1109/43.703924},
doi = {10.1109/43.703924},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KondoOT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KondratyevKY98,
author = {Alex Kondratyev and
Michael Kishinevsky and
Alexandre Yakovlev},
title = {Hazard-free implementation of speed-independent circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {749--771},
year = {1998},
url = {https://doi.org/10.1109/43.720313},
doi = {10.1109/43.720313},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KondratyevKY98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KonukF98,
author = {Haluk Konuk and
F. Joel Ferguson},
title = {Oscillation and sequential behavior caused by opens in the routing
in digital {CMOS} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1200--1210},
year = {1998},
url = {https://doi.org/10.1109/43.736192},
doi = {10.1109/43.736192},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KonukF98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LavoCLF98,
author = {David B. Lavo and
Brian Chess and
Tracy Larrabee and
F. Joel Ferguson},
title = {Diagnosing realistic bridging faults with single stuck-at information},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {3},
pages = {255--268},
year = {1998},
url = {https://doi.org/10.1109/43.700723},
doi = {10.1109/43.700723},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LavoCLF98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeS98,
author = {Edward A. Lee and
Alberto L. Sangiovanni{-}Vincentelli},
title = {A framework for comparing models of computation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1217--1229},
year = {1998},
url = {https://doi.org/10.1109/43.736561},
doi = {10.1109/43.736561},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeitnerS98,
author = {Ernst Leitner and
Siegfried Selberherr},
title = {Mixed-element decomposition method for three-dimensional grid adaptation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {7},
pages = {561--572},
year = {1998},
url = {https://doi.org/10.1109/43.709394},
doi = {10.1109/43.709394},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeitnerS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiJ98,
author = {Xiao Quan Li and
Marwan A. Jabri},
title = {Machine learning-based {VLSI} cells shape function estimation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {7},
pages = {613--623},
year = {1998},
url = {https://doi.org/10.1109/43.709400},
doi = {10.1109/43.709400},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiJ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiaoDK98,
author = {Stan Y. Liao and
Srinivas Devadas and
Kurt Keutzer},
title = {Code density optimization for embedded {DSP} processors using data
compression techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {7},
pages = {601--608},
year = {1998},
url = {https://doi.org/10.1109/43.709398},
doi = {10.1109/43.709398},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiaoDK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinMCL98,
author = {Chih{-}Chang Lin and
Malgorzata Marek{-}Sadowska and
Kwang{-}Ting Cheng and
Mike Tien{-}Chien Lee},
title = {Test-point insertion: scan paths through functional logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {838--851},
year = {1998},
url = {https://doi.org/10.1109/43.720319},
doi = {10.1109/43.720319},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LinMCL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinMLC98,
author = {Chih{-}Chang Lin and
Malgorzata Marek{-}Sadowska and
Mike Tien{-}Chien Lee and
Kuang{-}Chien Chen},
title = {Cost-free scan: a low-overhead scan path design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {852--861},
year = {1998},
url = {https://doi.org/10.1109/43.720320},
doi = {10.1109/43.720320},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinMLC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuW98,
author = {Huiqun Liu and
Martin D. F. Wong},
title = {Network-flow-based multiway partitioning with area and pin constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {1},
pages = {50--59},
year = {1998},
url = {https://doi.org/10.1109/43.673632},
doi = {10.1109/43.673632},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LoweG98,
author = {Kerry S. Lowe and
P. Glenn Gulak},
title = {A joint gate sizing and buffer insertion method for optimizing delay
and power in {CMOS} and BiCMOS combinational logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {419--434},
year = {1998},
url = {https://doi.org/10.1109/43.703932},
doi = {10.1109/43.703932},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LoweG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaciiPS98,
author = {Enrico Macii and
Massoud Pedram and
Fabio Somenzi},
title = {High-level power modeling, estimation, and optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1061--1079},
year = {1998},
url = {https://doi.org/10.1109/43.736181},
doi = {10.1109/43.736181},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaciiPS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarculescuMP98,
author = {Radu Marculescu and
Diana Marculescu and
Massoud Pedram},
title = {Probabilistic modeling of dependencies during switching activity analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {73--83},
year = {1998},
url = {https://doi.org/10.1109/43.681258},
doi = {10.1109/43.681258},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MarculescuMP98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MartinsPSS98,
author = {Rui Escadas Martins and
Wolfgang Pyka and
Rainer Sabelka and
Siegfried Selberherr},
title = {High-precision interconnect analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1148--1159},
year = {1998},
url = {https://doi.org/10.1109/43.736187},
doi = {10.1109/43.736187},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MartinsPSS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Miller98,
author = {D. Michael Miller},
title = {An improved method for computing a generalized spectral coefficient},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {3},
pages = {233--238},
year = {1998},
url = {https://doi.org/10.1109/43.700721},
doi = {10.1109/43.700721},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Miller98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MonteiroDG98,
author = {Jos{\'{e}} Monteiro and
Srinivas Devadas and
Abhijit Ghosh},
title = {Sequential logic optimization for low power using input-disabling
precomputation architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {3},
pages = {279--284},
year = {1998},
url = {https://doi.org/10.1109/43.700725},
doi = {10.1109/43.700725},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MonteiroDG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MurataFK98,
author = {Hiroshi Murata and
Kunihiro Fujiyoshi and
Mineo Kaneko},
title = {{VLSI/PCB} placement with obstacles based on sequence pair},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {1},
pages = {60--68},
year = {1998},
url = {https://doi.org/10.1109/43.673633},
doi = {10.1109/43.673633},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MurataFK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NagR98,
author = {Sudip Nag and
Rob A. Rutenbar},
title = {Performance-driven simultaneous placement and routing for FPGA's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {6},
pages = {499--518},
year = {1998},
url = {https://doi.org/10.1109/43.703831},
doi = {10.1109/43.703831},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/NagR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NagaoSK98,
author = {Akira Nagao and
Isao Shirakawa and
Takashi Kambe},
title = {A layout approach to monolithic microwave {IC}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1262--1272},
year = {1998},
url = {https://doi.org/10.1109/43.736566},
doi = {10.1109/43.736566},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NagaoSK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NagiCYA98,
author = {Naveena Nagi and
Abhijit Chatterjee and
Heebyung Yoon and
Jacob A. Abraham},
title = {Signature analysis for analog and mixed-signal circuit test response
compaction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {6},
pages = {540--546},
year = {1998},
url = {https://doi.org/10.1109/43.703834},
doi = {10.1109/43.703834},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NagiCYA98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NakatakeFMK98,
author = {Shigetoshi Nakatake and
Kunihiro Fujiyoshi and
Hiroshi Murata and
Yoji Kajitani},
title = {Module packing based on the BSG-structure and {IC} layout applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {6},
pages = {519--530},
year = {1998},
url = {https://doi.org/10.1109/43.703832},
doi = {10.1109/43.703832},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NakatakeFMK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NaseerBK98,
author = {A. R. Naseer and
M. Balakrishnan and
Anshul Kumar},
title = {Direct mapping of {RTL} structures onto LUT-based FPGA's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {7},
pages = {624--631},
year = {1998},
url = {https://doi.org/10.1109/43.709401},
doi = {10.1109/43.709401},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NaseerBK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NiknejadGM98,
author = {Ali M. Niknejad and
Ranjit Gharpurey and
Robert G. Meyer},
title = {Numerically stable Green function for modeling and analysis of substrate
coupling in integrated circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {4},
pages = {305--315},
year = {1998},
url = {https://doi.org/10.1109/43.703820},
doi = {10.1109/43.703820},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NiknejadGM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OdabasiogluCP98,
author = {Altan Odabasioglu and
Mustafa Celik and
Lawrence T. Pileggi},
title = {{PRIMA:} passive reduced-order interconnect macromodeling algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {8},
pages = {645--654},
year = {1998},
url = {https://doi.org/10.1109/43.712097},
doi = {10.1109/43.712097},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OdabasiogluCP98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PanKL98,
author = {Peichen Pan and
Arvind K. Karandikar and
C. L. Liu},
title = {Optimal clock period clustering for sequential circuits with retiming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {6},
pages = {489--498},
year = {1998},
url = {https://doi.org/10.1109/43.703830},
doi = {10.1109/43.703830},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PanKL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PandaDN98,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
title = {Incorporating {DRAM} access modes into high-level synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {96--109},
year = {1998},
url = {https://doi.org/10.1109/43.681260},
doi = {10.1109/43.681260},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PandaDN98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkP98,
author = {Kwang{-}Il Park and
Kyu Ho Park},
title = {Event suppression by optimizing {VHDL} programs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {8},
pages = {682--691},
year = {1998},
url = {https://doi.org/10.1109/43.712100},
doi = {10.1109/43.712100},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkP98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PastorCKR98,
author = {Enric Pastor and
Jordi Cortadella and
Alex Kondratyev and
Oriol Roig},
title = {Structural methods for the synthesis of speed-independent circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1108--1129},
year = {1998},
url = {https://doi.org/10.1109/43.736185},
doi = {10.1109/43.736185},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PastorCKR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Patil98,
author = {Mahesh B. Patil},
title = {New discretization scheme for two-dimensional semiconductor device
simulation on triangular grid},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1160--1165},
year = {1998},
url = {https://doi.org/10.1109/43.736188},
doi = {10.1109/43.736188},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Patil98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PlasunSS98,
author = {Richard Plasun and
Michael Stockinger and
Siegfried Selberherr},
title = {Integrated optimization capabilities in the {VISTA} technology {CAD}
framework},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1244--1251},
year = {1998},
url = {https://doi.org/10.1109/43.736564},
doi = {10.1109/43.736564},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PlasunSS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Low-complexity fault simulation under the multiple observation time
and the restricted multiple observation time testing approaches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {3},
pages = {269--278},
year = {1998},
url = {https://doi.org/10.1109/43.700724},
doi = {10.1109/43.700724},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR98a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Design-for-testability for path delay faults in large combinational
circuits using test points},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {4},
pages = {333--343},
year = {1998},
url = {https://doi.org/10.1109/43.703823},
doi = {10.1109/43.703823},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR98a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR98b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test sequences to achieve high defect coverage for synchronous sequential
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {1017--1029},
year = {1998},
url = {https://doi.org/10.1109/43.728921},
doi = {10.1109/43.728921},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR98b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PotkonjakS98,
author = {Miodrag Potkonjak and
Mani B. Srivastava},
title = {Behavioral optimization using the manipulation of timing constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {936--947},
year = {1998},
url = {https://doi.org/10.1109/43.728915},
doi = {10.1109/43.728915},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PotkonjakS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SathyamurthySF98,
author = {Harsha Sathyamurthy and
Sachin S. Sapatnekar and
John P. Fishburn},
title = {Speeding up pipelined circuits through a combination of gate sizing
and clock skew optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {173--182},
year = {1998},
url = {https://doi.org/10.1109/43.681267},
doi = {10.1109/43.681267},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SathyamurthySF98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Savir98,
author = {Jacob Savir},
title = {Random pattern testability of memory address logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1310--1318},
year = {1998},
url = {https://doi.org/10.1109/43.736570},
doi = {10.1109/43.736570},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Savir98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchmitT98,
author = {Herman Schmit and
Donald E. Thomas},
title = {Address generation for memories containing multiple arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {377--385},
year = {1998},
url = {https://doi.org/10.1109/43.703919},
doi = {10.1109/43.703919},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SchmitT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Stankovic98,
author = {Radomir S. Stankovic},
title = {Some remarks on terminology in spectral techniques for logic design:
Walsh transform and Hadamard matrices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1211--1214},
year = {1998},
url = {https://doi.org/10.1109/43.736193},
doi = {10.1109/43.736193},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Stankovic98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StroeleW98,
author = {Albrecht P. Stroele and
Hans{-}Joachim Wunderlich},
title = {Hardware-optimal test register insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {6},
pages = {531--539},
year = {1998},
url = {https://doi.org/10.1109/43.703833},
doi = {10.1109/43.703833},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StroeleW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SunDC98,
author = {Shangzhi Sun and
David Hung{-}Chang Du and
Hsi{-}Chuan Chen},
title = {Efficient timing analysis for {CMOS} circuits considering data dependent
delays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {6},
pages = {546--552},
year = {1998},
url = {https://doi.org/10.1109/43.703835},
doi = {10.1109/43.703835},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SunDC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangLL98,
author = {Jing{-}Jou Tang and
Kuen{-}Jong Lee and
Bin{-}Da Liu},
title = {A graph representation for programmable logic arrays to facilitate
testing and logic design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {1030--1043},
year = {1998},
url = {https://doi.org/10.1109/43.728922},
doi = {10.1109/43.728922},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangLL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TheobaldN98,
author = {Michael Theobald and
Steven M. Nowick},
title = {Fast heuristic and exact algorithms for two-level hazard-free logic
minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1130--1147},
year = {1998},
url = {https://doi.org/10.1109/43.736186},
doi = {10.1109/43.736186},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TheobaldN98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TinOM98,
author = {Suet Fong Tin and
Ashraf A. Osman and
Kartikeya Mayaram},
title = {Comments on "A small-signal {MOSFET} model for radio frequency {IC}
applications"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {4},
pages = {372--374},
year = {1998},
url = {https://doi.org/10.1109/43.703827},
doi = {10.1109/43.703827},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TinOM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TiwariMA98,
author = {Vivek Tiwari and
Sharad Malik and
Pranav Ashar},
title = {Guarded evaluation: pushing power management to logic synthesis/design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {1051--1060},
year = {1998},
url = {https://doi.org/10.1109/43.728924},
doi = {10.1109/43.728924},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TiwariMA98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TogawaYO98,
author = {Nozomu Togawa and
Masao Yanagisawa and
Tatsuo Ohtsuki},
title = {Maple-opt: a performance-oriented simultaneous technology mapping,
placement, and global routing algorithm for FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {803--818},
year = {1998},
url = {https://doi.org/10.1109/43.720317},
doi = {10.1109/43.720317},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TogawaYO98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TsaiWC98,
author = {Chia{-}Chun Tsai and
Chwan{-}Ming Wang and
Sao{-}Jie Chen},
title = {{NEWS:} a net-even-wiring system for the routing on a multilayer {PGA}
package},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {182--189},
year = {1998},
url = {https://doi.org/10.1109/43.681268},
doi = {10.1109/43.681268},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TsaiWC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TsuiPD98,
author = {Chi{-}Ying Tsui and
Massoud Pedram and
Alvin M. Despain},
title = {Low-power state assignment targeting two- and multilevel logic implementations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1281--1291},
year = {1998},
url = {https://doi.org/10.1109/43.736568},
doi = {10.1109/43.736568},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TsuiPD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TurgisA98,
author = {S. Turgis and
Daniel Auvergne},
title = {A novel macromodel for power estimation in {CMOS} structures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1090--1098},
year = {1998},
url = {https://doi.org/10.1109/43.736183},
doi = {10.1109/43.736183},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TurgisA98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VandenbergheBG98,
author = {Lieven Vandenberghe and
Stephen P. Boyd and
Abbas A. El Gamal},
title = {Optimizing dominant time constant in {RC} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {2},
pages = {110--125},
year = {1998},
url = {https://doi.org/10.1109/43.681261},
doi = {10.1109/43.681261},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VandenbergheBG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangD98,
author = {Feng Wang and
Donald L. Dietmeyer},
title = {Exploiting near symmetry in multilevel logic synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {772--781},
year = {1998},
url = {https://doi.org/10.1109/43.720314},
doi = {10.1109/43.720314},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangGS98,
author = {Zhihua Wang and
Georges G. E. Gielen and
Willy M. C. Sansen},
title = {Probabilistic fault detection and the selection of measurements for
analog integrated circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {862--872},
year = {1998},
url = {https://doi.org/10.1109/43.720321},
doi = {10.1109/43.720321},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangGS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WintonB98,
author = {Raymond S. Winton and
William R. Bandy},
title = {A simple, continuous, analytical charge/capacitance model for the
short-channel {MOSFET}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {7},
pages = {631--638},
year = {1998},
url = {https://doi.org/10.1109/43.709402},
doi = {10.1109/43.709402},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WintonB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WordelmanKS98,
author = {Carl J. Wordelman and
Thomas J. T. Kwan and
Charles M. Snell},
title = {Comparison of statistical enhancement methods for Monte Carlo semiconductor
simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1230--1235},
year = {1998},
url = {https://doi.org/10.1109/43.736562},
doi = {10.1109/43.736562},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WordelmanKS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XieB98,
author = {Aiguo Xie and
Peter A. Beerel},
title = {Efficient state classification of finite-state Markov chains},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1334--1339},
year = {1998},
url = {https://doi.org/10.1109/43.736573},
doi = {10.1109/43.736573},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XieB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangW98,
author = {Hannah Honghua Yang and
Martin D. F. Wong},
title = {Optimal min-area min-cut replication in partitioned circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {11},
pages = {1175--1183},
year = {1998},
url = {https://doi.org/10.1109/43.736190},
doi = {10.1109/43.736190},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YunLDD98,
author = {Kenneth Y. Yun and
Bill Lin and
David L. Dill and
Srinivas Devadas},
title = {BDD-based synthesis of extended burst-mode controllers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {9},
pages = {782--792},
year = {1998},
url = {https://doi.org/10.1109/43.720315},
doi = {10.1109/43.720315},
timestamp = {Mon, 01 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YunLDD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhuW98,
author = {Kai Zhu and
Martin D. F. Wong},
title = {Switch bound allocation for maximizing routability in timing-driven
routing of FPGA's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {4},
pages = {316--323},
year = {1998},
url = {https://doi.org/10.1109/43.703821},
doi = {10.1109/43.703821},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhuW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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