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@article{DBLP:journals/tcad/Abdel-MalekHH99,
author = {Hany L. Abdel{-}Malek and
Abdel{-}Karim S. O. Hassan and
Mohamed H. Heaba},
title = {A boundary gradient search technique and its applications in design
centering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1654--1660},
year = {1999},
url = {https://doi.org/10.1109/43.806810},
doi = {10.1109/43.806810},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Abdel-MalekHH99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AbderrahmanCK99,
author = {Abdessatar Abderrahman and
Eduard Cerny and
Bozena Kaminska},
title = {Worst case tolerance analysis and CLP-based multifrequency test generation
for analog circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {3},
pages = {332--345},
year = {1999},
url = {https://doi.org/10.1109/43.748163},
doi = {10.1109/43.748163},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AbderrahmanCK99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AktunaRC99,
author = {Mehmet Aktuna and
Rob A. Rutenbar and
L. Richard Carley},
title = {Device-level early floorplanning algorithms for {RF} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {375--388},
year = {1999},
url = {https://doi.org/10.1109/43.752922},
doi = {10.1109/43.752922},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/AktunaRC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AliotoP99,
author = {Massimo Alioto and
Gaetano Palumbo},
title = {Highly accurate and simple models for {CML} and {ECL} gates},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1369--1375},
year = {1999},
url = {https://doi.org/10.1109/43.784127},
doi = {10.1109/43.784127},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AliotoP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AllanW99,
author = {Gerard A. Allan and
Anthony J. Walton},
title = {Efficient extra material critical area algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1480--1486},
year = {1999},
url = {https://doi.org/10.1109/43.790624},
doi = {10.1109/43.790624},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AllanW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertDQ99,
author = {Charles J. Alpert and
Anirudh Devgan and
Stephen T. Quay},
title = {Buffer insertion for noise and delay optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1633--1645},
year = {1999},
url = {https://doi.org/10.1109/43.806808},
doi = {10.1109/43.806808},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertDQ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AsenovBDS99,
author = {Asen Asenov and
Andrew R. Brown and
John H. Davies and
Subhash Saini},
title = {Hierarchical approach to "atomistic" 3-D {MOSFET} simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1558--1565},
year = {1999},
url = {https://doi.org/10.1109/43.806802},
doi = {10.1109/43.806802},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AsenovBDS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BaegR99,
author = {Sanghyeon Baeg and
William A. Rogers},
title = {A cost-effective design for testability: clock line control and test
generation using selective clocking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {850--861},
year = {1999},
url = {https://doi.org/10.1109/43.766732},
doi = {10.1109/43.766732},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BaegR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BaiSSY99,
author = {Zhaojun Bai and
Rodney D. Slone and
William T. Smith and
Qiang Ye},
title = {Error bound for reduced system model by Pade approximation via the
Lanczos process},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {133--141},
year = {1999},
url = {https://doi.org/10.1109/43.743719},
doi = {10.1109/43.743719},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BaiSSY99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BalarinCGHJLSSS99,
author = {Felice Balarin and
Massimiliano Chiodo and
Paolo Giusto and
Harry Hsieh and
Attila Jurecska and
Luciano Lavagno and
Alberto L. Sangiovanni{-}Vincentelli and
Ellen Sentovich and
Kei Suzuki},
title = {Synthesis of software programs for embedded control applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {834--849},
year = {1999},
url = {https://doi.org/10.1109/43.766731},
doi = {10.1109/43.766731},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BalarinCGHJLSSS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BazarganKS99,
author = {Kia Bazargan and
Samjung Kim and
Majid Sarrafzadeh},
title = {Nostradamus: a floorplanner of uncertain designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {389--397},
year = {1999},
url = {https://doi.org/10.1109/43.752923},
doi = {10.1109/43.752923},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BazarganKS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeattieP99,
author = {Michael W. Beattie and
Lawrence T. Pileggi},
title = {Error bounds for capacitance extraction via window techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {3},
pages = {311--321},
year = {1999},
url = {https://doi.org/10.1109/43.748161},
doi = {10.1109/43.748161},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeattieP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeniniBPM99,
author = {Luca Benini and
Alessandro Bogliolo and
Giuseppe A. Paleologo and
Giovanni De Micheli},
title = {Policy optimization for dynamic power management},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {813--833},
year = {1999},
url = {https://doi.org/10.1109/43.766730},
doi = {10.1109/43.766730},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeniniBPM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BlumenrohrES99,
author = {Christian Blumenr{\"{o}}hr and
Dirk Eisenbiegler and
Detlef Schmid},
title = {On the efficiency of formal synthesis-experimental results},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {1},
pages = {25--32},
year = {1999},
url = {https://doi.org/10.1109/43.739056},
doi = {10.1109/43.739056},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BlumenrohrES99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BorrielloVC99,
author = {Gaetano Borriello and
Diederik Verkest and
Francky Catthoor},
title = {Guest Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {1},
pages = {1--2},
year = {1999},
url = {https://doi.org/10.1109/TCAD.1999.739053},
doi = {10.1109/TCAD.1999.739053},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BorrielloVC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BoubezariCKN99,
author = {Samir Boubezari and
Eduard Cerny and
Bozena Kaminska and
Benoit Nadeau{-}Dostie},
title = {Testability analysis and test-point insertion in {RTL} {VHDL} specifications
for scan-based {BIST}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1327--1340},
year = {1999},
url = {https://doi.org/10.1109/43.784124},
doi = {10.1109/43.784124},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BoubezariCKN99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CabodiCQ99,
author = {Gianpiero Cabodi and
Paolo Camurati and
Stefano Quer},
title = {Improving the efficiency of BDD-based operators by means of partitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {545--556},
year = {1999},
url = {https://doi.org/10.1109/43.759068},
doi = {10.1109/43.759068},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CabodiCQ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CaldwellKMMZ99,
author = {Andrew E. Caldwell and
Andrew B. Kahng and
Stefanus Mantik and
Igor L. Markov and
Alexander Zelikovsky},
title = {On wirelength estimations for row-based placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1265--1278},
year = {1999},
url = {https://doi.org/10.1109/43.784119},
doi = {10.1109/43.784119},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CaldwellKMMZ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CampenhoutMS99,
author = {David Van Campenhout and
Trevor N. Mudge and
Karem A. Sakallah},
title = {Timing verification of sequential dynamic circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {645--658},
year = {1999},
url = {https://doi.org/10.1109/43.759081},
doi = {10.1109/43.759081},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CampenhoutMS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CelikP99,
author = {Mustafa Celik and
Lawrence T. Pileggi},
title = {Metrics and bounds for phase delay and signal attenuation in RC(L)clock
trees},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {3},
pages = {293--300},
year = {1999},
url = {https://doi.org/10.1109/43.748159},
doi = {10.1109/43.748159},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CelikP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChaRN99,
author = {Young{-}Jun Cha and
Chong S. Rim and
Kazuo Nakajima},
title = {{SEGRA:} a very fast general area router for multichip modules},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {659--665},
year = {1999},
url = {https://doi.org/10.1109/43.759082},
doi = {10.1109/43.759082},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChaRN99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChakrabortyYD99,
author = {Supratik Chakraborty and
Kenneth Y. Yun and
David L. Dill},
title = {Timing analysis of asynchronous systems using time separation of events},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1061--1076},
year = {1999},
url = {https://doi.org/10.1109/43.775628},
doi = {10.1109/43.775628},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChakrabortyYD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChakradharD99,
author = {Srimat T. Chakradhar and
Sujit Dey},
title = {Resynthesis and retiming for optimum partial scan},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {621--630},
year = {1999},
url = {https://doi.org/10.1109/43.759078},
doi = {10.1109/43.759078},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChakradharD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Chang99,
author = {K. C. Chang},
title = {Comment on "Event suppression by optimizing {VHDL} programs"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1400--1401},
year = {1999},
url = {https://doi.org/10.1109/43.784131},
doi = {10.1109/43.784131},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Chang99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangC99,
author = {Chin{-}Chih Chang and
Jason Cong},
title = {An efficient approach to multilayer layer assignment with anapplication
to via minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {608--620},
year = {1999},
url = {https://doi.org/10.1109/43.759077},
doi = {10.1109/43.759077},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangC99a,
author = {Shih{-}Chieh Chang and
David Ihsin Cheng},
title = {Efficient Boolean division and substitution using redundancy addition
and removing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1096--1106},
year = {1999},
url = {https://doi.org/10.1109/43.775630},
doi = {10.1109/43.775630},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangC99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CharbonGMS99,
author = {Edoardo Charbon and
Ranjit Gharpurey and
Robert G. Meyer and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Substrate optimization based on semi-analytical techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {172--190},
year = {1999},
url = {https://doi.org/10.1109/43.743727},
doi = {10.1109/43.743727},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CharbonGMS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CharbonMCFS99,
author = {Edoardo Charbon and
Paolo Miliozzi and
Luca P. Carloni and
Alberto Ferrari and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Modeling digital substrate noise injection in mixed-signal IC's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {3},
pages = {301--310},
year = {1999},
url = {https://doi.org/10.1109/43.748160},
doi = {10.1109/43.748160},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CharbonMCFS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChatzigeorgiouNT99,
author = {Alexander Chatzigeorgiou and
Spiridon Nikolaidis and
Ioannis Tsoukalas},
title = {A modeling technique for {CMOS} gates},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {557--575},
year = {1999},
url = {https://doi.org/10.1109/43.759070},
doi = {10.1109/43.759070},
timestamp = {Tue, 04 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChatzigeorgiouNT99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCW99,
author = {Chung{-}Ping Chen and
Chris C. N. Chu and
Martin D. F. Wong},
title = {Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {1014--1025},
year = {1999},
url = {https://doi.org/10.1109/43.771182},
doi = {10.1109/43.771182},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenCW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengHD99,
author = {Kwang{-}Ting Cheng and
Shi{-}Yu Huang and
Wei{-}Jin Dai},
title = {Fault emulation: {A} new methodology for fault grading},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1487--1495},
year = {1999},
url = {https://doi.org/10.1109/43.790625},
doi = {10.1109/43.790625},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChengHD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChessL99,
author = {Brian Chess and
Tracy Larrabee},
title = {Creating small fault dictionaries [logic circuit fault diagnosis]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {3},
pages = {346--356},
year = {1999},
url = {https://doi.org/10.1109/43.748164},
doi = {10.1109/43.748164},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChessL99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouBY99,
author = {Wei{-}Chun Chou and
Peter A. Beerel and
Kenneth Y. Yun},
title = {Average-case technology mapping of asynchronous burst-mode circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1418--1434},
year = {1999},
url = {https://doi.org/10.1109/43.790619},
doi = {10.1109/43.790619},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChouBY99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChowdharyKSSG99,
author = {Amit Chowdhary and
Sudhakar Kale and
Phani K. Saripella and
Naresh Sehgal and
Rajesh K. Gupta},
title = {Extraction of functional regularity in datapath circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1279--1296},
year = {1999},
url = {https://doi.org/10.1109/43.784120},
doi = {10.1109/43.784120},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChowdharyKSSG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChuW99,
author = {Chris C. N. Chu and
Martin D. F. Wong},
title = {Greedy wire-sizing is linear time},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {398--405},
year = {1999},
url = {https://doi.org/10.1109/43.752924},
doi = {10.1109/43.752924},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChuW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChuW99a,
author = {Chris C. N. Chu and
Martin D. F. Wong},
title = {A quadratic programming approach to simultaneous buffer insertion/sizing
and wire sizing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {787--798},
year = {1999},
url = {https://doi.org/10.1109/43.766728},
doi = {10.1109/43.766728},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChuW99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChuW99b,
author = {Chris C. N. Chu and
Martin D. F. Wong},
title = {An efficient and optimal algorithm for simultaneous buffer and wire
sizing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1297--1304},
year = {1999},
url = {https://doi.org/10.1109/43.784121},
doi = {10.1109/43.784121},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChuW99b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ClementRCT99,
author = {J. Joseph Clement and
Stefan P. Riege and
Radenko Cvijetic and
Carl V. Thompson},
title = {Methodology for electromigration critical threshold design rule evaluation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {576--581},
year = {1999},
url = {https://doi.org/10.1109/43.759073},
doi = {10.1109/43.759073},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ClementRCT99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongH99,
author = {Jason Cong and
Lei He},
title = {Theory and algorithm of local-refinement-based optimization with application
to device and interconnect sizing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {406--420},
year = {1999},
url = {https://doi.org/10.1109/43.752925},
doi = {10.1109/43.752925},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongH99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongW99,
author = {Jason Cong and
Chang Wu},
title = {Optimal {FPGA} mapping and retiming with efficient initial state computation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1595--1607},
year = {1999},
url = {https://doi.org/10.1109/43.806805},
doi = {10.1109/43.806805},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ContiCOT99,
author = {Massimo Conti and
Paolo Crippa and
Simone Orcioni and
Claudio Turchetti},
title = {Parametric yield formulation of {MOS} IC's affected by mismatch effect},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {582--596},
year = {1999},
url = {https://doi.org/10.1109/43.759074},
doi = {10.1109/43.759074},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ContiCOT99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CornoGPRVV99,
author = {Fulvio Corno and
Uwe Gl{\"{a}}ser and
Paolo Prinetto and
Matteo Sonza Reorda and
Heinrich Theodor Vierhaus and
Massimo Violante},
title = {SymFony: a hybrid topological-symbolic {ATPG} exploiting RT-level
information},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {191--202},
year = {1999},
url = {https://doi.org/10.1109/43.743731},
doi = {10.1109/43.743731},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CornoGPRVV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CortadellaKKLPY99,
author = {Jordi Cortadella and
Michael Kishinevsky and
Alex Kondratyev and
Luciano Lavagno and
Enric Pastor and
Alexandre Yakovlev},
title = {Decomposition and technology mapping of speed-independent circuits
using Boolean relations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1221--1236},
year = {1999},
url = {https://doi.org/10.1109/43.784116},
doi = {10.1109/43.784116},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CortadellaKKLPY99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CostaCS99,
author = {Jo{\~{a}}o Paulo Costa and
Mike Chou and
Lu{\'{\i}}s Miguel Silveira},
title = {Efficient techniques for accurate modeling and simulation ofsubstrate
coupling in mixed-signal IC's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {597--607},
year = {1999},
url = {https://doi.org/10.1109/43.759076},
doi = {10.1109/43.759076},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CostaCS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DevarayanadurgSGH99,
author = {Giri Devarayanadurg and
Mani Soma and
Prashant Goteti and
Sam D. Huynh},
title = {Test set selection for structural faults in analog IC's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {1026--1039},
year = {1999},
url = {https://doi.org/10.1109/43.771183},
doi = {10.1109/43.771183},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DevarayanadurgSGH99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DeyRJW99,
author = {Sujit Dey and
Anand Raghunathan and
Niraj K. Jha and
Kazutoshi Wakabayashi},
title = {Controller-based power management for control-flow intensive designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1496--1508},
year = {1999},
url = {https://doi.org/10.1109/43.790626},
doi = {10.1109/43.790626},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DeyRJW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DickJ99,
author = {Robert P. Dick and
Niraj K. Jha},
title = {Corrections to "mogac: a multiobjective genetic algorithm for hardware-software
cosynthesis of distributed embedded systems"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1527--1527},
year = {1999},
url = {https://doi.org/10.1109/TCAD.1999.790630},
doi = {10.1109/TCAD.1999.790630},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DickJ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Dierks99,
author = {Henning Dierks},
title = {Synthesizing controllers from real-time specifications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {1},
pages = {33--43},
year = {1999},
url = {https://doi.org/10.1109/43.739057},
doi = {10.1109/43.739057},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Dierks99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DuttAT99,
author = {Shantanu Dutt and
Hasan Arslan and
Halim Theny},
title = {Partitioning using second-order information and stochastic-gainfunctions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {421--435},
year = {1999},
url = {https://doi.org/10.1109/43.752926},
doi = {10.1109/43.752926},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DuttAT99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EckhardtM99,
author = {Uwe Eckhardt and
Renate Merker},
title = {Hierarchical algorithm partitioning at system level for an improved
utilization of memory structures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {1},
pages = {14--24},
year = {1999},
url = {https://doi.org/10.1109/43.739055},
doi = {10.1109/43.739055},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EckhardtM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EinspahrMS99,
author = {Kent L. Einspahr and
Shashank K. Mehta and
Sharad C. Seth},
title = {A synthesis for testability scheme for finite state machines using
clock control},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1780--1792},
year = {1999},
url = {https://doi.org/10.1109/43.811327},
doi = {10.1109/43.811327},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EinspahrMS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EnosHS99,
author = {Morgan Enos and
Scott Hauck and
Majid Sarrafzadeh},
title = {Evaluation and optimization of replication algorithms for logic bipartitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1237--1248},
year = {1999},
url = {https://doi.org/10.1109/43.784117},
doi = {10.1109/43.784117},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EnosHS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EugeneS99,
author = {Le{-}Chin Eugene Liu and
Carl Sechen},
title = {Multilayer pin assignment for macro cell circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1452--1461},
year = {1999},
url = {https://doi.org/10.1109/43.790622},
doi = {10.1109/43.790622},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EugeneS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FernandoJ99,
author = {Joseph A. Fernando and
Jack S. N. Jean},
title = {Processor array design with {FPGA} area constraint},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {3},
pages = {253--264},
year = {1999},
url = {https://doi.org/10.1109/43.748156},
doi = {10.1109/43.748156},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FernandoJ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GaoW99,
author = {Youxin Gao and
Martin D. F. Wong},
title = {Optimal shape function for a bidirectional wire under Elmore delay
model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {994--999},
year = {1999},
url = {https://doi.org/10.1109/43.771180},
doi = {10.1109/43.771180},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GaoW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GaoW99a,
author = {Youxin Gao and
Martin D. F. Wong},
title = {Wire-sizing optimization with inductance consideration using transmission-line
model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1759--1767},
year = {1999},
url = {https://doi.org/10.1109/43.811325},
doi = {10.1109/43.811325},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GaoW99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GargCGIPCMSEKCPKM99,
author = {Atul Garg and
Y. L. Le Coz and
Hans J. Greub and
R. B. Iverson and
Robert F. Philhower and
Pete M. Campbell and
Cliff A. Maier and
Sam A. Steidl and
Matthew W. Ernest and
Russell P. Kraft and
Steven R. Carlough and
J. W. Perry and
Thomas W. Krawczyk Jr. and
John F. McDonald},
title = {Accurate high-speed performance prediction for full differential current-mode
logic: the effect of dielectric anisotropy},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {212--219},
year = {1999},
url = {https://doi.org/10.1109/43.743736},
doi = {10.1109/43.743736},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/GargCGIPCMSEKCPKM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Gebotys99,
author = {Catherine H. Gebotys},
title = {A minimum-cost circulation approach to {DSP} address-code generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {726--741},
year = {1999},
url = {https://doi.org/10.1109/43.766724},
doi = {10.1109/43.766724},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Gebotys99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhoshJD99,
author = {Indradeep Ghosh and
Niraj K. Jha and
Sujit Dey},
title = {A low overhead design for testability and test generation technique
for core-based systems-on-a-chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1661--1676},
year = {1999},
url = {https://doi.org/10.1109/43.806811},
doi = {10.1109/43.806811},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/GhoshJD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhoshRJ99,
author = {Indradeep Ghosh and
Anand Raghunathan and
Niraj K. Jha},
title = {Hierarchical test generation and design for testability methods for
ASPPs and ASIPs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {3},
pages = {357--370},
year = {1999},
url = {https://doi.org/10.1109/43.748165},
doi = {10.1109/43.748165},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhoshRJ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GiraultLL99,
author = {Alain Girault and
Bilung Lee and
Edward A. Lee},
title = {Hierarchical finite state machines with multiple concurrency models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {742--760},
year = {1999},
url = {https://doi.org/10.1109/43.766725},
doi = {10.1109/43.766725},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GiraultLL99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GoodbyO99,
author = {Laurence Goodby and
Alex Orailoglu},
title = {Redundancy and testability in digital filter datapaths},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {631--644},
year = {1999},
url = {https://doi.org/10.1109/43.759079},
doi = {10.1109/43.759079},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GoodbyO99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HamaE99,
author = {Toshiyuki Hama and
Hiroaki Etoh},
title = {Topological routing path search algorithm with incremental routability
test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {142--150},
year = {1999},
url = {https://doi.org/10.1109/43.743721},
doi = {10.1109/43.743721},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HamaE99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HamaE99a,
author = {Toshiyuki Hama and
Hiroaki Etoh},
title = {Curvilinear detailed routing with simultaneous wire-spreading and
wire-fattening},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1646--1653},
year = {1999},
url = {https://doi.org/10.1109/43.806809},
doi = {10.1109/43.806809},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HamaE99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HarrisHL99,
author = {David L. Harris and
Mark Horowitz and
Dean Liu},
title = {Timing analysis including clock skew},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1608--1618},
year = {1999},
url = {https://doi.org/10.1109/43.806806},
doi = {10.1109/43.806806},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HarrisHL99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HauckLS99,
author = {Scott Hauck and
Zhiyuan Li and
Eric J. Schwabe},
title = {Configuration compression for the Xilinx {XC6200} {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1107--1113},
year = {1999},
url = {https://doi.org/10.1109/43.775631},
doi = {10.1109/43.775631},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HauckLS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HongKQPS99,
author = {Inki Hong and
Darko Kirovski and
Gang Qu and
Miodrag Potkonjak and
Mani B. Srivastava},
title = {Power optimization of variable-voltage core-based systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1702--1714},
year = {1999},
url = {https://doi.org/10.1109/43.811318},
doi = {10.1109/43.811318},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HongKQPS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HouHS99,
author = {Huibo Hou and
Jiang Hu and
Sachin S. Sapatnekar},
title = {Non-Hanan routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {436--444},
year = {1999},
url = {https://doi.org/10.1109/43.752927},
doi = {10.1109/43.752927},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HouHS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangC99,
author = {Shi{-}Yu Huang and
Kwang{-}Ting Cheng},
title = {ErrorTracer: design error diagnosis based on fault simulation techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1341--1352},
year = {1999},
url = {https://doi.org/10.1109/43.784125},
doi = {10.1109/43.784125},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HuangC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangCC99,
author = {Shi{-}Yu Huang and
Kuang{-}Chien Chen and
Kwang{-}Ting Cheng},
title = {AutoFix: a hybrid tool for automatic logic rectification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1376--1384},
year = {1999},
url = {https://doi.org/10.1109/43.784128},
doi = {10.1109/43.784128},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HuangCC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HulgaardWA99,
author = {Henrik Hulgaard and
Poul Frederick Williams and
Henrik Reif Andersen},
title = {Equivalence checking of combinational circuits using Boolean expression
diagrams},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {903--917},
year = {1999},
url = {https://doi.org/10.1109/43.771175},
doi = {10.1109/43.771175},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HulgaardWA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JohnsonSR99,
author = {Mark C. Johnson and
Dinesh Somasekhar and
Kaushik Roy},
title = {Models and algorithms for bounds on leakage in {CMOS} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {714--725},
year = {1999},
url = {https://doi.org/10.1109/43.766723},
doi = {10.1109/43.766723},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JohnsonSR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KagarisT99,
author = {Dimitrios Kagaris and
Spyros Tragoudas},
title = {On the design of optimal counter-based schemes for test set embedding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {219--230},
year = {1999},
url = {https://doi.org/10.1109/43.743738},
doi = {10.1109/43.743738},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KagarisT99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngRSZ99,
author = {Andrew B. Kahng and
Gabriel Robins and
Anish Singh and
Alexander Zelikovsky},
title = {Filling algorithms and analyses for layout density control},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {445--462},
year = {1999},
url = {https://doi.org/10.1109/43.752928},
doi = {10.1109/43.752928},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngRSZ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KhouriLJ99,
author = {Kamal S. Khouri and
Ganesh Lakshminarayana and
Niraj K. Jha},
title = {High-level synthesis of low-power control-flow intensive circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1715--1729},
year = {1999},
url = {https://doi.org/10.1109/43.811321},
doi = {10.1109/43.811321},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KhouriLJ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimC99,
author = {Von{-}Kyoung Kim and
Tom Chen},
title = {On comparing functional fault coverage and defect coverage for memory
testing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1676--1683},
year = {1999},
url = {https://doi.org/10.1109/43.806812},
doi = {10.1109/43.806812},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KirovskiLPM99,
author = {Darko Kirovski and
Chunho Lee and
Miodrag Potkonjak and
William H. Mangione{-}Smith},
title = {Application-driven synthesis of memory-intensive systems-on-chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1316--1326},
year = {1999},
url = {https://doi.org/10.1109/43.784123},
doi = {10.1109/43.784123},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KirovskiLPM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KirovskiPG99,
author = {Darko Kirovski and
Miodrag Potkonjak and
Lisa M. Guerra},
title = {Improving the observability and controllability of datapaths foremulation-based
debugging},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1529--1541},
year = {1999},
url = {https://doi.org/10.1109/43.806800},
doi = {10.1109/43.806800},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KirovskiPG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KnudsenM99,
author = {Peter Voigt Knudsen and
Jan Madsen},
title = {Integrating communication protocol selection with hardware/software
codesign},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1077--1095},
year = {1999},
url = {https://doi.org/10.1109/43.775629},
doi = {10.1109/43.775629},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KnudsenM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Konuk99,
author = {Haluk Konuk},
title = {Voltage- and current-based fault simulation for interconnect open
defects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1768--1779},
year = {1999},
url = {https://doi.org/10.1109/43.811326},
doi = {10.1109/43.811326},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Konuk99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KrsticCC99,
author = {Angela Krstic and
Kwang{-}Ting Cheng and
Srimat T. Chakradhar},
title = {Primitive delay faults: identification, testing, and design for testability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {669--684},
year = {1999},
url = {https://doi.org/10.1109/43.766720},
doi = {10.1109/43.766720},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KrsticCC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LakshminarayanaJ99,
author = {Ganesh Lakshminarayana and
Niraj K. Jha},
title = {High-level synthesis of power-optimized and area-optimized circuits
from hierarchical data-flow intensive behaviors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {3},
pages = {265--281},
year = {1999},
url = {https://doi.org/10.1109/43.748157},
doi = {10.1109/43.748157},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LakshminarayanaJ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LakshminarayanaJ99a,
author = {Ganesh Lakshminarayana and
Niraj K. Jha},
title = {{FACT:} a framework for applying throughput and power optimizing transformations
to control-flow-intensive behavioral descriptions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1577--1594},
year = {1999},
url = {https://doi.org/10.1109/43.806804},
doi = {10.1109/43.806804},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LakshminarayanaJ99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LakshminarayanaKJ99,
author = {Ganesh Lakshminarayana and
Kamal S. Khouri and
Niraj K. Jha},
title = {Wavesched: a novel scheduling technique for control-flow intensive
designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {505--523},
year = {1999},
url = {https://doi.org/10.1109/43.759064},
doi = {10.1109/43.759064},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LakshminarayanaKJ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeCH99,
author = {Kuen{-}Jong Lee and
Jih{-}Jeen Chen and
Cheng{-}Hua Huang},
title = {Broadcasting test patterns to multiple circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1793--1802},
year = {1999},
url = {https://doi.org/10.1109/43.811328},
doi = {10.1109/43.811328},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeCH99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LekatsasW99,
author = {Haris Lekatsas and
Wayne H. Wolf},
title = {{SAMC:} a code compression algorithm for embedded processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1689--1701},
year = {1999},
url = {https://doi.org/10.1109/43.811316},
doi = {10.1109/43.811316},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LekatsasW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiW99,
author = {Yanbing Li and
Wayne H. Wolf},
title = {Hardware/software co-synthesis with memory hierarchies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1405--1417},
year = {1999},
url = {https://doi.org/10.1109/43.790618},
doi = {10.1109/43.790618},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LillisC99,
author = {John Lillis and
Chung{-}Kuan Cheng},
title = {Timing optimization for multisource nets: characterization andoptimal
repeater insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {3},
pages = {322--331},
year = {1999},
url = {https://doi.org/10.1109/43.748162},
doi = {10.1109/43.748162},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LillisC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinCM99,
author = {Chih{-}Chang Lin and
Kuang{-}Chien Chen and
Malgorzata Marek{-}Sadowska},
title = {Logic synthesis for engineering change},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {3},
pages = {282--292},
year = {1999},
url = {https://doi.org/10.1109/43.748158},
doi = {10.1109/43.748158},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinCM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinH99,
author = {How{-}Rern Lin and
TingTing Hwang},
title = {On determining sensitization criterion in an iterative gate sizing
process},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {231--238},
year = {1999},
url = {https://doi.org/10.1109/43.743742},
doi = {10.1109/43.743742},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinH99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LindermeirGA99,
author = {Walter M. Lindermeir and
Helmut E. Graeb and
Kurt Antreich},
title = {Analog testing by characteristic observation inference},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1353--1368},
year = {1999},
url = {https://doi.org/10.1109/43.784126},
doi = {10.1109/43.784126},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LindermeirGA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinharesYT99,
author = {Alexandre Linhares and
Horacio Hideki Yanasse and
Jos{\'{e}} Ricardo de Almeida Torreao},
title = {Linear gate assignment: a fast statistical mechanics approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1750--1758},
year = {1999},
url = {https://doi.org/10.1109/43.811324},
doi = {10.1109/43.811324},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinharesYT99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuS99,
author = {Le{-}Chin Eugene Liu and
Carl Sechen},
title = {Multilayer chip-level global routing using an efficient graph-based
Steiner tree heuristic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1442--1451},
year = {1999},
url = {https://doi.org/10.1109/43.790621},
doi = {10.1109/43.790621},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LokanathanB99,
author = {Arun N. Lokanathan and
Jay B. Brockman},
title = {A methodology for concurrent process-circuit optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {889--902},
year = {1999},
url = {https://doi.org/10.1109/43.771174},
doi = {10.1109/43.771174},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LokanathanB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaheshwariS99,
author = {Naresh Maheshwari and
Sachin S. Sapatnekar},
title = {Optimizing large multiphase level-clocked circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1249--1264},
year = {1999},
url = {https://doi.org/10.1109/43.784118},
doi = {10.1109/43.784118},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaheshwariS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaierETBK99,
author = {Christoph Maier and
Markus Emmenegger and
Stefano Taschini and
Henry Baltes and
Jan G. Korvink},
title = {Equivalent circuit model of resistive {IC} sensors derived with the
box integration method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {1000--1013},
year = {1999},
url = {https://doi.org/10.1109/43.771181},
doi = {10.1109/43.771181},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaierETBK99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarculescuMP99,
author = {Radu Marculescu and
Diana Marculescu and
Massoud Pedram},
title = {Sequence compaction for power estimation: theory and practice},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {973--993},
year = {1999},
url = {https://doi.org/10.1109/43.771179},
doi = {10.1109/43.771179},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MarculescuMP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MathewS99,
author = {Ben Mathew and
Daniel G. Saab},
title = {Combining multiple {DFT} schemes with test generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {685--696},
year = {1999},
url = {https://doi.org/10.1109/43.766721},
doi = {10.1109/43.766721},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MathewS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MesmanTMJ99,
author = {Bart Mesman and
Adwin H. Timmer and
Jef L. van Meerbergen and
Jochen A. G. Jess},
title = {Constraint analysis for {DSP} code generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {1},
pages = {44--57},
year = {1999},
url = {https://doi.org/10.1109/43.739058},
doi = {10.1109/43.739058},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MesmanTMJ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MeyassedKA99,
author = {Moshe Meyassed and
Robert H. Klenke and
James H. Aylor},
title = {Resolving unknown inputs in mixed-level simulation with sequential
elements},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1151--1164},
year = {1999},
url = {https://doi.org/10.1109/43.775634},
doi = {10.1109/43.775634},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MeyassedKA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MitraAM99,
author = {Subhasish Mitra and
LaNae J. Avra and
Edward J. McCluskey},
title = {An output encoding problem and a solution technique},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {761--768},
year = {1999},
url = {https://doi.org/10.1109/43.766726},
doi = {10.1109/43.766726},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MitraAM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukherjeeJTFAF99,
author = {Rajarshi Mukherjee and
Jawahar Jain and
Koichiro Takayama and
Masahiro Fujita and
Jacob A. Abraham and
Donald S. Fussell},
title = {An efficient filter-based approach for combinational verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1542--1557},
year = {1999},
url = {https://doi.org/10.1109/43.806801},
doi = {10.1109/43.806801},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukherjeeJTFAF99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MyersRM99,
author = {Chris J. Myers and
Tomas Rokicki and
Teresa H.{-}Y. Meng},
title = {{POSET} timing and its application to the synthesis and verification
of gate-level timed circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {769--786},
year = {1999},
url = {https://doi.org/10.1109/43.766727},
doi = {10.1109/43.766727},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MyersRM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NemaniN99,
author = {Mahadevamurty Nemani and
Farid N. Najm},
title = {High-level area and power estimation for {VLSI} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {697--713},
year = {1999},
url = {https://doi.org/10.1109/43.766722},
doi = {10.1109/43.766722},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NemaniN99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NetzelHBS99,
author = {Mario Netzel and
Bernd Heinemann and
Maik Brett and
Dagmar Schipanski},
title = {Methods for generating and editing merged isotropic/anisotropic triangular-element
meshes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1566--1576},
year = {1999},
url = {https://doi.org/10.1109/43.806803},
doi = {10.1109/43.806803},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NetzelHBS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NiewczasMS99,
author = {Mariusz Niewczas and
Wojciech Maly and
Andrzej J. Strojwas},
title = {An algorithm for determining repetitive patterns in very large {IC}
layouts},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {494--501},
year = {1999},
url = {https://doi.org/10.1109/43.752932},
doi = {10.1109/43.752932},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NiewczasMS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PandaDN99,
author = {Preeti Ranjan Panda and
Nikil D. Dutt and
Alexandru Nicolau},
title = {Local memory exploration and optimization in embedded systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {1},
pages = {3--13},
year = {1999},
url = {https://doi.org/10.1109/43.739054},
doi = {10.1109/43.739054},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PandaDN99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PandeyB99,
author = {Manish Pandey and
Randal E. Bryant},
title = {Exploiting symmetry when verifying transistor-level circuits by symbolic
trajectory evaluation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {918--935},
year = {1999},
url = {https://doi.org/10.1109/43.771176},
doi = {10.1109/43.771176},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PandeyB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PandeyUW99,
author = {Sheetanshu L. Pandey and
Kothanda Umamageswaran and
Philip A. Wilsey},
title = {{VHDL} semantics and validating transformations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {936--955},
year = {1999},
url = {https://doi.org/10.1109/43.771177},
doi = {10.1109/43.771177},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PandeyUW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PapadopoulouL99,
author = {Evanthia Papadopoulou and
D. T. Lee},
title = {Critical area computation via Voronoi diagrams},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {463--474},
year = {1999},
url = {https://doi.org/10.1109/43.752929},
doi = {10.1109/43.752929},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PapadopoulouL99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PaskoSDVD99,
author = {Robert Pasko and
Patrick Schaumont and
Veerle Derudder and
Serge Vernalde and
Daniela Durackov{\'{a}}},
title = {A new algorithm for elimination of common subexpressions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {1},
pages = {58--68},
year = {1999},
url = {https://doi.org/10.1109/43.739059},
doi = {10.1109/43.739059},
timestamp = {Mon, 04 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PaskoSDVD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Patil99,
author = {Mahesh B. Patil},
title = {Extension of the {VR} discretization scheme for velocity saturation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1508--1511},
year = {1999},
url = {https://doi.org/10.1109/43.790627},
doi = {10.1109/43.790627},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Patil99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PedramP99,
author = {Massoud Pedram and
Bryan Preas},
title = {Interconnection analysis for standard cell layouts},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1512--1519},
year = {1999},
url = {https://doi.org/10.1109/43.790628},
doi = {10.1109/43.790628},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PedramP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PenaO99,
author = {Jorge M. Pena and
Arlindo L. Oliveira},
title = {A new algorithm for exact reduction of incompletely specified finite
state machines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1619--1632},
year = {1999},
url = {https://doi.org/10.1109/43.806807},
doi = {10.1109/43.806807},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PenaO99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PendurkarTC99,
author = {Rajesh Pendurkar and
Craig A. Tovey and
Abhijit Chatterjee},
title = {Single-probe traversal optimization for testing of {MCM} substrate
interconnections},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1178--1191},
year = {1999},
url = {https://doi.org/10.1109/43.775636},
doi = {10.1109/43.775636},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PendurkarTC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PhamN99,
author = {Hoan H. Pham and
Arokia Nathan},
title = {An integral equation of the second kind for computation of capacitance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1435--1441},
year = {1999},
url = {https://doi.org/10.1109/43.790620},
doi = {10.1109/43.790620},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PhamN99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PiazzaKJ99,
author = {Alfredo J. Piazza and
Can E. Korman and
Amro M. Jaradeh},
title = {A physics-based semiconductor noise model suitable for efficient numerical
implementation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1730--1740},
year = {1999},
url = {https://doi.org/10.1109/43.811322},
doi = {10.1109/43.811322},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PiazzaKJ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PleskaczOM99,
author = {Witold A. Pleskacz and
Charles H. Ouyang and
Wojciech Maly},
title = {A DRC-based algorithm for extraction of critical areas for opens in
large {VLSI} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {151--162},
year = {1999},
url = {https://doi.org/10.1109/43.743724},
doi = {10.1109/43.743724},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PleskaczOM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A comment on "Improving a nonenumerative method to estimate path delay
fault coverage"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {665--666},
year = {1999},
url = {https://doi.org/10.1109/43.759083},
doi = {10.1109/43.759083},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzRG99,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Ruifeng Guo},
title = {Static test compaction for synchronous sequential circuits based on
vector restoration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {1040--1049},
year = {1999},
url = {https://doi.org/10.1109/43.771184},
doi = {10.1109/43.771184},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzRG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PotkonjakR99,
author = {Miodrag Potkonjak and
Jan M. Rabaey},
title = {Algorithm selection: a quantitative optimization-intensive approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {524--532},
year = {1999},
url = {https://doi.org/10.1109/43.759065},
doi = {10.1109/43.759065},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PotkonjakR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PradhanC99,
author = {Dhiraj K. Pradhan and
Mitrajit Chatterjee},
title = {GLFSR-a new test pattern generator for built-in-self-test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {238--247},
year = {1999},
url = {https://doi.org/10.1109/43.743744},
doi = {10.1109/43.743744},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PradhanC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PykaFHS99,
author = {Wolfgang Pyka and
Peter Fleischmann and
Bernhard Haindl and
Siegfried Selberherr},
title = {Three-dimensional simulation of HPCVD-linking continuum transport
and reaction kinetics with topography simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1741--1749},
year = {1999},
url = {https://doi.org/10.1109/43.811323},
doi = {10.1109/43.811323},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PykaFHS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaghunathanDJ99,
author = {Anand Raghunathan and
Sujit Dey and
Niraj K. Jha},
title = {Register transfer level power optimization with emphasis on glitch
analysis and reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1114--1131},
year = {1999},
url = {https://doi.org/10.1109/43.775632},
doi = {10.1109/43.775632},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RaghunathanDJ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SalekLP99,
author = {Amir H. Salek and
Jinan Lou and
Massoud Pedram},
title = {An integrated logical and physical design flow for deep submicron
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1305--1315},
year = {1999},
url = {https://doi.org/10.1109/43.784122},
doi = {10.1109/43.784122},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SalekLP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchollMMD99,
author = {Christoph Scholl and
Dirk M{\"{o}}ller and
Paul Molitor and
Rolf Drechsler},
title = {{BDD} minimization using symmetries},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {81--100},
year = {1999},
url = {https://doi.org/10.1109/43.743706},
doi = {10.1109/43.743706},
timestamp = {Wed, 03 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SchollMMD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeifiPV99,
author = {Abbas Seifi and
Kumaraswamy Ponnambalam and
Jir{\'{\i}} Vlach},
title = {Probabilistic design of integrated circuits with correlated input
parameters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1214--1219},
year = {1999},
url = {https://doi.org/10.1109/43.775639},
doi = {10.1109/43.775639},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeifiPV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShepardNR99,
author = {Kenneth L. Shepard and
Vinod Narayanan and
Ron Rose},
title = {Harmony: static noise analysis of deep submicron digital integrated
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1132--1150},
year = {1999},
url = {https://doi.org/10.1109/43.775633},
doi = {10.1109/43.775633},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShepardNR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuWL99,
author = {Hsiao{-}Pin Su and
Allen C.{-}H. Wu and
Youn{-}Long Lin},
title = {A timing-driven soft-macro placement and resynthesis method in interaction
with chip floorplanning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {475--483},
year = {1999},
url = {https://doi.org/10.1109/43.752930},
doi = {10.1109/43.752930},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuWL99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TaharSCZLM99,
author = {Sofi{\`{e}}ne Tahar and
Xiaoyu Song and
Eduard Cerny and
Zijian Zhou and
Michel Langevin and
Otmane A{\"{\i}}t Mohamed},
title = {Modeling and formal verification of the Fairisle {ATM} switch fabricusing
MDGs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {956--972},
year = {1999},
url = {https://doi.org/10.1109/43.771178},
doi = {10.1109/43.771178},
timestamp = {Mon, 18 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/TaharSCZLM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangSW99,
author = {Qian{-}Yu Tang and
Xiaoyu Song and
Yuke Wang},
title = {Diagnosis of clustered faults for identical degree topologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1192--1201},
year = {1999},
url = {https://doi.org/10.1109/43.775637},
doi = {10.1109/43.775637},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangSW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ToubaM99,
author = {Nur A. Touba and
Edward J. McCluskey},
title = {{RP-SYN:} synthesis of random pattern testable circuits with test
point insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1202--1213},
year = {1999},
url = {https://doi.org/10.1109/43.775638},
doi = {10.1109/43.775638},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ToubaM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TragoudasK99,
author = {Spyros Tragoudas and
Dimitrios Karayiannis},
title = {A fast nonenumerative automatic test pattern generator for pathdelay
faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {1050--1057},
year = {1999},
url = {https://doi.org/10.1109/43.771185},
doi = {10.1109/43.771185},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TragoudasK99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TsengS99,
author = {Hsiao{-}Ping Tseng and
Carl Sechen},
title = {A gridless multilayer router for standard cell circuits using CTMcells},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1462--1479},
year = {1999},
url = {https://doi.org/10.1109/43.790623},
doi = {10.1109/43.790623},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TsengS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Vahid99,
author = {Frank Vahid},
title = {Techniques for minimizing and balancing {I/O} during functional partitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {1},
pages = {69--75},
year = {1999},
url = {https://doi.org/10.1109/43.739060},
doi = {10.1109/43.739060},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Vahid99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VaishnavP99,
author = {Hirendu Vaishnav and
Massoud Pedram},
title = {Delay-optimal clustering targeting low-power {VLSI} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {799--812},
year = {1999},
url = {https://doi.org/10.1109/43.766729},
doi = {10.1109/43.766729},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VaishnavP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VenerisH99,
author = {Andreas G. Veneris and
Ibrahim N. Hajj},
title = {Design error diagnosis and correction via test vector simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1803--1816},
year = {1999},
url = {https://doi.org/10.1109/43.811329},
doi = {10.1109/43.811329},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VenerisH99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VittalCMWY99,
author = {Ashok Vittal and
Lauren Hui Chen and
Malgorzata Marek{-}Sadowska and
Kai{-}Ping Wang and
Sherry Yang},
title = {Crosstalk in {VLSI} interconnections},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {12},
pages = {1817--1824},
year = {1999},
url = {https://doi.org/10.1109/43.811330},
doi = {10.1109/43.811330},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VittalCMWY99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuA99,
author = {Yuejian Wu and
Saman Adham},
title = {Scan-based {BIST} fault diagnosis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {203--211},
year = {1999},
url = {https://doi.org/10.1109/43.743733},
doi = {10.1109/43.743733},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuytackSCJY99,
author = {Sven Wuytack and
Julio Leao da Silva Jr. and
Francky Catthoor and
Gjalt G. de Jong and
Chantal Ykman{-}Couvreur},
title = {Memory management for embedded network applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {533--544},
year = {1999},
url = {https://doi.org/10.1109/43.759067},
doi = {10.1109/43.759067},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuytackSCJY99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XieB99,
author = {Aiguo Xie and
Peter A. Beerel},
title = {Accelerating Markovian analysis of asynchronous systems using state
compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {869--888},
year = {1999},
url = {https://doi.org/10.1109/43.771173},
doi = {10.1109/43.771173},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XieB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuGC99,
author = {Jin Xu and
Pei{-}Ning Guo and
Chung{-}Kuan Cheng},
title = {Sequence-pair approach for rectilinear module placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {4},
pages = {484--493},
year = {1999},
url = {https://doi.org/10.1109/43.752931},
doi = {10.1109/43.752931},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuGC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YamagamiNUTO99,
author = {Yoshihiro Yamagami and
Yoshifumi Nishio and
Akio Ushida and
Masayuki Takahashi and
Kimihiro Ogawa},
title = {Analysis of communication circuits based on multidimensional Fourier
transformation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {8},
pages = {1165--1177},
year = {1999},
url = {https://doi.org/10.1109/43.775635},
doi = {10.1109/43.775635},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YamagamiNUTO99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Yan99,
author = {Jin{-}Tai Yan},
title = {An improved optimal algorithm for bubble-sorting-basednon-Manhattan
channel routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {163--171},
year = {1999},
url = {https://doi.org/10.1109/43.743726},
doi = {10.1109/43.743726},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Yan99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Yan99a,
author = {Jin{-}Tai Yan},
title = {An efficient cut-based algorithm on minimizing the number of L-shaped
channels for safe routing ordering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {10},
pages = {1519--1526},
year = {1999},
url = {https://doi.org/10.1109/43.790629},
doi = {10.1109/43.790629},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Yan99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YoungWY99,
author = {Evangeline F. Y. Young and
Martin D. F. Wong and
Hannah Honghua Yang},
title = {Slicing floorplans with boundary constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1385--1389},
year = {1999},
url = {https://doi.org/10.1109/43.784129},
doi = {10.1109/43.784129},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YoungWY99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YunD99,
author = {Kenneth Y. Yun and
David L. Dill},
title = {Automatic synthesis of extended burst-mode circuits. I.(Specification
and hazard-free implementations)},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {101--117},
year = {1999},
url = {https://doi.org/10.1109/43.743711},
doi = {10.1109/43.743711},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YunD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YunD99a,
author = {Kenneth Y. Yun and
David L. Dill},
title = {Automatic synthesis of extended burst-mode circuits. {II.} (Automaticsynthesis)},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {118--132},
year = {1999},
url = {https://doi.org/10.1109/43.743715},
doi = {10.1109/43.743715},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YunD99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZemanianC99,
author = {Armen H. Zemanian and
Victor A. Chang},
title = {Exterior templates for capacitance computations [interconnections]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {248--251},
year = {1999},
url = {https://doi.org/10.1109/43.743747},
doi = {10.1109/43.743747},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZemanianC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhongMAM99,
author = {Peixin Zhong and
Margaret Martonosi and
Pranav Ashar and
Sharad Malik},
title = {Using configurable computing to accelerate Boolean satisfiability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {6},
pages = {861--868},
year = {1999},
url = {https://doi.org/10.1109/43.766733},
doi = {10.1109/43.766733},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhongMAM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouW99,
author = {Hai Zhou and
Martin D. F. Wong},
title = {Global routing with crosstalk constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {11},
pages = {1683--1688},
year = {1999},
url = {https://doi.org/10.1109/43.806813},
doi = {10.1109/43.806813},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhouW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZienSC99,
author = {Jason Y. Zien and
Martine D. F. Schlag and
Pak K. Chan},
title = {Multilevel spectral hypergraph partitioning with arbitrary vertex
sizes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {9},
pages = {1389--1399},
year = {1999},
url = {https://doi.org/10.1109/43.784130},
doi = {10.1109/43.784130},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZienSC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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