Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSearch dblp for Publications
export results for "toc:db/journals/tcad/tcad21.bht:"
download as .bib file
@article{DBLP:journals/tcad/AcarDP02,
author = {Emrah Acar and
Florentin Dartu and
Lawrence T. Pileggi},
title = {{TETA:} transistor-level waveform evaluation for timing analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {605--616},
year = {2002},
url = {https://doi.org/10.1109/43.998631},
doi = {10.1109/43.998631},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AcarDP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AkturanJ02,
author = {Cagdas Akturan and
Margarida F. Jacome},
title = {{RS-FDRA:} {A} register-sensitive software pipelining algorithm for
embedded {VLIW} processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1395--1415},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804373},
doi = {10.1109/TCAD.2002.804373},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AkturanJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Alippi02,
author = {Cesare Alippi},
title = {A probably approximately correct framework to estimate performancedegradation
in embedded systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {749--762},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013889},
doi = {10.1109/TCAD.2002.1013889},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Alippi02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertDFQ02,
author = {Charles J. Alpert and
Anirudh Devgan and
John P. Fishburn and
Stephen T. Quay},
title = {Correction to "interconnect synthesis without wire tapering"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {4},
pages = {497--497},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.992775},
doi = {10.1109/TCAD.2002.992775},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertDFQ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BanerjeeM02,
author = {Kaustav Banerjee and
Amit Mehrotra},
title = {Analysis of on-chip inductance effects for distributed {RLC} interconnects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {904--915},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800459},
doi = {10.1109/TCAD.2002.800459},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BanerjeeM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Bergamaschi02,
author = {Reinaldo A. Bergamaschi},
title = {Bridging the domains of high-level and logic synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {582--596},
year = {2002},
url = {https://doi.org/10.1109/43.998629},
doi = {10.1109/43.998629},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Bergamaschi02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BhattacharyaDGC02,
author = {Bhargab B. Bhattacharya and
Alexej Dmitriev and
Michael G{\"{o}}ssel and
Krishnendu Chakrabarty},
title = {Synthesis of single-output space compactors for scan-based sequential
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1171--1179},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802275},
doi = {10.1109/TCAD.2002.802275},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BhattacharyaDGC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BlaauwZS02,
author = {David T. Blaauw and
Vladimir Zolotov and
Savithri Sundareswaran},
title = {Slope propagation in static timing analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1180--1195},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802274},
doi = {10.1109/TCAD.2002.802274},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BlaauwZS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrandoleseSFS02,
author = {Carlo Brandolese and
Fabio Salice and
William Fornaciari and
Donatella Sciuto},
title = {Static power modeling of 32-bit microprocessors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1306--1316},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804104},
doi = {10.1109/TCAD.2002.804104},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrandoleseSFS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChanSK02,
author = {Steven C. Chan and
Kenneth L. Shepard and
Dae{-}Jin Kim},
title = {Static noise analysis for digital integrated circuits in partially
depleted silicon-on-insulator technology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {916--927},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800461},
doi = {10.1109/TCAD.2002.800461},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChanSK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChandraC02,
author = {Anshuman Chandra and
Krishnendu Chakrabarty},
title = {Low-power scan testing and test data compression forsystem-on-a-chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {597--604},
year = {2002},
url = {https://doi.org/10.1109/43.998630},
doi = {10.1109/43.998630},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChandraC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChandraC02a,
author = {Anshuman Chandra and
Krishnendu Chakrabarty},
title = {Test data compression and decompression based on internal scanchains
and Golomb coding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {715--722},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004315},
doi = {10.1109/TCAD.2002.1004315},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChandraC02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenGB02,
author = {Wei{-}Yu Chen and
Sandeep K. Gupta and
Melvin A. Breuer},
title = {Analytical models for crosstalk excitation and propagation in {VLSI}
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1117--1131},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802276},
doi = {10.1109/TCAD.2002.802276},
timestamp = {Thu, 21 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenGB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenKRZ02,
author = {Yu Chen and
Andrew B. Kahng and
Gabriel Robins and
Alexander Zelikovsky},
title = {Area fill synthesis for uniform layout density},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1132--1147},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802278},
doi = {10.1109/TCAD.2002.802278},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenKRZ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenYS02,
author = {Chunhong Chen and
Xiaojian Yang and
Majid Sarrafzadeh},
title = {Predicting potential performance for digital circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {3},
pages = {253--262},
year = {2002},
url = {https://doi.org/10.1109/43.986420},
doi = {10.1109/43.986420},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenYS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengTW02,
author = {Kuo{-}Liang Cheng and
Ming{-}Fu Tsai and
Cheng{-}Wen Wu},
title = {Neighborhood pattern-sensitive fault testing and diagnostics for random-access
memories},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1328--1336},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804101},
doi = {10.1109/TCAD.2002.804101},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengTW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouL02,
author = {Yih{-}Chih Chou and
Youn{-}Long Lin},
title = {Effective enforcement of path-delay constraints inperformance-driven
placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {1},
pages = {15--22},
year = {2002},
url = {https://doi.org/10.1109/43.974133},
doi = {10.1109/43.974133},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChouL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChungLDLC02,
author = {Eui{-}Young Chung and
Luca Benini and
Giovanni De Micheli and
Gabriele Luculli and
Marco Carilli},
title = {Value-sensitive automatic code specialization for embedded software},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1051--1067},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801096},
doi = {10.1109/TCAD.2002.801096},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChungLDLC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CiesielskiAL02,
author = {Maciej J. Ciesielski and
Serkan Askar and
Samuel Levitin},
title = {Analytical approach to layout generation of datapath cells},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1480--1488},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804376},
doi = {10.1109/TCAD.2002.804376},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CiesielskiAL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongP02,
author = {Jason Cong and
David Zhigang Pan},
title = {Wire width planning for interconnect performance optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {3},
pages = {319--329},
year = {2002},
url = {https://doi.org/10.1109/43.986425},
doi = {10.1109/43.986425},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CortadellaKBKLSTY02,
author = {Jordi Cortadella and
Michael Kishinevsky and
Steven M. Burns and
Alex Kondratyev and
Luciano Lavagno and
Ken S. Stevens and
Alexander Taubin and
Alexandre Yakovlev},
title = {Lazy transition systems and asynchronous circuit synthesis withrelative
timing assumptions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {109--130},
year = {2002},
url = {https://doi.org/10.1109/43.980253},
doi = {10.1109/43.980253},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CortadellaKBKLSTY02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CrippaTC02,
author = {Paolo Crippa and
Claudio Turchetti and
Massimo Conti},
title = {A statistical methodology for the design of high-performance CMOScurrent-steering
digital-to-analog converters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {4},
pages = {377--394},
year = {2002},
url = {https://doi.org/10.1109/43.992761},
doi = {10.1109/43.992761},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CrippaTC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DaemsGS02,
author = {Walter Daems and
Georges G. E. Gielen and
Willy M. C. Sansen},
title = {Circuit simplification for the symbolic analysis of analogintegrated
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {4},
pages = {395--407},
year = {2002},
url = {https://doi.org/10.1109/43.992763},
doi = {10.1109/43.992763},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DaemsGS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasK02,
author = {Sabyasachi Das and
Sunil P. Khatri},
title = {An efficient and regular routing methodology for datapath designsusing
net regularity extraction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {1},
pages = {93--101},
year = {2002},
url = {https://doi.org/10.1109/43.974141},
doi = {10.1109/43.974141},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DasK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DraganKMMZ02,
author = {Feodor F. Dragan and
Andrew B. Kahng and
Ion I. Mandoiu and
Sudhakar Muddu and
Alexander Zelikovsky},
title = {Provably good global buffering by generalized multiterminalmulticommodity
flow approximation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {3},
pages = {263--274},
year = {2002},
url = {https://doi.org/10.1109/43.986421},
doi = {10.1109/43.986421},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DraganKMMZ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Edwards02,
author = {Stephen A. Edwards},
title = {An Esterel compiler for large control-dominated systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {169--183},
year = {2002},
url = {https://doi.org/10.1109/43.980257},
doi = {10.1109/43.980257},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Edwards02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EoSE02,
author = {Yungseon Eo and
Jongin Shim and
William R. Eisenstadt},
title = {A traveling-wave-based waveform approximation technique for thetiming
verification of single transmission lines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {723--730},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004316},
doi = {10.1109/TCAD.2002.1004316},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EoSE02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EoSES02,
author = {Yungseon Eo and
Seongkyun Shin and
William R. Eisenstadt and
Jongin Shim},
title = {Generalized traveling-wave-based waveform approximation technique
for the efficient signal integrity verification of multicoupled transmission
line system},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1489--1497},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804381},
doi = {10.1109/TCAD.2002.804381},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EoSES02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EvmorfopoulosSA02,
author = {Nestoras E. Evmorfopoulos and
Georgios I. Stamoulis and
John N. Avaritsiotis},
title = {A Monte Carlo approach for maximum power estimation based onextreme
value theory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {4},
pages = {415--432},
year = {2002},
url = {https://doi.org/10.1109/43.992765},
doi = {10.1109/43.992765},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EvmorfopoulosSA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FavalliD02,
author = {Michele Favalli and
Marcello Dalpasso},
title = {Bridging fault modeling and simulation for deep submicron {CMOS} ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {941--953},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800457},
doi = {10.1109/TCAD.2002.800457},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FavalliD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FerreF02,
author = {Antoni Ferr{\'{e}} and
Joan Figueras},
title = {Leakage power bounds in {CMOS} digital technologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {731--738},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004317},
doi = {10.1109/TCAD.2002.1004317},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FerreF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GaoLBCO02,
author = {Xiaofang Gao and
Juin J. Liou and
Joe Bernier and
Gregg D. Croft and
Adelmo Ortiz{-}Conde},
title = {Implementation of a comprehensive and robust {MOSFET} model in cadence
{SPICE} for {ESD} applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1497--1502},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804379},
doi = {10.1109/TCAD.2002.804379},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GaoLBCO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GivargisV02,
author = {Tony Givargis and
Frank Vahid},
title = {Platune: a tuning framework for system-on-a-chip platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1317--1327},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804107},
doi = {10.1109/TCAD.2002.804107},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GivargisV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GizdarskiF02,
author = {Emil Gizdarski and
Hideo Fujiwara},
title = {{SPIRIT:} a highly robust combinational test generation algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1446--1458},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804387},
doi = {10.1109/TCAD.2002.804387},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GizdarskiF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GnaniGVCR02,
author = {Elena Gnani and
Vincenzo Giudicissi and
Radu Vissarion and
Claudio Contiero and
Massimo Rudan},
title = {Automatic 2-D and 3-D simulation of parasitic structures insmart-power
integrated circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {791--798},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013892},
doi = {10.1109/TCAD.2002.1013892},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GnaniGVCR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GopalakrishnanOPR02,
author = {Padmini Gopalakrishnan and
Altan Odabasioglu and
Lawrence T. Pileggi and
Salil Raje},
title = {An analysis of the wire-load model uncertainty problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {1},
pages = {23--31},
year = {2002},
url = {https://doi.org/10.1109/43.974134},
doi = {10.1109/43.974134},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GopalakrishnanOPR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Guo02,
author = {Yu{-}Shun Guo},
title = {Transient simulation of high-speed interconnects based on thesemidiscretization
of Telegrapher's equations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {799--809},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013893},
doi = {10.1109/TCAD.2002.1013893},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Guo02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HamdiouiG02,
author = {Said Hamdioui and
Ad J. van de Goor},
title = {Thorough testing of any multiport memory with linear tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {217--231},
year = {2002},
url = {https://doi.org/10.1109/43.980260},
doi = {10.1109/43.980260},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HamdiouiG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HarrisT02,
author = {Ian G. Harris and
Russell Tessier},
title = {Testing and diagnosis of interconnect faults in cluster-based {FPGA}
architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1337--1343},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804108},
doi = {10.1109/TCAD.2002.804108},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HarrisT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HeraguSKB02,
author = {Keerthi Heragu and
Manish Sharma and
Rahul Kundu and
Ronald D. Blanton},
title = {Test vector generation for charge sharing failures in dynamic logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1502--1508},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804377},
doi = {10.1109/TCAD.2002.804377},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HeraguSKB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehP02,
author = {Cheng{-}Ta Hsieh and
Massoud Pedram},
title = {Architectural energy optimization by bus splitting},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {4},
pages = {408--414},
year = {2002},
url = {https://doi.org/10.1109/43.992764},
doi = {10.1109/43.992764},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiehP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuS02,
author = {Jiang Hu and
Sachin S. Sapatnekar},
title = {A timing-constrained simultaneous global routing algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1025--1036},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801083},
doi = {10.1109/TCAD.2002.801083},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangJ02,
author = {Der{-}Cheng Huang and
Wen{-}Ben Jone},
title = {A parallel built-in self-diagnostic method for embedded memoryarrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {4},
pages = {449--465},
year = {2002},
url = {https://doi.org/10.1109/43.992768},
doi = {10.1109/43.992768},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangJ02a,
author = {Der{-}Cheng Huang and
Wen{-}Ben Jone},
title = {A parallel transparent {BIST} method for embedded memory arrays bytolerating
redundant operations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {617--628},
year = {2002},
url = {https://doi.org/10.1109/43.998632},
doi = {10.1109/43.998632},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangJ02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HungSAD02,
author = {William N. N. Hung and
Xiaoyu Song and
El Mostapha Aboulhamid and
Michael A. Driscoll},
title = {{BDD} minimization by scatter search},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {974--979},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800452},
doi = {10.1109/TCAD.2002.800452},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HungSAD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuttonRC02,
author = {Michael D. Hutton and
Jonathan Rose and
Derek G. Corneil},
title = {Automatic generation of synthetic sequential benchmark circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {928--940},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800456},
doi = {10.1109/TCAD.2002.800456},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuttonRC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IsmailF02,
author = {Yehea I. Ismail and
Eby G. Friedman},
title = {{DTT:} direct truncation of the transfer function - an alternative
tomoment matching for tree structured interconnect},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {131--144},
year = {2002},
url = {https://doi.org/10.1109/43.980254},
doi = {10.1109/43.980254},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IsmailF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IyengarC02,
author = {Vikram Iyengar and
Krishnendu Chakrabarty},
title = {System-on-a-chip test scheduling with precedence relationships, preemption,
and power constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1088--1094},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801102},
doi = {10.1109/TCAD.2002.801102},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/IyengarC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JacobsonM02,
author = {Hans M. Jacobson and
Chris J. Myers},
title = {Efficient algorithms for exact two-level hazard-free logic minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1269--1283},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804103},
doi = {10.1109/TCAD.2002.804103},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JacobsonM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangV02,
author = {Wanli Jiang and
Bapiraju Vinnakota},
title = {Statistical threshold formulation for dynamic I\({}_{\mbox{dd}}\)
test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {694--705},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004313},
doi = {10.1109/TCAD.2002.1004313},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungM02,
author = {Sung Tae Jung and
Chris J. Myers},
title = {Direct synthesis of timed circuits from free-choice STGs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {3},
pages = {275--290},
year = {2002},
url = {https://doi.org/10.1109/43.986422},
doi = {10.1109/43.986422},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Kagaris02,
author = {Dimitrios Kagaris},
title = {Linear dependencies in extended LFSMs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {852--859},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013897},
doi = {10.1109/TCAD.2002.1013897},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Kagaris02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KagarisT02,
author = {Dimitrios Kagaris and
Spyros Tragoudas},
title = {On the nonenumerative path delay fault simulation problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1095--1101},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801108},
doi = {10.1109/TCAD.2002.801108},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KagarisT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KallaC02,
author = {Priyank Kalla and
Maciej J. Ciesielski},
title = {A comprehensive approach to the partial scan problem using implicitstate
enumeration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {810--826},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013894},
doi = {10.1109/TCAD.2002.1013894},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KallaC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KarriIK02,
author = {Ramesh Karri and
Balakrishnan Iyer and
Israel Koren},
title = {Phantom redundancy: a register transfer level technique for gracefully
degradable data path synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {877--888},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800450},
doi = {10.1109/TCAD.2002.800450},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KarriIK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KarriWMK02,
author = {Ramesh Karri and
Kaijie Wu and
Piyush Mishra and
Yongkook Kim},
title = {Concurrent error detection schemes for fault-based side-channel cryptanalysis
of symmetric block ciphers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1509--1517},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804378},
doi = {10.1109/TCAD.2002.804378},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KarriWMK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KastnerBS02,
author = {Ryan Kastner and
Elaheh Bozorgzadeh and
Majid Sarrafzadeh},
title = {Pattern routing: use and theory for increasing predictability andavoiding
coupling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {777--790},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013891},
doi = {10.1109/TCAD.2002.1013891},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KastnerBS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KavousianosBNT02,
author = {Xrysovalantis Kavousianos and
Dimitris Bakalis and
Dimitris Nikolos and
Spyros Tragoudas},
title = {A new built-in {TPG} method for circuits with random patternresistant
faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {859--866},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013898},
doi = {10.1109/TCAD.2002.1013898},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KavousianosBNT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimKLK02,
author = {Ki{-}Wook Kim and
Taewhan Kim and
C. L. Liu and
Sung{-}Mo Kang},
title = {Domino logic synthesis based on implication graph},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {232--240},
year = {2002},
url = {https://doi.org/10.1109/43.980261},
doi = {10.1109/43.980261},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimKLK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimuraIS02,
author = {Mutsumi Kimura and
Satoshi Inoue and
Tatsuya Shimoda},
title = {Table look-up model of thin-film transistors for circuit simulationusing
spline interpolation with transformation by y=x+log(x)},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1101--1104},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801090},
doi = {10.1109/TCAD.2002.801090},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimuraIS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Koranne02,
author = {Sandeep Koranne},
title = {Formulating SoC test scheduling as a network transportation problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1517--1525},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804382},
doi = {10.1109/TCAD.2002.804382},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Koranne02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KozhayaNN02,
author = {Joseph N. Kozhaya and
Sani R. Nassif and
Farid N. Najm},
title = {A multigrid-like technique for power grid analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1148--1160},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802271},
doi = {10.1109/TCAD.2002.802271},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KozhayaNN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KudlugiT02,
author = {Murali Kudlugi and
Russell Tessier},
title = {Static scheduling of multidomain circuits for fast functional verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1253--1268},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804086},
doi = {10.1109/TCAD.2002.804086},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KudlugiT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuehlmannPKG02,
author = {Andreas Kuehlmann and
Viresh Paruthi and
Florian Krohm and
Malay K. Ganai},
title = {Robust Boolean reasoning for equivalence checking and functional property
verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1377--1394},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804386},
doi = {10.1109/TCAD.2002.804386},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuehlmannPKG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LaiW02,
author = {Minghorng Lai and
Martin D. F. Wong},
title = {Maze routing with buffer insertion and wiresizing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1205--1209},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802260},
doi = {10.1109/TCAD.2002.802260},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LaiW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LapinskiiJV02,
author = {Viktor S. Lapinskii and
Margarida F. Jacome and
Gustavo de Veciana},
title = {Application-specific clustered {VLIW} datapaths: early exploration
on a parameterized design space},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {889--903},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800451},
doi = {10.1109/TCAD.2002.800451},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LapinskiiJV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeC02,
author = {Yu{-}Min Lee and
Charlie Chung{-}Ping Chen},
title = {Power grid transient simulation in linear time based on transmission-line-modeling
alternating-direction-implicit method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1343--1352},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804082},
doi = {10.1109/TCAD.2002.804082},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Lin02,
author = {Rung{-}Bin Lin},
title = {Comments on "Filling algorithms and analyses for layout density control"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1209--1211},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802262},
doi = {10.1109/TCAD.2002.802262},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Lin02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuPF02,
author = {Xun Liu and
Marios C. Papaefthymiou and
Eby G. Friedman},
title = {Retiming and clock scheduling for digital circuit optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {184--203},
year = {2002},
url = {https://doi.org/10.1109/43.980258},
doi = {10.1109/43.980258},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuPF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LouTKS02,
author = {Jinan Lou and
Shashidhar Thakur and
Shankar Krishnamoorthy and
Henry S. Sheng},
title = {Estimating routing congestion using probabilistic analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {1},
pages = {32--41},
year = {2002},
url = {https://doi.org/10.1109/43.974135},
doi = {10.1109/43.974135},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LouTKS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuBM02,
author = {Yung{-}Hsiang Lu and
Luca Benini and
Giovanni De Micheli},
title = {Dynamic frequency scaling with buffer insertion for mixed workloads},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1284--1305},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804087},
doi = {10.1109/TCAD.2002.804087},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuBM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Madden02,
author = {Patrick H. Madden},
title = {Reporting of standard cell placement results},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {240--247},
year = {2002},
url = {https://doi.org/10.1109/43.980262},
doi = {10.1109/43.980262},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Madden02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Mak02,
author = {Wai{-}Kei Mak},
title = {Min-cut partitioning with functional replication fortechnology-mapped
circuits using minimum area overhead},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {4},
pages = {491--497},
year = {2002},
url = {https://doi.org/10.1109/43.992773},
doi = {10.1109/43.992773},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Mak02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ManquinhoM02,
author = {Vasco M. Manquinho and
Jo{\~{a}}o P. Marques Silva},
title = {Search pruning techniques in SAT-based branch-and-bound algorithmsfor
the binate covering problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {505--516},
year = {2002},
url = {https://doi.org/10.1109/43.998623},
doi = {10.1109/43.998623},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ManquinhoM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaurineRAA02,
author = {Philippe Maurine and
Mustapha Rezzoug and
Nadine Az{\'{e}}mard and
Daniel Auvergne},
title = {Transition time modeling in deep submicron {CMOS}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1352--1363},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804088},
doi = {10.1109/TCAD.2002.804088},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaurineRAA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MuhammadR02,
author = {Khurram Muhammad and
Kaushik Roy},
title = {A graph theoretic approach for synthesizing very low-complexityhigh-speed
digital filters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {204--216},
year = {2002},
url = {https://doi.org/10.1109/43.980259},
doi = {10.1109/43.980259},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MuhammadR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NakatakeKK02,
author = {Shigetoshi Nakatake and
Yukiko Kubo and
Yoji Kajitani},
title = {Consistent floorplanning with hierarchical superconstraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {1},
pages = {42--49},
year = {2002},
url = {https://doi.org/10.1109/43.974136},
doi = {10.1109/43.974136},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NakatakeKK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NalamalpuSB02,
author = {Ankireddy Nalamalpu and
Sriram Srinivasan and
Wayne P. Burleson},
title = {Boosters for driving long onchip interconnects - design issues, interconnect
synthesis, and comparison with repeaters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {1},
pages = {50--62},
year = {2002},
url = {https://doi.org/10.1109/43.974137},
doi = {10.1109/43.974137},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NalamalpuSB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NamSR02,
author = {Gi{-}Joon Nam and
Karem A. Sakallah and
Rob A. Rutenbar},
title = {A new {FPGA} detailed routing approach via search-based Booleansatisfiability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {674--684},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004311},
doi = {10.1109/TCAD.2002.1004311},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/NamSR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OliveiraL02,
author = {Alexandre C{\'{e}}sar Muniz de Oliveira and
Luiz Antonio Nogueira Lorena},
title = {A constructive genetic algorithm for gate matrix layout problems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {969--974},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800454},
doi = {10.1109/TCAD.2002.800454},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OliveiraL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OrshanskyMCKH02,
author = {Michael Orshansky and
Linda Milor and
Pinhong Chen and
Kurt Keutzer and
Chenming Hu},
title = {Impact of spatial intrachip gate length variability on theperformance
of high-speed digital circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {544--553},
year = {2002},
url = {https://doi.org/10.1109/43.998626},
doi = {10.1109/43.998626},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/OrshanskyMCKH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OuyangTTGD02,
author = {Min Ouyang and
Michel Toulouse and
Krishnaiyan Thulasiraman and
Fred W. Glover and
Jitender S. Deogun},
title = {Multilevel cooperative search for the circuit/hypergraphpartitioning
problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {685--693},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004312},
doi = {10.1109/TCAD.2002.1004312},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OuyangTTGD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkK02,
author = {In{-}Cheol Park and
Hyeong{-}Ju Kang},
title = {Digital filter synthesis based on an algorithm to generate all minimal
signed digit representations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1525--1529},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804374},
doi = {10.1109/TCAD.2002.804374},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ParkK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PlasVGS02,
author = {Geert Van der Plas and
Jan Vandenbussche and
Georges G. E. Gielen and
Willy M. C. Sansen},
title = {A layout synthesis methodology for array-type analog blocks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {645--661},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004309},
doi = {10.1109/TCAD.2002.1004309},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PlasVGS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz02,
author = {Irith Pomeranz},
title = {On the use of random limited-scan to improve at-speed randompattern
testing of scan circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1068--1076},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801092},
doi = {10.1109/TCAD.2002.801092},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR02,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Property-based test generation for scan designs and the effects ofthe
test application scheme and scan selection on the number ofdetectable
faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {628--637},
year = {2002},
url = {https://doi.org/10.1109/43.998633},
doi = {10.1109/43.998633},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR02a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test compaction for at-speed testing of scan circuits based onnonscan
test. sequences and removal of transfer sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {706--714},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004314},
doi = {10.1109/TCAD.2002.1004314},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR02b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {n-pass n-detection fault simulation and its applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {980--986},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800453},
doi = {10.1109/TCAD.2002.800453},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR02b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Qu02,
author = {Gang Qu},
title = {Publicly detectable watermarking for intellectual property authentication
in {VLSI} design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1363--1368},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804205},
doi = {10.1109/TCAD.2002.804205},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Qu02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RamanathanIG02,
author = {Dinesh Ramanathan and
Sandy Irani and
Rajesh K. Gupta},
title = {An analysis of system level power management algorithms and theireffects
on latency},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {3},
pages = {291--305},
year = {2002},
url = {https://doi.org/10.1109/43.986423},
doi = {10.1109/43.986423},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RamanathanIG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RanterPSGS02,
author = {Carl De Ranter and
Geert Van der Plas and
Michiel Steyaert and
Georges G. E. Gielen and
Willy M. C. Sansen},
title = {{CYCLONE:} automated design and layout of {RF} LC-oscillators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1161--1170},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802267},
doi = {10.1109/TCAD.2002.802267},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RanterPSGS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaviJ02,
author = {Srivaths Ravi and
Niraj K. Jha},
title = {Test synthesis of systems-on-a-chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1211--1217},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802265},
doi = {10.1109/TCAD.2002.802265},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RaviJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaviLJ02,
author = {Srivaths Ravi and
Ganesh Lakshminarayana and
Niraj K. Jha},
title = {High-level test compaction techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {827--841},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013895},
doi = {10.1109/TCAD.2002.1013895},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RaviLJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RayCN02,
author = {Baidya Nath Ray and
Parimal Pal Chaudhuri and
Prasanta Kumar Nandi},
title = {Efficient synthesis of {OTA} network for linear analog functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {517--533},
year = {2002},
url = {https://doi.org/10.1109/43.998624},
doi = {10.1109/43.998624},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RayCN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RosingerAN02,
author = {Paul M. Rosinger and
Bashir M. Al{-}Hashimi and
Nicola Nicolici},
title = {Power profile manipulation: a new approach for reducing test application
time under power constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1217--1225},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802256},
doi = {10.1109/TCAD.2002.802256},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RosingerAN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RosselloS02,
author = {Jos{\'{e}} Luis Rossell{\'{o}} and
Jaume Segura},
title = {Charge-based analytical model for the evaluation of powerconsumption
in submicron {CMOS} buffers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {4},
pages = {433--448},
year = {2002},
url = {https://doi.org/10.1109/43.992767},
doi = {10.1109/43.992767},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RosselloS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SalekLP02,
author = {Amir H. Salek and
Jinan Lou and
Massoud Pedram},
title = {Hierarchical buffered routing tree generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {554--567},
year = {2002},
url = {https://doi.org/10.1109/43.998627},
doi = {10.1109/43.998627},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SalekLP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SamiSSZ02,
author = {Mariagiovanna Sami and
Donatella Sciuto and
Cristina Silvano and
Vittorio Zaccaria},
title = {An instruction-level energy model for embedded {VLIW} architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {998--1010},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801105},
doi = {10.1109/TCAD.2002.801105},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SamiSSZ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchoenmakerM02,
author = {Wim Schoenmaker and
Peter Meuris},
title = {Electromagnetic interconnects and passives modeling: softwareimplementation
issues},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {534--543},
year = {2002},
url = {https://doi.org/10.1109/43.998625},
doi = {10.1109/43.998625},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SchoenmakerM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchoenmakerMMM02,
author = {Wim Schoenmaker and
Wim Magnus and
Peter Meuris and
Bert Maleszka},
title = {Renormalization group meshes and the discretization of {TCAD} equations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1425--1433},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804383},
doi = {10.1109/TCAD.2002.804383},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SchoenmakerMMM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiLKY02,
author = {Weiping Shi and
Jianguo Liu and
Naveen Kakani and
Tiejun Yu},
title = {A fast hierarchical algorithm for three-dimensional capacitanceextraction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {3},
pages = {330--336},
year = {2002},
url = {https://doi.org/10.1109/43.986426},
doi = {10.1109/43.986426},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShiLKY02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShinS02,
author = {Youngsoo Shin and
Takayasu Sakurai},
title = {Power distribution analysis of {VLSI} interconnects using model orderreduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {739--745},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004318},
doi = {10.1109/TCAD.2002.1004318},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShinS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SidorowiczB02,
author = {Piotr R. Sidorowicz and
Janusz A. Brzozowski},
title = {A framework for testing special-purpose memories},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1459--1468},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804375},
doi = {10.1109/TCAD.2002.804375},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SidorowiczB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SikdarGC02,
author = {Biplab K. Sikdar and
Niloy Ganguly and
Parimal Pal Chaudhuri},
title = {Design of hierarchical cellular automata for on-chip test pattern
generator},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1530--1539},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804380},
doi = {10.1109/TCAD.2002.804380},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SikdarGC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SripramongT02,
author = {Thanwa Sripramong and
Christofer Toumazou},
title = {The invention of {CMOS} amplifiers using genetic programming and current-flow
analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1237--1252},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804109},
doi = {10.1109/TCAD.2002.804109},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SripramongT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SundararajanSP02,
author = {Vijay Sundararajan and
Sachin S. Sapatnekar and
Keshab K. Parhi},
title = {Fast and exact transistor sizing based on iterative relaxation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {568--581},
year = {2002},
url = {https://doi.org/10.1109/43.998628},
doi = {10.1109/43.998628},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SundararajanSP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TakahashiBST02,
author = {Hiroshi Takahashi and
Kwame Osei Boateng and
Kewal K. Saluja and
Yuzo Takamatsu},
title = {On diagnosing multiple stuck-at faults using multiple and singlefault
simulation in combinational circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {3},
pages = {362--368},
year = {2002},
url = {https://doi.org/10.1109/43.986429},
doi = {10.1109/43.986429},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TakahashiBST02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TanRLJ02,
author = {Tat Kee Tan and
Anand Raghunathan and
Ganesh Lakshminarayana and
Niraj K. Jha},
title = {High-level energy macromodeling of embedded software},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1037--1050},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801094},
doi = {10.1109/TCAD.2002.801094},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TanRLJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TianTW02,
author = {Ruiqi Tian and
Xiaoping Tang and
Martin D. F. Wong},
title = {Dummy-feature placement for chemical-mechanical polishinguniformity
in a shallow-trench isolation process},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {1},
pages = {63--71},
year = {2002},
url = {https://doi.org/10.1109/43.974138},
doi = {10.1109/43.974138},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TianTW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TienCT02,
author = {Tzyy{-}Kuen Tien and
Shih{-}Chieh Chang and
Tong{-}Kai Tsai},
title = {Crosstalk alleviation for dynamic PLAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1416--1424},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804384},
doi = {10.1109/TCAD.2002.804384},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TienCT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/UchinoC02,
author = {Taku Uchino and
Jason Cong},
title = {An interconnect energy model considering coupling effects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {763--776},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013890},
doi = {10.1109/TCAD.2002.1013890},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/UchinoC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/UshidaYNKI02,
author = {Akio Ushida and
Yoshihiro Yamagami and
Yoshifumi Nishio and
Ikkei Kinouchi and
Yasuaki Inoue},
title = {An efficient algorithm for finding multiple {DC} solutions based onthe
SPICE-oriented Newton homotopy method},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {3},
pages = {337--348},
year = {2002},
url = {https://doi.org/10.1109/43.986427},
doi = {10.1109/43.986427},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/UshidaYNKI02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VanasscheGS02,
author = {Piet Vanassche and
Georges G. E. Gielen and
Willy M. C. Sansen},
title = {Symbolic modeling of periodically time-varying systems usingharmonic
transfer matrices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1011--1024},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801098},
doi = {10.1109/TCAD.2002.801098},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VanasscheGS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VariyamCC02,
author = {Pramodchandran N. Variyam and
Sasikumar Cherubal and
Abhijit Chatterjee},
title = {Prediction of analog performance parameters using fast transienttesting},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {3},
pages = {349--361},
year = {2002},
url = {https://doi.org/10.1109/43.986428},
doi = {10.1109/43.986428},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VariyamCC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VenerisA02,
author = {Andreas G. Veneris and
Magdy S. Abadir},
title = {Design rewiring using {ATPG}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1469--1479},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804388},
doi = {10.1109/TCAD.2002.804388},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VenerisA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangC02,
author = {Ting{-}Yuan Wang and
Charlie Chung{-}Ping Chen},
title = {3-D Thermal-ADI: a linear-time chip level transient thermal simulator},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1434--1445},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804385},
doi = {10.1109/TCAD.2002.804385},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangG02,
author = {Seongmoon Wang and
Sandeep K. Gupta},
title = {{DS-LFSR:} a {BIST} {TPG} for low switching activity},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {842--851},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013896},
doi = {10.1109/TCAD.2002.1013896},
timestamp = {Fri, 22 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangG02a,
author = {Seongmoon Wang and
Sandeep K. Gupta},
title = {An automatic test pattern generator for minimizing switching activity
during scan testing activity},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {954--968},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800460},
doi = {10.1109/TCAD.2002.800460},
timestamp = {Fri, 22 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangG02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangTJ02,
author = {Chun{-}Yao Wang and
Shing{-}Wu Tung and
Jing{-}Yang Jou},
title = {On automatic-verification pattern generation for SoC withport-order
fault model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {4},
pages = {466--479},
year = {2002},
url = {https://doi.org/10.1109/43.992770},
doi = {10.1109/43.992770},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangTJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangTJ02a,
author = {Chun{-}Yao Wang and
Shing{-}Wu Tung and
Jing{-}Yang Jou},
title = {An automorphic approach to verification pattern generation for SoC
design verification using port-order fault model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1225--1232},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802266},
doi = {10.1109/TCAD.2002.802266},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangTJ02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangV02,
author = {Qi Wang and
Sarma B. K. Vrudhula},
title = {Algorithms for minimizing standby power in deep submicrometer, dual-V\({}_{\mbox{t}}\)
{CMOS} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {3},
pages = {306--318},
year = {2002},
url = {https://doi.org/10.1109/43.986424},
doi = {10.1109/43.986424},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WolfeWP02,
author = {Gregory Wolfe and
Jennifer L. Wong and
Miodrag Potkonjak},
title = {Watermarking graph partitioning solutions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {10},
pages = {1196--1204},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.802277},
doi = {10.1109/TCAD.2002.802277},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WolfeWP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuHCW02,
author = {Chi{-}Feng Wu and
Chih{-}Tsun Huang and
Kuo{-}Liang Cheng and
Cheng{-}Wen Wu},
title = {Fault simulation and test algorithm generation for random accessmemories},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {4},
pages = {480--490},
year = {2002},
url = {https://doi.org/10.1109/43.992771},
doi = {10.1109/43.992771},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuHCW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuK02,
author = {Kaijie Wu and
Ramesh Karri},
title = {Algorithm level recomputing using allocation diversity: a registertransfer
level approach to time redundancy-based concurrent errordetection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1077--1087},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801110},
doi = {10.1109/TCAD.2002.801110},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiangF02,
author = {Dong Xiang and
Hideo Fujiwara},
title = {Handling the pin overhead problem of DFTs for high-quality and at-speed
tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1105--1113},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801099},
doi = {10.1109/TCAD.2002.801099},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XiangF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XingK02,
author = {Zhaoyun Xing and
Russell Kao},
title = {Shortest path search using tiles and piecewise linear costpropagation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {145--158},
year = {2002},
url = {https://doi.org/10.1109/43.980255},
doi = {10.1109/43.980255},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XingK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangC02,
author = {Congguang Yang and
Maciej J. Ciesielski},
title = {{BDS:} a BDD-based logic optimization system},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {7},
pages = {866--876},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1013899},
doi = {10.1109/TCAD.2002.1013899},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangKS02,
author = {Xiaojian Yang and
Ryan Kastner and
Majid Sarrafzadeh},
title = {Congestion estimation during top-down placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {1},
pages = {72--80},
year = {2002},
url = {https://doi.org/10.1109/43.974139},
doi = {10.1109/43.974139},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangKS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YildizM02,
author = {Mehmet Can Yildiz and
Patrick H. Madden},
title = {Preferred direction Steiner trees},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {11},
pages = {1368--1372},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804105},
doi = {10.1109/TCAD.2002.804105},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YildizM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuanO02,
author = {Fei Yuan and
Ajoy Opal},
title = {An efficient transient analysis algorithm for mildly nonlinearcircuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {662--673},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004310},
doi = {10.1109/TCAD.2002.1004310},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuanO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangCF02,
author = {Tianhao Zhang and
Krishnendu Chakrabarty and
Richard B. Fair},
title = {Design of reconfigurable composite microsystems based on hardware/software
codesign principles},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {987--995},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800455},
doi = {10.1109/TCAD.2002.800455},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangCF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoPSB02,
author = {Min Zhao and
Rajendran Panda and
Sachin S. Sapatnekar and
David T. Blaauw},
title = {Hierarchical analysis of power distribution networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {159--168},
year = {2002},
url = {https://doi.org/10.1109/43.980256},
doi = {10.1109/43.980256},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoPSB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoRK02,
author = {Shiyou Zhao and
Kaushik Roy and
Cheng{-}Kok Koh},
title = {Decoupling capacitance allocation and its application topower-supply
noise-aware floorplanning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {1},
pages = {81--92},
year = {2002},
url = {https://doi.org/10.1109/43.974140},
doi = {10.1109/43.974140},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoRK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
retrieved on 2024-04-25 02:48 CEST from data curated by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
