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@article{DBLP:journals/tvlsi/AlidinaMDGP94,
author = {Mazhar Alidina and
Jos{\'{e}} Monteiro and
Srinivas Devadas and
Abhijit Ghosh and
Marios C. Papaefthymiou},
title = {Precomputation-based sequential logic optimization for low power},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {426--436},
year = {1994},
url = {https://doi.org/10.1109/92.335011},
doi = {10.1109/92.335011},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlidinaMDGP94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AthasSKTC94,
author = {William C. Athas and
Lars J. Svensson and
Jefferey G. Koller and
Nestoras Tzartzanis and
E. Ying{-}Chin Chou},
title = {Low-power digital systems based on adiabatic-switching principles},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {398--407},
year = {1994},
url = {https://doi.org/10.1109/92.335009},
doi = {10.1109/92.335009},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AthasSKTC94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AudetSA94,
author = {Daniel Audet and
Yvon Savaria and
N. Arel},
title = {Pipelining communications in large {VLSI/ULSI} systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {1--10},
year = {1994},
url = {https://doi.org/10.1109/92.273144},
doi = {10.1109/92.273144},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AudetSA94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BombanaBCFSZ94,
author = {Massimo Bombana and
Giacomo Buonanno and
Patrizia Cavalloro and
Fabrizio Ferrandi and
Donatella Sciuto and
Giuseppe Zaza},
title = {{ALADIN:} a multilevel testability analyzer for {VLSI} system design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {157--171},
year = {1994},
url = {https://doi.org/10.1109/92.285743},
doi = {10.1109/92.285743},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BombanaBCFSZ94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChakrabartiW94,
author = {Chaitali Chakrabarti and
Li{-}Yu Wang},
title = {Novel sorting network-based architectures for rank order filters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {502--507},
year = {1994},
url = {https://doi.org/10.1109/92.335027},
doi = {10.1109/92.335027},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabartiW94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaudhuriWM94,
author = {Samit Chaudhuri and
Robert A. Walker and
J. E. Mitchell},
title = {Analyzing and exploiting the structure of the constraints in the {ILP}
approach to the scheduling problem},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {456--471},
year = {1994},
url = {https://doi.org/10.1109/92.335014},
doi = {10.1109/92.335014},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaudhuriWM94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHK94,
author = {Yunn Yen Chen and
Yu{-}Chin Hsu and
Chung{-}Ta King},
title = {{MULTIPAR:} behavioral partition for synthesizing multiprocessor architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {21--32},
year = {1994},
url = {https://doi.org/10.1109/92.273146},
doi = {10.1109/92.273146},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenY94,
author = {Chien{-}In Henry Chen and
Joel T. Yuen},
title = {Automated synthesis of pseudo-exhaustive test generator in {VLSI}
{BIST} design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {273--291},
year = {1994},
url = {https://doi.org/10.1109/92.311637},
doi = {10.1109/92.311637},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenY94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CherkauerF94,
author = {Brian S. Cherkauer and
Eby G. Friedman},
title = {Channel width tapering of serially connected MOSFET's with emphasis
on power dissipation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {100--114},
year = {1994},
url = {https://doi.org/10.1109/92.273155},
doi = {10.1109/92.273155},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CherkauerF94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoiSC94,
author = {Joongho Choi and
Bing J. Sheu and
Josephine C.{-}F. Chang},
title = {A Gaussian synapse circuit for analog {VLSI} neural networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {129--133},
year = {1994},
url = {https://doi.org/10.1109/92.273156},
doi = {10.1109/92.273156},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoiSC94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChungWH94,
author = {Pi{-}Yu Chung and
Yi{-}Min Wang and
Ibrahim N. Hajj},
title = {Logic design error diagnosis and correction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {320--332},
year = {1994},
url = {https://doi.org/10.1109/92.311641},
doi = {10.1109/92.311641},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChungWH94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CongD94,
author = {Jason Cong and
Yuzheng Ding},
title = {On area/depth trade-off in LUT-based {FPGA} technology mapping},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {137--148},
year = {1994},
url = {https://doi.org/10.1109/92.285741},
doi = {10.1109/92.285741},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CongD94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CongK94,
author = {Jason Cong and
Cheng{-}Kok Koh},
title = {Simultaneous driver and wire sizing for performance and power optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {408--425},
year = {1994},
url = {https://doi.org/10.1109/92.335010},
doi = {10.1109/92.335010},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CongK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DeNNB94,
author = {Kaushik De and
Chitra Natarajan and
Devi Nair and
Prithviraj Banerjee},
title = {{RSYN:} a system for automated synthesis of reliable multilevel circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {186--195},
year = {1994},
url = {https://doi.org/10.1109/92.285745},
doi = {10.1109/92.285745},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DeNNB94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DevadasKMW94,
author = {Srinivas Devadas and
Kurt Keutzer and
Sharad Malik and
Albert R. Wang},
title = {Certified timing verification and the transition delay of a logic
circuit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {333--342},
year = {1994},
url = {https://doi.org/10.1109/92.311642},
doi = {10.1109/92.311642},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DevadasKMW94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FaginR94,
author = {Barry S. Fagin and
C. Renard},
title = {Field programmable gate arrays and floating point arithmetic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {365--367},
year = {1994},
url = {https://doi.org/10.1109/92.311646},
doi = {10.1109/92.311646},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FaginR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangCSCC94,
author = {Wai{-}Chi Fang and
Chi{-}Yung Chang and
Bing J. Sheu and
Oscal T.{-}C. Chen and
John C. Curlander},
title = {{VLSI} systolic binary tree-searched vector quantizer for image compression},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {33--44},
year = {1994},
url = {https://doi.org/10.1109/92.273148},
doi = {10.1109/92.273148},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FangCSCC94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Gebotys94,
author = {Catherine H. Gebotys},
title = {An optimization approach to the synthesis of multichip architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {11--20},
year = {1994},
url = {https://doi.org/10.1109/92.273145},
doi = {10.1109/92.273145},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Gebotys94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhoshVK94,
author = {Joydeep Ghosh and
Anujan Varma and
Naveen Krishnamurthy},
title = {Distributed control schemes for fast arbitration in large crossbar
networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {54--67},
year = {1994},
url = {https://doi.org/10.1109/92.273150},
doi = {10.1109/92.273150},
timestamp = {Mon, 09 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GhoshVK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeydariTX94,
author = {Mohammad Hossain Heydari and
Ioannis G. Tollis and
Chunliang Xia},
title = {Algorithms and bounds for layer assignment of {MCM} routing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {265--270},
year = {1994},
url = {https://doi.org/10.1109/92.285755},
doi = {10.1109/92.285755},
timestamp = {Tue, 26 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeydariTX94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HossainWA94,
author = {Razak Hossain and
Leszek D. Wronski and
Alexander Albicki},
title = {Low power design using double edge triggered flip-flops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {261--265},
year = {1994},
url = {https://doi.org/10.1109/92.285754},
doi = {10.1109/92.285754},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HossainWA94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HowardTA94,
author = {Neil J. Howard and
Andrew M. Tyrrell and
Nigel M. Allinson},
title = {The yield enhancement of field-programmable gate arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {115--123},
year = {1994},
url = {https://doi.org/10.1109/92.273147},
doi = {10.1109/92.273147},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HowardTA94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangW94,
author = {Steve C.{-}Y. Huang and
Wayne H. Wolf},
title = {Performance-driven synthesis in controller-datapath systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {68--80},
year = {1994},
url = {https://doi.org/10.1109/92.273151},
doi = {10.1109/92.273151},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangW94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JengC94,
author = {Lih{-}Gwo Jeng and
Liang{-}Gee Chen},
title = {Rate-optimal {DSP} synthesis by pipeline and minimum unfolding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {81--88},
year = {1994},
url = {https://doi.org/10.1109/92.273152},
doi = {10.1109/92.273152},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JengC94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JunH94,
author = {Hong{-}Shin Jun and
Sun{-}Young Hwang},
title = {Design of a pipelined datapath synthesis system for digital signal
processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {292--303},
year = {1994},
url = {https://doi.org/10.1109/92.311638},
doi = {10.1109/92.311638},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JunH94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KangLS94,
author = {Eric Q. Kang and
Rung{-}Bin Lin and
Eugene Shragowitz},
title = {Fuzzy logic approach to {VLSI} placement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {489--501},
year = {1994},
url = {https://doi.org/10.1109/92.335016},
doi = {10.1109/92.335016},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KangLS94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KangS94,
author = {Sungho Kang and
Stephen A. Szygenda},
title = {The simulation automation system (SAS); concepts, implementation,
and results},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {89--99},
year = {1994},
url = {https://doi.org/10.1109/92.273154},
doi = {10.1109/92.273154},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KangS94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Katti94,
author = {Raj S. Katti},
title = {A modified Booth algorithm for high radix fixed-point multiplication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {522--524},
year = {1994},
url = {https://doi.org/10.1109/92.335021},
doi = {10.1109/92.335021},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Katti94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KorenKS94,
author = {Israel Koren and
Zahava Koren and
Charles H. Stapper},
title = {A statistical study of defect maps of large area {VLSI} IC's},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {249--256},
year = {1994},
url = {https://doi.org/10.1109/92.285750},
doi = {10.1109/92.285750},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KorenKS94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Kundu94,
author = {Sandip Kundu},
title = {Diagnosing scan chain faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {512--516},
year = {1994},
url = {https://doi.org/10.1109/92.335019},
doi = {10.1109/92.335019},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Kundu94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeungL94,
author = {S. C. Leung and
Hon Fung Li},
title = {A syntax-directed translation for the synthesis of delay-insensitive
circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {196--210},
year = {1994},
url = {https://doi.org/10.1109/92.285746},
doi = {10.1109/92.285746},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeungL94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LevittRA94,
author = {Marc E. Levitt and
Kaushik Roy and
Jacob A. Abraham},
title = {BiCMOS logic testing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {241--248},
year = {1994},
url = {https://doi.org/10.1109/92.285749},
doi = {10.1109/92.285749},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LevittRA94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinO94,
author = {Ming{-}Bo Lin and
A. Yavuz Oru{\c{c}}},
title = {A fault-tolerant permutation network modulo arithmetic processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {312--319},
year = {1994},
url = {https://doi.org/10.1109/92.311640},
doi = {10.1109/92.311640},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinO94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Liu94,
author = {Lishing Liu},
title = {Partial address directory for cache access},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {226--240},
year = {1994},
url = {https://doi.org/10.1109/92.285748},
doi = {10.1109/92.285748},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Liu94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MarkasRK94,
author = {Tassos Markas and
Mark Royals and
Nick Kanopoulos},
title = {Design and {DCVS} implementation of a self-checking bus-monitor unit
for highly reliable fault-tolerant system configurations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {149--156},
year = {1994},
url = {https://doi.org/10.1109/92.285742},
doi = {10.1109/92.285742},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MarkasRK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NagendraOI94,
author = {Chetana Nagendra and
Robert Michael Owens and
Mary Jane Irwin},
title = {Power-delay characteristics of {CMOS} adders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {377--381},
year = {1994},
url = {https://doi.org/10.1109/92.311649},
doi = {10.1109/92.311649},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NagendraOI94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Najm94,
author = {Farid N. Najm},
title = {A survey of power estimation techniques in {VLSI} circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {446--455},
year = {1994},
url = {https://doi.org/10.1109/92.335013},
doi = {10.1109/92.335013},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Najm94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NielsenNSB94,
author = {Lars Skovby Nielsen and
Cees Niessen and
Jens Spars{\o} and
Kees van Berkel},
title = {Low-power operation using self-timed circuits and adaptive scaling
of the supply voltage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {391--397},
year = {1994},
url = {https://doi.org/10.1109/92.335008},
doi = {10.1109/92.335008},
timestamp = {Tue, 27 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NielsenNSB94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OhY94,
author = {Choong Gun Oh and
Hee Yong Youn},
title = {On concurrent error location and correction of {FFT} networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {257--260},
year = {1994},
url = {https://doi.org/10.1109/92.285753},
doi = {10.1109/92.285753},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OhY94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Oklobdzija94,
author = {Vojin G. Oklobdzija},
title = {An algorithmic and novel design of a leading zero detector circuit:
comparison with logic synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {124--128},
year = {1994},
url = {https://doi.org/10.1109/92.273153},
doi = {10.1109/92.273153},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Oklobdzija94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OrailogluK94,
author = {Alex Orailoglu and
Ramesh Karri},
title = {Coactive scheduling and checkpoint determination during high level
synthesis of self-recovering microarchitectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {304--311},
year = {1994},
url = {https://doi.org/10.1109/92.311639},
doi = {10.1109/92.311639},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/OrailogluK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PelletierM94,
author = {R. V. Pelletier and
Robert D. McLeod},
title = {Loop based design for wafer scale systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {354--357},
year = {1994},
url = {https://doi.org/10.1109/92.311643},
doi = {10.1109/92.311643},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PelletierM94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RimMJL94,
author = {Minjoong Rim and
Ashutosh Mujumdar and
Rajiv Jain and
Renato De Leone},
title = {Optimal and heuristic algorithms for solving the binding problem},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {211--225},
year = {1994},
url = {https://doi.org/10.1109/92.285747},
doi = {10.1109/92.285747},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RimMJL94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RoyN94,
author = {Kaushik Roy and
Sudip Nag},
title = {Automatic synthesis of {FPGA} channel architecture for routability
and performance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {508--511},
year = {1994},
url = {https://doi.org/10.1109/92.335018},
doi = {10.1109/92.335018},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RoyN94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SavirP94,
author = {Jacob Savir and
Srinivas Patil},
title = {On broad-side delay test},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {368--372},
year = {1994},
url = {https://doi.org/10.1109/92.311647},
doi = {10.1109/92.311647},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SavirP94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeawrightB94,
author = {Andrew Seawright and
Forrest Brewer},
title = {Clairvoyant: a synthesis system for production-based specification},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {2},
pages = {172--185},
year = {1994},
url = {https://doi.org/10.1109/92.285744},
doi = {10.1109/92.285744},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeawrightB94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SrinivasVP94,
author = {Hosahalli R. Srinivas and
Bapiraju Vinnakota and
Keshab K. Parhi},
title = {A C-testable carry-free divider},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {472--488},
year = {1994},
url = {https://doi.org/10.1109/92.335015},
doi = {10.1109/92.335015},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SrinivasVP94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Stroud94,
author = {Charles E. Stroud},
title = {Reliability of majority voting based {VLSI} fault-tolerant circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {516--521},
year = {1994},
url = {https://doi.org/10.1109/92.335020},
doi = {10.1109/92.335020},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Stroud94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TiwariMW94,
author = {Vivek Tiwari and
Sharad Malik and
Andrew Wolfe},
title = {Power analysis of embedded software: a first step towards software
power minimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {4},
pages = {437--445},
year = {1994},
url = {https://doi.org/10.1109/92.335012},
doi = {10.1109/92.335012},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TiwariMW94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsangW94,
author = {K. Tsang and
Belle W. Y. Wei},
title = {A {VLSI} architecture for a real-time code book generator and encoder
of a vector quantizer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {360--364},
year = {1994},
url = {https://doi.org/10.1109/92.311645},
doi = {10.1109/92.311645},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsangW94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TzionasTT94,
author = {Panagiotis Tzionas and
Philippos G. Tsalides and
Adonios Thanailakis},
title = {A new, cellular automaton-based, nearest neighbor pattern classifier
and its {VLSI} implementation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {343--353},
year = {1994},
url = {https://doi.org/10.1109/92.311634},
doi = {10.1109/92.311634},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TzionasTT94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YakovlevPL94,
author = {Alexandre Yakovlev and
A. Petrov and
Luciano Lavagno},
title = {A low latency asynchronous arbitration circuit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {372--377},
year = {1994},
url = {https://doi.org/10.1109/92.311648},
doi = {10.1109/92.311648},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YakovlevPL94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YehLCHAL94,
author = {Chingwei Yeh and
Lung{-}Tien Liu and
Chung{-}Kuan Cheng and
T. C. Hu and
S. Ahmed and
M. Liddel},
title = {Block-oriented programmable design with switching network interconnect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {1},
pages = {45--53},
year = {1994},
url = {https://doi.org/10.1109/92.273149},
doi = {10.1109/92.273149},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YehLCHAL94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangWY94,
author = {Chang N. Zhang and
J. H. Weston and
Y.{-}F. Yan},
title = {Determining objective functions in systolic array designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {2},
number = {3},
pages = {357--360},
year = {1994},
url = {https://doi.org/10.1109/92.311644},
doi = {10.1109/92.311644},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangWY94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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