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@article{DBLP:journals/tvlsi/AggarwalMK12,
author = {Supriya Aggarwal and
Pramod Kumar Meher and
Kavita Khare},
title = {Area-Time Efficient Scaling-Free {CORDIC} Using Generalized Micro-Rotation
Selection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1542--1546},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2158459},
doi = {10.1109/TVLSI.2011.2158459},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AggarwalMK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AhmedM12,
author = {Fahad Ahmed and
Linda Milor},
title = {Analysis and On-Chip Monitoring of Gate Oxide Breakdown in {SRAM}
Cells},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {855--864},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2119500},
doi = {10.1109/TVLSI.2011.2119500},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AhmedM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlimohammadFC12,
author = {Amirhossein Alimohammad and
Saeed Fouladi Fard and
Bruce F. Cockburn},
title = {Hardware Implementation of Nakagami and Weibull Variate Generators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1276--1284},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2156822},
doi = {10.1109/TVLSI.2011.2156822},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlimohammadFC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AmadorKPR12,
author = {Erick Amador and
Raymond Knopp and
Renaud Pacalet and
Vincent Rezard},
title = {Dynamic Power Management for the Iterative Decoding of Turbo Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2133--2137},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2167765},
doi = {10.1109/TVLSI.2011.2167765},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AmadorKPR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AmaruMM12,
author = {Luca Gaetano Amar{\`{u}} and
Maurizio Martina and
Guido Masera},
title = {High Speed Architectures for Finding the First two Maximum/Minimum
Values},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2342--2346},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2174166},
doi = {10.1109/TVLSI.2011.2174166},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AmaruMM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AndersonWR12,
author = {Jason Helge Anderson and
Qiang Wang and
Chirag Ravishankar},
title = {Raising {FPGA} Logic Density Through Synthesis-Inspired Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {537--550},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2102781},
doi = {10.1109/TVLSI.2010.2102781},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AndersonWR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AtasuLMOD12,
author = {Kubilay Atasu and
Wayne Luk and
Oskar Mencer and
Can C. {\"{O}}zturan and
G{\"{u}}nhan D{\"{u}}ndar},
title = {{FISH:} Fast Instruction SyntHesis for Custom Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {52--65},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2090543},
doi = {10.1109/TVLSI.2010.2090543},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AtasuLMOD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AubertinLS12,
author = {P. Aubertin and
J. M. Pierre Langlois and
Yvon Savaria},
title = {Real-Time Computation of Local Neighborhood Functions in Application-Specific
Instruction-Set Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2031--2043},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2170204},
doi = {10.1109/TVLSI.2011.2170204},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AubertinLS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AxelosPG12,
author = {Nicholas Axelos and
Kiamal Z. Pekmestzi and
Dimitris Gizopoulos},
title = {Efficient Memory Repair Using Cache-Based Redundancy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2278--2288},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2170593},
doi = {10.1109/TVLSI.2011.2170593},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AxelosPG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AyinalaBP12,
author = {Manohar Ayinala and
Michael J. Brown and
Keshab K. Parhi},
title = {Pipelined Parallel {FFT} Architectures via Folding Transformation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1068--1081},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2147338},
doi = {10.1109/TVLSI.2011.2147338},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AyinalaBP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AzarderakhshR12,
author = {Reza Azarderakhsh and
Arash Reyhani{-}Masoleh},
title = {Efficient {FPGA} Implementations of Point Multiplication on Binary
Edwards and Generalized Hessian Curves Using Gaussian Normal Basis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1453--1466},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2158595},
doi = {10.1109/TVLSI.2011.2158595},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AzarderakhshR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaccarinEA12,
author = {Davide Baccarin and
David Esseni and
Massimo Alioto},
title = {Mixed {FBB/RBB:} {A} Novel Low-Leakage Technique for FinFET Forced
Stacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1467--1472},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2158614},
doi = {10.1109/TVLSI.2011.2158614},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BaccarinEA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaoAEP12,
author = {Min Bao and
Alexandru Andrei and
Petru Eles and
Zebo Peng},
title = {Temperature-Aware Idle Time Distribution for Leakage Energy Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1187--1200},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2157542},
doi = {10.1109/TVLSI.2011.2157542},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaoAEP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BarrancoTDVR12,
author = {Francisco Barranco and
Matteo Tomasi and
Javier D{\'{\i}}az and
Mauricio Vanegas and
Eduardo Ros},
title = {Parallel Architecture for Hierarchical Optical Flow Estimation Based
on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1058--1067},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2145423},
doi = {10.1109/TVLSI.2011.2145423},
timestamp = {Tue, 10 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BarrancoTDVR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhattacharyyaS12,
author = {Kalyan Bhattacharyya and
Ted H. Szymanski},
title = {Temperature Characteristics and Analysis of Monolithic Microwave {CMOS}
Distributed Oscillators With {\textdollar}\{G\}{\_}\{m\}{\textdollar}-Varied
Gain Cells and Folded Coplanar Interconnects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1332--1336},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2148130},
doi = {10.1109/TVLSI.2011.2148130},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BhattacharyyaS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BucciGLT12,
author = {Marco Bucci and
Luca Giancane and
Raimondo Luzzi and
Alessandro Trifiletti},
title = {A Flip-Flop for the {DPA} Resistant Three-Phase Dual-Rail Pre-Charge
Logic Family},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2128--2132},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2165862},
doi = {10.1109/TVLSI.2011.2165862},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BucciGLT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChakrabortyR12,
author = {Koushik Chakraborty and
Sanghamitra Roy},
title = {Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {512--522},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2105513},
doi = {10.1109/TVLSI.2011.2105513},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabortyR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChandraRD12,
author = {Saumya Chandra and
Anand Raghunathan and
Sujit Dey},
title = {Variation-Aware Voltage Level Selection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {925--936},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2126050},
doi = {10.1109/TVLSI.2011.2126050},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChandraRD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChattopadhyayZ12,
author = {Atanu Chattopadhyay and
Zeljko Zilic},
title = {Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution
Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {523--536},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2104982},
doi = {10.1109/TVLSI.2011.2104982},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChattopadhyayZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenC12,
author = {Yuan{-}Ho Chen and
Tsin{-}Yuan Chang},
title = {A High Performance Video Transform Engine by Using Space-Time Scheduling
Strategy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {655--664},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2110620},
doi = {10.1109/TVLSI.2011.2110620},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenCLH12,
author = {Fu{-}Wei Chen and
Shih{-}Liang Chen and
Yung{-}Sheng Lin and
TingTing Hwang},
title = {A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop
Reduction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2255--2264},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2173361},
doi = {10.1109/TVLSI.2011.2173361},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenCLH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenO12,
author = {Mingjing Chen and
Alex Orailoglu},
title = {Scan Power Reduction for Linear Test Compression Schemes Through Seed
Selection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2170--2183},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2173509},
doi = {10.1109/TVLSI.2011.2173509},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenSHTCC12,
author = {Tse{-}Wei Chen and
Yu{-}Chi Su and
Keng{-}Yen Huang and
Yi{-}Min Tsai and
Shao{-}Yi Chien and
Liang{-}Gee Chen},
title = {Visual Vocabulary Processor Based on Binary Tree Architecture for
Real-Time Object Recognition in Full-HD Resolution},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2329--2332},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2170203},
doi = {10.1109/TVLSI.2011.2170203},
timestamp = {Wed, 14 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenSHTCC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenSS12,
author = {Zhong{-}Ho Chen and
Alvin Wen{-}Yu Su and
Ming{-}Ting Sun},
title = {Resource-Efficient {FPGA} Architecture and Implementation of Hough
Transform},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1419--1428},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160002},
doi = {10.1109/TVLSI.2011.2160002},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenTZC12,
author = {Shoushun Chen and
Wei Tang and
Xiangyu Zhang and
Eugenio Culurciello},
title = {A 64 {\(^\times\)} 64 Pixels {UWB} Wireless Temporal-Difference Digital
Image Sensor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2232--2240},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2172470},
doi = {10.1109/TVLSI.2011.2172470},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenTZC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenWCMY12,
author = {Xiaoming Chen and
Yu Wang and
Yu Cao and
Yuchun Ma and
Huazhong Yang},
title = {Variation-Aware Supply Voltage Assignment for Simultaneous Power and
Aging Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2143--2147},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2168433},
doi = {10.1109/TVLSI.2011.2168433},
timestamp = {Thu, 15 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenWCMY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenYGWS12,
author = {Ning Chen and
Zhiyuan Yan and
Maximilien Gadouleau and
Ying Wang and
Bruce W. Suter},
title = {Rank Metric Decoder Architectures for Random Linear Network Coding
With Error Control},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {296--309},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2096239},
doi = {10.1109/TVLSI.2010.2096239},
timestamp = {Wed, 15 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenYGWS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengGXXHS12,
author = {Lerong Cheng and
Fang Gong and
Wenyao Xu and
Jinjun Xiong and
Lei He and
Majid Sarrafzadeh},
title = {Fourier Series Approximation for Max Operation in Non-Gaussian and
Quadratic Statistical Static Timing Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1383--1391},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2157843},
doi = {10.1109/TVLSI.2011.2157843},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengGXXHS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengHHJ12,
author = {Kuo{-}Hsing Cheng and
Kai{-}Wei Hong and
Chi{-}Fa Hsu and
Bo{-}Qian Jiang},
title = {An All-Digital Clock Synchronization Buffer With One Cycle Dynamic
Synchronizing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1818--1827},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2166092},
doi = {10.1109/TVLSI.2011.2166092},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengHHJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengLH12,
author = {Chang{-}Hsin Cheng and
Yu Liu and
Chun{-}Lung Hsu},
title = {Design of an Error Detection and Data Recovery Architecture for Motion
Estimation Testing Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {665--672},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2109972},
doi = {10.1109/TVLSI.2011.2109972},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengLH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengWKCW12,
author = {Chieh{-}Jen Cheng and
Chao{-}Ching Wang and
Wei{-}Chun Ku and
Tien{-}Fu Chen and
Jinn{-}Shyan Wang},
title = {A Scalable High-Performance Virus Detection Processor Against a Large
Pattern Set for Embedded Network Security},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {841--854},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2119382},
doi = {10.1109/TVLSI.2011.2119382},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengWKCW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChiangWW12,
author = {Cheng{-}Ta Chiang and
Chih{-}Hsien Wang and
Chia{-}Yu Wu},
title = {A {CMOS} {MEMS} Audio Transducer Implemented by Silicon Condenser
Microphone With Analog Front-End Circuits of Audio Codec},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1656--1667},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160746},
doi = {10.1109/TVLSI.2011.2160746},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChiangWW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChiuL12,
author = {Geng{-}Ming Chiu and
James Chien{-}Mo Li},
title = {A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks
for Embedded Cores},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {126--134},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2089071},
doi = {10.1109/TVLSI.2010.2089071},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChiuL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoCKPH12,
author = {Young In Cho and
Nam Su Chang and
Chang Han Kim and
Young{-}Ho Park and
Seokhie Hong},
title = {New Bit Parallel Multiplier With Low Space Complexity for All Irreducible
Trinomials Over GF(2\({}^{\mbox{n}}\))},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1903--1908},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2162594},
doi = {10.1109/TVLSI.2011.2162594},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoCKPH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoLLR12,
author = {Sang{-}Hyun Cho and
Chang{-}Kyo Lee and
Sang{-}Gug Lee and
Seung{-}Tak Ryu},
title = {A Two-Channel Asynchronous {SAR} {ADC} With Metastable-Then-Set Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {765--769},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2109743},
doi = {10.1109/TVLSI.2011.2109743},
timestamp = {Wed, 02 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoLLR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoiKL12,
author = {Jaehyouk Choi and
Woonyun Kim and
Kyutae Lim},
title = {A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump
{PLL}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {969--973},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2129602},
doi = {10.1109/TVLSI.2011.2129602},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoiKL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ConsoliPP12,
author = {Elio Consoli and
Gaetano Palumbo and
Melita Pennisi},
title = {Reconsidering High-Speed Design Criteria for Transmission-Gate-Based
Master-Slave Flip-Flops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {284--295},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2098426},
doi = {10.1109/TVLSI.2010.2098426},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ConsoliPP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CostagliolaCGIRSS12,
author = {Maurizio Costagliola and
Davide De Caro and
Antonio Girardi and
Roberto Izzi and
Niccol{\`{o}} Rinaldi and
M. Spirito and
P. Spirito},
title = {An Experimental Power-Lines Model for Digital ASICs Based on Transmission
Lines},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {162--166},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2090368},
doi = {10.1109/TVLSI.2010.2090368},
timestamp = {Mon, 12 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CostagliolaCGIRSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CrupiAFMKGMWH12,
author = {Felice Crupi and
Massimo Alioto and
Jacopo Franco and
Paolo Magnone and
Ben Kaczer and
Guido Groeseneken and
J{\'{e}}r{\^{o}}me Mitard and
Liesbeth Witters and
Thomas Y. Hoffmann},
title = {Buried Silicon-Germanium pMOSFETs: Experimental Analysis in {VLSI}
Logic Circuits Under Aggressive Voltage Scaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1487--1495},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2159870},
doi = {10.1109/TVLSI.2011.2159870},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CrupiAFMKGMWH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DaiLL12,
author = {Ke{-}Ren Dai and
Wen{-}Hao Liu and
Yih{-}Lang Li},
title = {{NCTU-GR:} Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed
Layer Assignment on 3-D Global Routing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {459--472},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2102780},
doi = {10.1109/TVLSI.2010.2102780},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DaiLL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DehbaouiLOTRM12,
author = {Amine Dehbaoui and
Victor Lomn{\'{e}} and
Thomas Ordas and
Lionel Torres and
Michel Robert and
Philippe Maurine},
title = {Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {573--577},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2104984},
doi = {10.1109/TVLSI.2011.2104984},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DehbaouiLOTRM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DongPXVZ12,
author = {Guiqiang Dong and
Yangyang Pan and
Ningde Xie and
Chandra Varanasi and
Tong Zhang},
title = {Estimating Information-Theoretical nand Flash Memory Storage Capacity
and its Implication to Memory System Design Space Exploration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1705--1714},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160747},
doi = {10.1109/TVLSI.2011.2160747},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DongPXVZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EguiaTSLPTW12,
author = {Thom Jefferson A. Eguia and
Sheldon X.{-}D. Tan and
Ruijing Shen and
Duo Li and
Eduardo H. Pacheco and
Murli Tirumala and
Lingli Wang},
title = {General Parameterized Thermal Modeling for High-Performance Microprocessor
Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {211--224},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2098054},
doi = {10.1109/TVLSI.2010.2098054},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EguiaTSLPTW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ErbP12,
author = {Stefan Erb and
Wolfgang Pribyl},
title = {Design Specification for {BER} Analysis Methods Using Built-In Jitter
Measurements},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1804--1817},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2163325},
doi = {10.1109/TVLSI.2011.2163325},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ErbP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EsmaeiliAC12,
author = {Seyed Ebrahim Esmaeili and
Asim J. Al{-}Khalili and
Glenn E. R. Cowan},
title = {Low-Swing Differential Conditional Capturing Flip-Flop for {LC} Resonant
Clock Distribution Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1547--1551},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2158613},
doi = {10.1109/TVLSI.2011.2158613},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EsmaeiliAC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangCJPT12,
author = {Hongxia Fang and
Krishnendu Chakrabarty and
Abhijit Jas and
Srinivas Patil and
Chandra Tirumurti},
title = {Functional Test-Sequence Grading at Register-Transfer Level},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1890--1894},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2163651},
doi = {10.1109/TVLSI.2011.2163651},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FangCJPT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangS12,
author = {Jianxin Fang and
Sachin S. Sapatnekar},
title = {Scalable Methods for Analyzing the Circuit Failure Probability Due
to Gate Oxide Breakdown},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {1960--1973},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2166568},
doi = {10.1109/TVLSI.2011.2166568},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FangS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FaruqueEH12,
author = {Mohammad Abdullah Al Faruque and
Thomas Ebi and
J{\"{o}}rg Henkel},
title = {AdNoC: Runtime Adaptive Network-on-Chip Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {257--269},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2094215},
doi = {10.1109/TVLSI.2010.2094215},
timestamp = {Thu, 25 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FaruqueEH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FeiYZY12,
author = {Wei Fei and
Hao Yu and
Wei Zhang and
Kiat Seng Yeo},
title = {Design Exploration of Hybrid {CMOS} and Memristor Circuit by New Modified
Nodal Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1012--1025},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2136443},
doi = {10.1109/TVLSI.2011.2136443},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FeiYZY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuLL12,
author = {Xiang Fu and
Huawei Li and
Xiaowei Li},
title = {Testable Path Selection and Grouping for Faster Than At-Speed Testing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {236--247},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2099243},
doi = {10.1109/TVLSI.2010.2099243},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FuLL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuketaHMO12,
author = {Hiroshi Fuketa and
Masanori Hashimoto and
Yukio Mitsuyama and
Takao Onoye},
title = {Adaptive Performance Compensation With In-Situ Timing Error Predictive
Sensors for Subthreshold Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {333--343},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2101089},
doi = {10.1109/TVLSI.2010.2101089},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FuketaHMO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Garcia-HerreroCVM12,
author = {Francisco Garcia{-}Herrero and
Mar{\'{\i}}a Jos{\'{e}} Canet and
Javier Valls and
Pramod Kumar Meher},
title = {High-Throughput Interpolator Architecture for Low-Complexity Chase
Decoding of {RS} Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {568--573},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2103961},
doi = {10.1109/TVLSI.2010.2103961},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Garcia-HerreroCVM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GargM12,
author = {Siddharth Garg and
Diana Marculescu},
title = {System-Level Leakage Variability Mitigation for MPSoC Platforms Using
Body-Bias Islands},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2289--2301},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2171512},
doi = {10.1109/TVLSI.2011.2171512},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GargM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GeQW12,
author = {Yang Ge and
Qinru Qiu and
Qing Wu},
title = {A Multi-Agent Framework for Thermal Aware Task Migration in Many-Core
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1758--1771},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2162348},
doi = {10.1109/TVLSI.2011.2162348},
timestamp = {Tue, 28 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GeQW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GengZLSWW12,
author = {Yongtao Geng and
Huan Zou and
Chaojiang Li and
Jiwei Sun and
Haibo Wang and
Pingshan Wang},
title = {Short Pulse Generation With On-Chip Pulse-Forming Lines},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1553--1564},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160103},
doi = {10.1109/TVLSI.2011.2160103},
timestamp = {Thu, 09 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GengZLSWW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GongYWH12,
author = {Fang Gong and
Hao Yu and
Lingli Wang and
Lei He},
title = {A Parallel and Incremental Extraction of Variational Capacitance With
Stochastic Geometric Moments},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1729--1737},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161352},
doi = {10.1109/TVLSI.2011.2161352},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GongYWH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GortPKAHWY12,
author = {Marcel Gort and
Flavio M. de Paula and
Johnny J. W. Kuan and
Tor M. Aamodt and
Alan J. Hu and
Steven J. E. Wilton and
Jin Yang},
title = {Formal-Analysis-Based Trace Computation for Post-Silicon Debug},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {1997--2010},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2166416},
doi = {10.1109/TVLSI.2011.2166416},
timestamp = {Mon, 17 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GortPKAHWY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GoyalSCHC12,
author = {Abhilash Goyal and
Madhavan Swaminathan and
Abhijit Chatterjee and
Duane C. Howard and
John D. Cressler},
title = {A New Self-Healing Methodology for {RF} Amplifier Circuits Based on
Oscillation Principles},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1835--1848},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2163953},
doi = {10.1109/TVLSI.2011.2163953},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GoyalSCHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GraciaDAKY12,
author = {Dar{\'{\i}}o Su{\'{a}}rez Gracia and
Giorgos Dimitrakopoulos and
Teresa Monreal Arnal and
Manolis Katevenis and
V{\'{\i}}ctor Vi{\~{n}}als Y{\'{u}}fera},
title = {{LP-NUCA:} Networks-in-Cache for High-Performance Low-Power Embedded
Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1510--1523},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2158249},
doi = {10.1109/TVLSI.2011.2158249},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GraciaDAKY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GriffinRR12,
author = {W. Paul Griffin and
Anand Raghunathan and
Kaushik Roy},
title = {{CLIP:} Circuit Level {IC} Protection Through Direct Injection of
Process Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {791--803},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2135868},
doi = {10.1109/TVLSI.2011.2135868},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GriffinRR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuWGZS12,
author = {Junhui Gu and
Jianhui Wu and
Danhong Gu and
Meng Zhang and
Longxing Shi},
title = {All-Digital Wide Range Precharge Logic 50{\%} Duty Cycle Corrector},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {760--764},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2111424},
doi = {10.1109/TVLSI.2011.2111424},
timestamp = {Mon, 07 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuWGZS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuanFL12,
author = {Xuan Guan and
Yunsi Fei and
Hai Lin},
title = {Hierarchical Design of an Application-Specific Instruction Set Processor
for High-Throughput and Scalable {FFT} Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {551--563},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2105512},
doi = {10.1109/TVLSI.2011.2105512},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GuanFL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuptaS12,
author = {Saket Gupta and
Sachin S. Sapatnekar},
title = {Compact Current Source Models for Timing Analysis Under Temperature
and Body Bias Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2104--2117},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2169686},
doi = {10.1109/TVLSI.2011.2169686},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuptaS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HaWMXCH12,
author = {Dongwan Ha and
Kyoungho Woo and
Scott E. Meninger and
Thucydides Xanthopoulos and
Ethan Crain and
Donhee Ham},
title = {Time-Domain {CMOS} Temperature Sensors With Dual Delay-Locked Loops
for Microprocessor Thermal Monitoring},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1590--1601},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161783},
doi = {10.1109/TVLSI.2011.2161783},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HaWMXCH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HaghdadA12,
author = {Kian Haghdad and
Mohab Anis},
title = {Power Yield Analysis Under Process and Temperature Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1794--1803},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2163535},
doi = {10.1109/TVLSI.2011.2163535},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HaghdadA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HanYLPOP12,
author = {Jung{-}Won Han and
Kwisung Yoo and
Dongmyung Lee and
Kangyeob Park and
Wonseok Oh and
Sung Min Park},
title = {A Low-Power Gigabit {CMOS} Limiting Amplifier Using Negative Impedance
Compensation and Its Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {393--399},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2104333},
doi = {10.1109/TVLSI.2010.2104333},
timestamp = {Fri, 04 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HanYLPOP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HasanNN12,
author = {M. Anwar Hasan and
Ashkan Hosseinzadeh Namin and
Christophe N{\`{e}}gre},
title = {Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {449--458},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2106524},
doi = {10.1109/TVLSI.2011.2106524},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HasanNN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Hashemian12,
author = {Reza Hashemian},
title = {Application of Fixator-Norator Pairs in Designing Active Loads and
Current Mirrors in Analog Integrated Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2220--2231},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2172229},
doi = {10.1109/TVLSI.2011.2172229},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Hashemian12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HassanVS12,
author = {Faiz{-}ul Hassan and
Wim Vanderbauwhede and
Fernando Rodr{\'{\i}}guez Salazar},
title = {Impact of Random Dopant Fluctuations on the Timing Characteristics
of Flip-Flops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {157--161},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2088409},
doi = {10.1109/TVLSI.2010.2088409},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HassanVS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeDJBP12,
author = {Ou He and
Sheqin Dong and
Wooyoung Jang and
Jinian Bian and
David Z. Pan},
title = {{UNISM:} Unified Scheduling and Mapping for General Networks on Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1496--1509},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2159280},
doi = {10.1109/TVLSI.2011.2159280},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeDJBP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeLWHZ12,
author = {Jinjin He and
Huaping Liu and
Zhongfeng Wang and
Xinming Huang and
Kai Zhang},
title = {High-Speed Low-Power Viterbi Decoder Design for {TCM} Decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {755--759},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2111392},
doi = {10.1109/TVLSI.2011.2111392},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeLWHZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HealyL12,
author = {Michael B. Healy and
Sung Kyu Lim},
title = {Distributed {TSV} Topology for 3-D Power-Supply Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2066--2079},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2167359},
doi = {10.1109/TVLSI.2011.2167359},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HealyL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HedayatiB12,
author = {Hiva Hedayati and
Bertan Bakkaloglu},
title = {A 3 GHz Wideband {\(\Sigma\)} {\(\Delta\)} Fractional-N Synthesizer
With Switched-RC Sample-and-Hold {PFD}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1681--1690},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161500},
doi = {10.1109/TVLSI.2011.2161500},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HedayatiB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HerbertGM12,
author = {Sebastian Herbert and
Siddharth Garg and
Diana Marculescu},
title = {Exploiting Process Variability in Voltage/Frequency Control},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1392--1404},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160001},
doi = {10.1109/TVLSI.2011.2160001},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HerbertGM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HongSL12,
author = {Fei Hong and
Aviral Shrivastava and
Jongeun Lee},
title = {Return Data Interleaving for Multi-Channel Embedded CMPs Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1351--1354},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2157368},
doi = {10.1109/TVLSI.2011.2157368},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HongSL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HonkoteT12,
author = {Vinayak Honkote and
Baris Taskin},
title = {ZeROA: Zero Clock Skew Rotary Oscillatory Array},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1528--1532},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2158458},
doi = {10.1109/TVLSI.2011.2158458},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HonkoteT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HoyosTVCAKN12,
author = {Sebastian Hoyos and
Cheongyuen W. Tsang and
Johan P. Vanderhaegen and
Yun Chiu and
Yasutoshi Aibara and
Haideh Khorramabadi and
Borivoje Nikolic},
title = {A 15 MHz to 600 MHz, 20 mW, 0.38 mm\({}^{\mbox{2}}\) Split-Control,
Fast Coarse Locking Digital {DLL} in 0.13 {\(\mathrm{\mu}\)} m {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {564--568},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2106170},
doi = {10.1109/TVLSI.2011.2106170},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HoyosTVCAKN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsiehFHSC12,
author = {Chien{-}Yu Hsieh and
Ming{-}Long Fan and
Vita Pi{-}Ho Hu and
Pin Su and
Ching{-}Te Chuang},
title = {Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold
SRAMs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1201--1210},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2156435},
doi = {10.1109/TVLSI.2011.2156435},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsiehFHSC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsiehH12,
author = {Ang{-}Chih Hsieh and
TingTing Hwang},
title = {{TSV} Redundancy: Architecture and Design Issues in 3-D {IC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {711--722},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2107924},
doi = {10.1109/TVLSI.2011.2107924},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsiehH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsiehH12a,
author = {Wei{-}Chih Hsieh and
Wei Hwang},
title = {All Digital Linear Voltage Regulator for Super- to Near-Threshold
Operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {989--1001},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2143438},
doi = {10.1109/TVLSI.2011.2143438},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsiehH12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsiehH12b,
author = {Ang{-}Chih Hsieh and
TingTing Hwang},
title = {Run-Time Reconfiguration of Expandable Cache for Embedded Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1863--1875},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2163534},
doi = {10.1109/TVLSI.2011.2163534},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsiehH12b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsuC12,
author = {Terng{-}Yin Hsu and
Shau{-}Yu Cheng},
title = {Low-Complexity Sequential Searcher for Robust Symbol Synchronization
in {OFDM} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {959--963},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2136390},
doi = {10.1109/TVLSI.2011.2136390},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsuC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuWC12,
author = {Kangmin Hu and
Larry Wu and
Patrick Yin Chiang},
title = {A Comparative Study of 20-Gb/s {NRZ} and Duobinary Signaling Using
Statistical Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1336--1341},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2148131},
doi = {10.1109/TVLSI.2011.2148131},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuWC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangCLLCHLCL12,
author = {Shao{-}Chang Huang and
Ke{-}Horng Chen and
Weiyao Lin and
Zon{-}Lon Lee and
Kun{-}Wei Chang and
Erica Hsu and
Wenson Lee and
Lin{-}Fwu Chen and
Chris Chun{-}Hung Lu},
title = {Embedded {I/O} {PAD} Circuit Design for {OTP} Memory Power-Switch
Functionality},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {746--750},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2106808},
doi = {10.1109/TVLSI.2011.2106808},
timestamp = {Tue, 18 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangCLLCHLCL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangL12,
author = {Yu{-}Jen Huang and
Jin{-}Fu Li},
title = {Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced
{IEEE} 1500 Test Wrappers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2123--2127},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2165568},
doi = {10.1109/TVLSI.2011.2165568},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangHKPM12,
author = {Seokjoong Hwang and
Youngsun Han and
Seon Wook Kim and
Jongsun Park and
Byung Gueon Min},
title = {Resource Efficient Implementation of Low Power {MB-OFDM} {PHY} Baseband
Modem With Highly Parallel Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1248--1261},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2148132},
doi = {10.1109/TVLSI.2011.2148132},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangHKPM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangL12,
author = {Yin{-}Tsung Hwang and
Jin{-}Fa Lin},
title = {Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass
Transistor Logic Circuit Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1738--1742},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161598},
doi = {10.1109/TVLSI.2011.2161598},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangLS12,
author = {Yin{-}Tsung Hwang and
Jin{-}Fa Lin and
Ming{-}Hwa Sheu},
title = {Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement
Scheme},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {361--366},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2096483},
doi = {10.1109/TVLSI.2010.2096483},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangLS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JainJ12,
author = {Palkesh Jain and
Ankit Jain},
title = {Accurate Current Estimation for Interconnect Reliability Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1634--1644},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160882},
doi = {10.1109/TVLSI.2011.2160882},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JainJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JangFB12,
author = {Jinwook Jang and
Olivier Franza and
Wayne P. Burleson},
title = {Compact Expressions for Supply Noise Induced Period Jitter of Global
Binary Clock Trees},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {66--79},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2089706},
doi = {10.1109/TVLSI.2010.2089706},
timestamp = {Mon, 06 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JangFB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JangKYC12,
author = {Tae{-}Kwang Jang and
Jaewook Kim and
Young{-}Gyu Yoon and
SeongHwan Cho},
title = {A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase
Interpolator and Digital Calibration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1368--1372},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2159635},
doi = {10.1109/TVLSI.2011.2159635},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JangKYC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiangC12,
author = {Iris Hui{-}Ru Jiang and
Hua{-}Yu Chang},
title = {{ECOS:} Stable Matching Based Metal-Only {ECO} Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {485--497},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2104377},
doi = {10.1109/TVLSI.2011.2104377},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiangC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiangCC12,
author = {Iris Hui{-}Ru Jiang and
Hua{-}Yu Chang and
Chih{-}Long Chang},
title = {WiT: Optimal Wiring Topology for Electromigration Avoidance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {581--592},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2116049},
doi = {10.1109/TVLSI.2011.2116049},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiangCC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiangP12,
author = {Weirong Jiang and
Viktor K. Prasanna},
title = {Scalable Packet Classification on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1668--1680},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2162112},
doi = {10.1109/TVLSI.2011.2162112},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiangP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiangXCM12,
author = {Li Jiang and
Qiang Xu and
Krishnendu Chakrabarty and
T. M. Mak},
title = {Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling
for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1621--1633},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160410},
doi = {10.1109/TVLSI.2011.2160410},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiangXCM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiaoK12,
author = {Hailong Jiao and
Volkan Kursun},
title = {Threshold Voltage Tuning for Faster Activation With Lower Noise in
Tri-Mode {MTCMOS} Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {741--745},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2110663},
doi = {10.1109/TVLSI.2011.2110663},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiaoK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoshiMAB12,
author = {Rimesh M. Joshi and
Arjuna Madanayake and
Jithra Adikari and
Leonard T. Bruton},
title = {Synthesis and Array Processor Realization of a 2-D {IIR} Beam Filter
for Wireless Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2241--2254},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2174167},
doi = {10.1109/TVLSI.2011.2174167},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JoshiMAB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KahngLPS12,
author = {Andrew B. Kahng and
Bin Li and
Li{-}Shiuan Peh and
Kambiz Samadi},
title = {{ORION} 2.0: {A} Power-Area Simulator for Interconnection Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {191--196},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2091686},
doi = {10.1109/TVLSI.2010.2091686},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KahngLPS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KaoMSP12,
author = {Jerry C. Kao and
Wei{-}Hsiang Ma and
Visvesh S. Sathe and
Marios C. Papaefthymiou},
title = {Energy-Efficient Low-Latency 600 MHz {FIR} With High-Overdrive Charge-Recovery
Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {977--988},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2140346},
doi = {10.1109/TVLSI.2011.2140346},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KaoMSP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KatohNI12,
author = {Kentaroh Katoh and
Kazuteru Namba and
Hideo Ito},
title = {An On-Chip Delay Measurement Technique Using Signature Registers for
Small-Delay Defect Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {804--817},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2125994},
doi = {10.1109/TVLSI.2011.2125994},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KatohNI12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhodabandehlooMA12,
author = {Golnar Khodabandehloo and
Mitra Mirhassani and
Majid Ahmadi},
title = {Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {750--754},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2109404},
doi = {10.1109/TVLSI.2011.2109404},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhodabandehlooMA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhurramH12,
author = {Muhammad Khurram and
S. M. Rezaul Hasan},
title = {A 3-5 GHz Current-Reuse g\({}_{\mbox{m}}\)-Boosted {CG} {LNA} for
Ultrawideband in 130 nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {400--409},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2106229},
doi = {10.1109/TVLSI.2011.2106229},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhurramH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimCYHJC12,
author = {Sokehwan Kim and
Hyunho Chu and
Isaak Yang and
Sanghoon Hong and
Sung Hoon Jung and
Kwang{-}Hyun Cho},
title = {A Hierarchical Self-Repairing Architecture for Fast Fault Recovery
of Digital Systems Inspired From Paralogous Gene Regulatory Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2315--2328},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2176544},
doi = {10.1109/TVLSI.2011.2176544},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimCYHJC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimDZKGP12,
author = {Nam Sung Kim and
Stark C. Draper and
Shi{-}Ting Zhou and
Sumeet Katariya and
Hamid Reza Ghasemi and
Taejoon Park},
title = {Analyzing the Impact of Joint Optimization of Cell Size, Redundancy,
and {ECC} on Low-Voltage {SRAM} Array Total Area},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2333--2337},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2173220},
doi = {10.1109/TVLSI.2011.2173220},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimDZKGP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimKKPPK12,
author = {Young{-}Jun Kim and
Hyo{-}Eun Kim and
Seok{-}Hoon Kim and
Jun{-}Seok Park and
Seungwook Paek and
Lee{-}Sup Kim},
title = {Homogeneous Stream Processors With Embedded Special Function Units
for High-Utilization Programmable Shaders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1691--1704},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161499},
doi = {10.1109/TVLSI.2011.2161499},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimKKPPK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimLK12,
author = {Moo{-}young Kim and
Hokyu Lee and
Chulwoo Kim},
title = {{PVT} Variation Tolerant Current Source With On-Chip Digital Self-Calibration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {737--741},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2109971},
doi = {10.1109/TVLSI.2011.2109971},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimLK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimRKJ12,
author = {Jisu Kim and
Kyungho Ryu and
Seung{-}Hyuk Kang and
Seong{-}Ook Jung},
title = {A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque {MRAM}
{(STT-MRAM)}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {181--186},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2088143},
doi = {10.1109/TVLSI.2010.2088143},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimRKJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimSSS12,
author = {Nam Sung Kim and
Abhishek A. Sinkar and
Jun Seomun and
Youngsoo Shin},
title = {Maximizing Frequency and Yield of Power-Constrained Designs Using
Programmable Power-Gating},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1885--1890},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2163533},
doi = {10.1109/TVLSI.2011.2163533},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimSSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimYCKKCK12,
author = {Seok{-}Hoon Kim and
Sung{-}Eui Yoon and
Sang{-}Hye Chung and
Young{-}Jun Kim and
Hong{-}Yun Kim and
Kyusik Chung and
Lee{-}Sup Kim},
title = {A Mobile 3-D Display Processor With {A} Bandwidth-Saving Subdivider},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1082--1093},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2150253},
doi = {10.1109/TVLSI.2011.2150253},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimYCKKCK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KnezevicKIMSKFKSSVOHA12,
author = {Miroslav Knezevic and
Kazuyuki Kobayashi and
Jun Ikegami and
Shin'ichiro Matsuo and
Akashi Satoh and
{\"{U}}nal Ko{\c{c}}abas and
Junfeng Fan and
Toshihiro Katashita and
Takeshi Sugawara and
Kazuo Sakiyama and
Ingrid Verbauwhede and
Kazuo Ohta and
Naofumi Homma and
Takafumi Aoki},
title = {Fair and Consistent Hardware Evaluation of Fourteen Round Two {SHA-3}
Candidates},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {827--840},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2128353},
doi = {10.1109/TVLSI.2011.2128353},
timestamp = {Fri, 26 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KnezevicKIMSKFKSSVOHA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KongPOMMC12,
author = {Joonho Kong and
Yan Pan and
Serkan Ozdemir and
Anitha Mohan and
Gokhan Memik and
Sung Woo Chung},
title = {Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under
Process Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1532--1536},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2159634},
doi = {10.1109/TVLSI.2011.2159634},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KongPOMMC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KuanWWLG12,
author = {Ta{-}Wen Kuan and
Jhing{-}Fa Wang and
Jia{-}Ching Wang and
Po{-}Chuan Lin and
Gaung{-}Hui Gu},
title = {{VLSI} Design of an {SVM} Learning Core on Sequential Minimal Optimization
Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {673--683},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2107533},
doi = {10.1109/TVLSI.2011.2107533},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KuanWWLG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KulkarniKJXS12,
author = {Raghavendra Kulkarni and
Jusung Kim and
Hyung{-}Joon Jeon and
Jianhong Xiao and
Jos{\'{e}} Silva{-}Mart{\'{\i}}nez},
title = {{UHF} Receiver Front-End: Implementation and Analog Baseband Design
Considerations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {197--210},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2096438},
doi = {10.1109/TVLSI.2010.2096438},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KulkarniKJXS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KulkarniR12,
author = {Jaydeep P. Kulkarni and
Kaushik Roy},
title = {Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based
{SRAM} Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {319--332},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2100834},
doi = {10.1109/TVLSI.2010.2100834},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KulkarniR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarV12,
author = {Jayanand Asok Kumar and
Shobha Vasudevan},
title = {Formal Performance Analysis for Faulty {MIMO} Hardware},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1914--1918},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2164103},
doi = {10.1109/TVLSI.2011.2164103},
timestamp = {Wed, 27 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KwonYLP12,
author = {Suknam Kwon and
Sungjoo Yoo and
Sunggu Lee and
Jinpyo Park},
title = {Optimizing Video Application Design for Phase-Change RAM-Based Main
Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2011--2019},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2165974},
doi = {10.1109/TVLSI.2011.2165974},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KwonYLP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeHHHMF12,
author = {Jim Le and
Christopher Hanken and
Martin Held and
Michael S. Hagedorn and
Kartikeya Mayaram and
Terri S. Fiez},
title = {Experimental Characterization and Analysis of an Asynchronous Approach
for Reduction of Substrate Noise in Digital Circuitry},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {344--356},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2100835},
doi = {10.1109/TVLSI.2010.2100835},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeHHHMF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeHWC12,
author = {Yu{-}Huei Lee and
Shao{-}Chang Huang and
Shih{-}Wei Wang and
Ke{-}Horng Chen},
title = {Fast Transient {(FT)} Technique With Adaptive Phase Margin {(APM)}
for Current Mode {DC-DC} Buck Converters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1781--1793},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2163093},
doi = {10.1109/TVLSI.2011.2163093},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeHWC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeK12,
author = {Jungseob Lee and
Nam Sung Kim},
title = {Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained
Multicore Processors by Exploiting {DVFS} and {PCPG}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {225--235},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2092795},
doi = {10.1109/TVLSI.2010.2092795},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeK12a,
author = {Won{-}Young Lee and
Lee{-}Sup Kim},
title = {An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort
Main Link in 0.18-{\(\mathrm{\mu}\)}m {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {964--968},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2130546},
doi = {10.1109/TVLSI.2011.2130546},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeK12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeKK12,
author = {Younghoon Lee and
Jungsoo Kim and
Chong{-}Min Kyung},
title = {Energy-Aware Video Encoding for Image Quality Improvement in Battery-Operated
Surveillance Camera},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {310--318},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2102055},
doi = {10.1109/TVLSI.2010.2102055},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeKK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeV12,
author = {Sang Hyun Lee and
Sriram Vishwanath},
title = {Boolean Functions Over Nano-Fabrics: Improving Resilience Through
Coding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2054--2065},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2166417},
doi = {10.1109/TVLSI.2011.2166417},
timestamp = {Fri, 31 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiCCDT12,
author = {Chung{-}Yi Li and
Yuan{-}Ho Chen and
Tsin{-}Yuan Chang and
Lih{-}Yuan Deng and
Kiwing To},
title = {Period Extension and Randomness Enhancement Using High-Throughput
Reseeding-Mixing {PRNG}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {385--389},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2103332},
doi = {10.1109/TVLSI.2010.2103332},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiCCDT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiLL12,
author = {Yunlei Li and
Jin Liu and
Hoi Lee},
title = {Ground Switching Load Modulation With Ground Isolation for Passive
{HF} {RFID} Transponders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1443--1452},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160102},
doi = {10.1109/TVLSI.2011.2160102},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiLL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiMCDMSMJVSS12,
author = {Zheng Li and
Moustafa Mohamed and
Xi Chen and
Eric Dudley and
Ke Meng and
Li Shang and
Alan Rolf Mickelson and
Russ Joseph and
Manish Vachharajani and
Brian Schwartz and
Yihe Sun},
title = {Reliability Modeling and Management of Nanophotonic On-Chip Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {98--111},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2089072},
doi = {10.1109/TVLSI.2010.2089072},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiMCDMSMJVSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiYWSPZ12,
author = {Li Li and
Bo Yuan and
Zhongfeng Wang and
Jin Sha and
Hongbing Pan and
Weishan Zheng},
title = {Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error
Correction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1346--1350},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2154369},
doi = {10.1109/TVLSI.2011.2154369},
timestamp = {Mon, 20 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiYWSPZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinH12,
author = {Jai{-}Ming Lin and
Zhi{-}Xiong Hung},
title = {SKB-Tree: {A} Fixed-Outline Driven Representation for Modern Floorplanning
Problems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {473--484},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2104983},
doi = {10.1109/TVLSI.2011.2104983},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinZJ12,
author = {Ting{-}Jung Lin and
Wei Zhang and
Niraj K. Jha},
title = {SRAM-Based {NATURE:} {A} Dynamically Reconfigurable {FPGA} Based on
10T Low-Power SRAMs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2151--2156},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2169996},
doi = {10.1109/TVLSI.2011.2169996},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinZJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuBG12,
author = {Kai Liu and
Evgeniy Belyaev and
Jie Guo},
title = {{VLSI} Architecture of Arithmetic Coder Used in {SPIHT}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {697--710},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2109068},
doi = {10.1109/TVLSI.2011.2109068},
timestamp = {Wed, 05 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuBG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuLWQ12,
author = {Shaobo Liu and
Jun Lu and
Qing Wu and
Qinru Qiu},
title = {Harvesting-Aware Power Management for Real-Time Systems With Renewable
Energy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1473--1486},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2159820},
doi = {10.1109/TVLSI.2011.2159820},
timestamp = {Tue, 28 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuLWQ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuRM12,
author = {Shih{-}Fu Liu and
Pedro Reviriego and
Juan Antonio Maestro},
title = {Efficient Majority Logic Fault Detection With Difference-Set Codes
for Memory Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {148--156},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2091432},
doi = {10.1109/TVLSI.2010.2091432},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuRM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuWQSG12,
author = {Duo Liu and
Yi Wang and
Zhiwei Qin and
Zili Shao and
Yong Guan},
title = {A Space Reuse Strategy for Flash Translation Layers in {SLC} {NAND}
Flash Memory Storage Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1094--1107},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2142015},
doi = {10.1109/TVLSI.2011.2142015},
timestamp = {Fri, 10 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuWQSG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuC12,
author = {Tai{-}You Lu and
Wei{-}Zen Chen},
title = {A 3-10 GHz, 14 Bands {CMOS} Frequency Synthesizer With Spurs Reduction
for {MB-OFDM} {UWB} System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {948--958},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2134874},
doi = {10.1109/TVLSI.2011.2134874},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuCS12,
author = {Jingwei Lu and
Wing{-}Kai Chow and
Chiu{-}Wing Sham},
title = {Fast Power- and Slew-Aware Gated Clock Tree Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2094--2103},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2168834},
doi = {10.1109/TVLSI.2011.2168834},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuCS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuTT12,
author = {Jianchao Lu and
Ying Teng and
Baris Taskin},
title = {A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1002--1011},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2147339},
doi = {10.1109/TVLSI.2011.2147339},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuTT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaCL12,
author = {Chixiang Ma and
Hao Cao and
Ping Lin},
title = {A Low-Power Low-Cost Design of Primary Synchronization Signal Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1161--1166},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2152866},
doi = {10.1109/TVLSI.2011.2152866},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaCL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaityM12,
author = {Biswajit Maity and
Pradip Mandal},
title = {A High Performance Switched Capacitor-Based {DC-DC} Buck Converter
Suitable for Embedded Power Management Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1880--1885},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2163206},
doi = {10.1109/TVLSI.2011.2163206},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaityM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MakC12,
author = {Wai{-}Kei Mak and
Chris Chu},
title = {Rethinking the Wirelength Benefit of 3-D Integration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2346--2351},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2176353},
doi = {10.1109/TVLSI.2011.2176353},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MakC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MannHNC12,
author = {Randy W. Mann and
Terry B. Hook and
Phung T. Nguyen and
Benton H. Calhoun},
title = {Nonrandom Device Mismatch Considerations in Nanoscale {SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1211--1220},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2158863},
doi = {10.1109/TVLSI.2011.2158863},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MannHNC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ManthenaDBY12,
author = {Manthena Vamshi Krishna and
Manh Anh Do and
Chirn Chye Boon and
Kiat Seng Yeo},
title = {A Low-Power Single-Phase Clock Multiband Flexible Divider},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {376--380},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2100052},
doi = {10.1109/TVLSI.2010.2100052},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ManthenaDBY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MbayeBSP12,
author = {Mame Maria Mbaye and
Normand B{\'{e}}langer and
Yvon Savaria and
Samuel Pierre},
title = {Loop Acceleration Exploration for {ASIP} Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {684--696},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2107923},
doi = {10.1109/TVLSI.2011.2107923},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MbayeBSP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MehtaA12,
author = {Nandish Ashutosh Mehta and
Bharadwaj Amrutur},
title = {Dynamic Supply and Threshold Voltage Scaling for {CMOS} Digital Circuits
Using In-Situ Power Monitor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {892--901},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2132765},
doi = {10.1109/TVLSI.2011.2132765},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MehtaA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MeijerG12,
author = {Maurice Meijer and
Jos{\'{e}} Pineda de Gyvez},
title = {Body-Bias-Driven Design Strategy for Area- and Performance-Efficient
{CMOS} Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {42--51},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2091974},
doi = {10.1109/TVLSI.2010.2091974},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MeijerG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MinJKCSKK12,
author = {Young{-}Jae Min and
Chan{-}Hui Jeong and
Kyu{-}Young Kim and
Won Ho Choi and
Jong{-}Pil Son and
Chulwoo Kim and
Soo{-}Won Kim},
title = {A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation
Register for {DDR} {DRAM} Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1524--1528},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2158011},
doi = {10.1109/TVLSI.2011.2158011},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MinJKCSKK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MoradiKEP12,
author = {Amir Moradi and
Mario Kirschbaum and
Thomas Eisenbarth and
Christof Paar},
title = {Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power
Analysis Methods},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1578--1589},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160375},
doi = {10.1109/TVLSI.2011.2160375},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MoradiKEP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MostafaAE12,
author = {Hassan Mostafa and
Mohab Anis and
Mohamed I. Elmasry},
title = {On-Chip Process Variations Compensation Using an Analog Adaptive Body
Bias {(A-ABB)}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {770--774},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2107583},
doi = {10.1109/TVLSI.2011.2107583},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MostafaAE12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Mutyam12,
author = {Madhu Mutyam},
title = {Fibonacci Codes for Crosstalk Avoidance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1899--1903},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2162010},
doi = {10.1109/TVLSI.2011.2162010},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Mutyam12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NeophytouM12,
author = {Stelios Neophytou and
Maria K. Michael},
title = {Test Pattern Generation of Relaxed n-Detect Test Sets},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {410--423},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2102056},
doi = {10.1109/TVLSI.2010.2102056},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NeophytouM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NigussieTPIT12,
author = {Ethiopia Nigussie and
Sampo Tuuna and
Juha Plosila and
Jouni Isoaho and
Hannu Tenhunen},
title = {Semi-Serial On-Chip Link Implementation for Energy Efficiency and
High Throughput},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2265--2277},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2170228},
doi = {10.1109/TVLSI.2011.2170228},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NigussieTPIT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NiitsuKMIK12,
author = {Kiichi Niitsu and
Shusuke Kawai and
Noriyuki Miura and
Hiroki Ishikuro and
Tadahiro Kuroda},
title = {A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling
Technique for Low-Power Inter-Chip Communication in 3-D System Integration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1285--1294},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2150252},
doi = {10.1109/TVLSI.2011.2150252},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NiitsuKMIK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NourivandAS12,
author = {Afshin Nourivand and
Asim J. Al{-}Khalili and
Yvon Savaria},
title = {Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield
Losses Due to Parametric Data-Retention Failures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {29--41},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2093938},
doi = {10.1109/TVLSI.2010.2093938},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NourivandAS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Nunez-YanezNHV12,
author = {Jos{\'{e}} Luis N{\'{u}}{\~{n}}ez{-}Y{\'{a}}{\~{n}}ez and
Atukem Nabina and
Eddie Hung and
George Vafiadis},
title = {Cogeneration of Fast Motion Estimation Processors and Algorithms for
Advanced Video Coding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {437--448},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2104166},
doi = {10.1109/TVLSI.2010.2104166},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Nunez-YanezNHV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PakbazniaP12,
author = {Ehsan Pakbaznia and
Massoud Pedram},
title = {Design of a Tri-Modal Multi-Threshold {CMOS} Switch With Application
to Data Retentive Power Gating},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {380--385},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2102054},
doi = {10.1109/TVLSI.2010.2102054},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PakbazniaP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PanHL12,
author = {Songjun Pan and
Yu Hu and
Xiaowei Li},
title = {{IVF:} Characterizing the Vulnerability of Microprocessor Structures
to Intermittent Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {777--790},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2134115},
doi = {10.1109/TVLSI.2011.2134115},
timestamp = {Fri, 25 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PanHL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PantGS12,
author = {Aashish Pant and
Puneet Gupta and
Mihaela van der Schaar},
title = {AppAdapt: Opportunistic Application Adaptation in Presence of Hardware
Variation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {1986--1996},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2167360},
doi = {10.1109/TVLSI.2011.2167360},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PantGS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkLR12,
author = {Sang Phill Park and
Dongsoo Lee and
Kaushik Roy},
title = {Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {248--256},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2095435},
doi = {10.1109/TVLSI.2010.2095435},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkLR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkP12,
author = {Kangwoo Park and
In{-}Cheol Park},
title = {Low-Complexity Tone Reservation for {PAPR} Reduction in {OFDM} Communication
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1919--1923},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2164104},
doi = {10.1109/TVLSI.2011.2164104},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PaschalisVG12,
author = {Antonis M. Paschalis and
Ioannis Voyiatzis and
Dimitris Gizopoulos},
title = {Accumulator Based 3-Weight Pattern Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {357--361},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2102373},
doi = {10.1109/TVLSI.2010.2102373},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PaschalisVG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PeiLL12,
author = {Songwei Pei and
Huawei Li and
Xiaowei Li},
title = {A High-Precision On-Chip Path Delay Measurement Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1565--1577},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161353},
doi = {10.1109/TVLSI.2011.2161353},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PeiLL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PeiLL12a,
author = {Songwei Pei and
Huawei Li and
Xiaowei Li},
title = {Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition
Test Data Volume},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2157--2169},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2170227},
doi = {10.1109/TVLSI.2011.2170227},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PeiLL12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PhamPMK12,
author = {Phi{-}Hung Pham and
Jongsun Park and
Phuong Mau and
Chulwoo Kim},
title = {Design and Implementation of Backtracking Wave-Pipeline Switch to
Support Guaranteed Throughput in Network-on-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {270--283},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2096520},
doi = {10.1109/TVLSI.2010.2096520},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PhamPMK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz12,
author = {Irith Pomeranz},
title = {Gradual Diagnostic Test Generation and Observation Point Insertion
Based on the Structural Distance Between Indistinguished Fault Pairs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1026--1035},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2138729},
doi = {10.1109/TVLSI.2011.2138729},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz12a,
author = {Irith Pomeranz},
title = {Multi-Pattern {\textdollar}n{\textdollar}-Detection Stuck-At Test
Sets for Delay Defect Coverage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1156--1160},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2144627},
doi = {10.1109/TVLSI.2011.2144627},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz12b,
author = {Irith Pomeranz},
title = {Generation of Mixed Test Sets for Transition Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1895--1899},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161786},
doi = {10.1109/TVLSI.2011.2161786},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz12b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz12c,
author = {Irith Pomeranz},
title = {Non-Uniform Coverage by n -Detection Test Sets},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2138--2142},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2168432},
doi = {10.1109/TVLSI.2011.2168432},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz12c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR12,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Resolution of Diagnosis Based on Transition Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {172--176},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2091975},
doi = {10.1109/TVLSI.2010.2091975},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PulimenoGP12,
author = {Azzurra Pulimeno and
Mariagrazia Graziano and
Gianluca Piccinini},
title = {{UDSM} Trends Comparison: From Technology Roadmap to UltraSparc Niagara2},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1341--1346},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2148183},
doi = {10.1109/TVLSI.2011.2148183},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PulimenoGP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PurohitM12,
author = {Sohan Purohit and
Martin Margala},
title = {Investigating the Impact of Logic and Circuit Implementation on Full
Adder Performance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1327--1331},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2157543},
doi = {10.1109/TVLSI.2011.2157543},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PurohitM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RamanujamL12,
author = {Rohit Sunkam Ramanujam and
Bill Lin},
title = {Randomized Partially-Minimal Routing: Near-Optimal Oblivious Routing
for 3-D Mesh Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2080--2093},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2167361},
doi = {10.1109/TVLSI.2011.2167361},
timestamp = {Mon, 01 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RamanujamL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RamkumarK12,
author = {B. Ramkumar and
Harish M. Kittur},
title = {Low-Power and Area-Efficient Carry Select Adder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {371--375},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2101621},
doi = {10.1109/TVLSI.2010.2101621},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RamkumarK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReddingtonA12,
author = {Joseph Reddington and
Kubilay Atasu},
title = {Complexity of Computing Convex Subgraphs in Custom Instruction Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2337--2341},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2173221},
doi = {10.1109/TVLSI.2011.2173221},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ReddingtonA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RitheCGWDGBC12,
author = {Rahul Rithe and
Sharon Chou and
Jie Gu and
Alice Wang and
Satyendra Datla and
Gordon Gammie and
Dennis Buss and
Anantha P. Chandrakasan},
title = {The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {911--924},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2124477},
doi = {10.1109/TVLSI.2011.2124477},
timestamp = {Mon, 27 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RitheCGWDGBC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RyuKJKKJ12,
author = {Kyungho Ryu and
Jisu Kim and
Jiwan Jung and
Jung Pill Kim and
Seung{-}Hyuk Kang and
Seong{-}Ook Jung},
title = {A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention
Flip-Flop},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2044--2053},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2172644},
doi = {10.1109/TVLSI.2011.2172644},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RyuKJKKJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SahaS12,
author = {Debasri Saha and
Susmita Sur{-}Kolay},
title = {Secure Public Verification of {IP} Marks in {FPGA} Design Through
a Zero-Knowledge Protocol},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1749--1757},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2162347},
doi = {10.1109/TVLSI.2011.2162347},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SahaS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SalmaniTP12,
author = {Hassan Salmani and
Mohammad Tehranipoor and
Jim Plusquellic},
title = {A Novel Technique for Improving Hardware Trojan Detection and Reducing
Trojan Activation Time},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {112--125},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2093547},
doi = {10.1109/TVLSI.2010.2093547},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SalmaniTP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SanyalGK12,
author = {Alodeep Sanyal and
Kunal P. Ganeshpure and
Sandip Kundu},
title = {Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering
Gate Leakage Loading in Presence of Gate Delays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {424--436},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2106169},
doi = {10.1109/TVLSI.2011.2106169},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SanyalGK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SasanAHEK12,
author = {Avesta Sasan and
Kiarash Amiri and
Houman Homayoun and
Ahmed M. Eltawil and
Fadi J. Kurdahi},
title = {Variation Trained Drowsy Cache (VTD-Cache): {A} History Trained Variation
Aware Drowsy Cache for Fine Grain Voltage Scaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {630--642},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2106523},
doi = {10.1109/TVLSI.2011.2106523},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SasanAHEK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SchlottmannAH12,
author = {Craig Schlottmann and
David Abramson and
Paul E. Hasler},
title = {A MITE-Based Translinear {FPAA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {1--9},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2089705},
doi = {10.1109/TVLSI.2010.2089705},
timestamp = {Tue, 20 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SchlottmannAH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SchlottmannPH12,
author = {Craig Schlottmann and
Csaba Petre and
Paul E. Hasler},
title = {A High-Level Simulink-Based Tool for {FPAA} Configuration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {10--18},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2091687},
doi = {10.1109/TVLSI.2010.2091687},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SchlottmannPH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SebastiaoRF12,
author = {Nuno Sebasti{\~{a}}o and
Nuno Roma and
Paulo F. Flores},
title = {Integrated Hardware Architecture for Efficient Computation of the
{\textdollar}n{\textdollar}-Best Bio-Sequence Local Alignments in
Embedded Platforms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1262--1275},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2157541},
doi = {10.1109/TVLSI.2011.2157541},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SebastiaoRF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SenDC12,
author = {Shreyas Sen and
Shyam Kumar Devarakond and
Abhijit Chatterjee},
title = {Phase Distortion to Amplitude Conversion-Based Low-Cost Measurement
of {AM-AM} and {AM-PM} Effects in {RF} Power Amplifiers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1602--1614},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160376},
doi = {10.1109/TVLSI.2011.2160376},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SenDC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeokHBS12,
author = {Mingoo Seok and
Scott Hanson and
David T. Blaauw and
Dennis Sylvester},
title = {Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating
Switch for Ultra-Low {\textdollar}\{V\}{\_}\{{\textbackslash}rm dd\}{\textdollar}
Operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {605--615},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2109069},
doi = {10.1109/TVLSI.2011.2109069},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeokHBS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShabanyG12,
author = {Mahdi Shabany and
P. Glenn Gulak},
title = {A 675 Mbps, 4 {\texttimes} 4 64-QAM K-Best {MIMO} Detector in 0.13
{\(\mathrm{\mu}\)}m {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {135--147},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2090367},
doi = {10.1109/TVLSI.2010.2090367},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShabanyG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShenESM12,
author = {Chung{-}An Shen and
Ahmed M. Eltawil and
Khaled N. Salama and
Sudip Mondal},
title = {A Best-First Soft/Hard Decision Tree Searching {MIMO} Decoder for
a 4 {\texttimes} 4 64-QAM System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1537--1541},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2159821},
doi = {10.1109/TVLSI.2011.2159821},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShenESM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShenH12,
author = {Meng{-}Hung Shen and
Po{-}Chiun Huang},
title = {A Low Cost Calibrated {DAC} for High-Resolution Video Display System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1743--1747},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161679},
doi = {10.1109/TVLSI.2011.2161679},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShenH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShiTYO12,
author = {Youhua Shi and
Nozomu Togawa and
Masao Yanagisawa and
Tatsuo Ohtsuki},
title = {Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {176--181},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2120635},
doi = {10.1109/TVLSI.2011.2120635},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShiTYO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShihW12,
author = {Horng{-}Yuan Shih and
Chih{-}Wei Wang},
title = {A Highly-Integrated 3-8 GHz Ultra-Wideband {RF} Transmitter With Digital-Assisted
Carrier Leakage Calibration and Automatic Transmit Power Control},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1357--1367},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2157842},
doi = {10.1109/TVLSI.2011.2157842},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShihW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShinPSS12,
author = {Insup Shin and
Seungwhun Paik and
Dongwan Shin and
Youngsoo Shin},
title = {HLS-dv: {A} High-Level Synthesis Framework for Dual-Vdd Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {593--604},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2122310},
doi = {10.1109/TVLSI.2011.2122310},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShinPSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SiddiquaG12,
author = {Taniya Siddiqua and
Sudhanva Gurumurthi},
title = {Enhancing {NBTI} Recovery in {SRAM} Arrays Through Recovery Boosting},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {616--629},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2109973},
doi = {10.1109/TVLSI.2011.2109973},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SiddiquaG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinghKBS12,
author = {Prashant Singh and
Eric Karl and
David T. Blaauw and
Dennis Sylvester},
title = {Compact Degradation Sensors for Monitoring {NBTI} and Oxide Degradation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1645--1655},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161784},
doi = {10.1109/TVLSI.2011.2161784},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SinghKBS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SmithaV12,
author = {Kavallur Gopi Smitha and
A. Prasad Vinod},
title = {A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military
Radio Receivers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1323--1327},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2151214},
doi = {10.1109/TVLSI.2011.2151214},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SmithaV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Strauch12,
author = {Tobias Strauch},
title = {Single Cycle Access Structure for Logic Test},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {878--891},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2134875},
doi = {10.1109/TVLSI.2011.2134875},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Strauch12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunC12,
author = {Yang Sun and
Joseph R. Cavallaro},
title = {High-Throughput Soft-Output {MIMO} Detector Based on Path-Preserving
Trellis-Search Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1235--1247},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2147811},
doi = {10.1109/TVLSI.2011.2147811},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SunC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunLCW12,
author = {Zhenyu Sun and
Hai Li and
Yiran Chen and
Xiaobin Wang},
title = {Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer
Torque Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2020--2030},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2166282},
doi = {10.1109/TVLSI.2011.2166282},
timestamp = {Wed, 10 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SunLCW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunLXZZZ12,
author = {Hongbin Sun and
Chuanyin Liu and
Wei Xu and
Jizhong Zhao and
Nanning Zheng and
Tong Zhang},
title = {Using Magnetic {RAM} to Build Low-Power and Soft Error-Resilient {L1}
Cache},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {19--28},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2090914},
doi = {10.1109/TVLSI.2010.2090914},
timestamp = {Mon, 19 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SunLXZZZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TangHWZ12,
author = {Weiguo Tang and
Jie Huang and
Lei Wang and
Shengli Zhou},
title = {A Nonbinary {LDPC} Decoder Architecture With Adaptive Message Control},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2118--2122},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2165346},
doi = {10.1109/TVLSI.2011.2165346},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TangHWZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Tanzawa12,
author = {Toru Tanzawa},
title = {A Behavior Model of an On-Chip High Voltage Generator for Fast, System-Level
Simulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2351--2355},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2176762},
doi = {10.1109/TVLSI.2011.2176762},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Tanzawa12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TomasiVBDR12,
author = {Matteo Tomasi and
Mauricio Vanegas and
Francisco Barranco and
Javier D{\'{\i}}az and
Eduardo Ros},
title = {Real-Time Architecture for a Robust Multi-Scale Stereo Engine on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2208--2219},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2172007},
doi = {10.1109/TVLSI.2011.2172007},
timestamp = {Tue, 10 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TomasiVBDR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaiL12,
author = {Kun{-}Hung Tsai and
Shen{-}Iuan Liu},
title = {A 104-GHz Phase-Locked Loop Using a {VCO} at Second Pole Frequency},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {80--88},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2088144},
doi = {10.1109/TVLSI.2010.2088144},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaiL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaoC12,
author = {Yu{-}Chi Tsao and
Ken Choi},
title = {Area-Efficient Parallel {FIR} Digital Filter Structures for Symmetric
Convolutions Based on Fast {FIR} Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {2},
pages = {366--371},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2095892},
doi = {10.1109/TVLSI.2010.2095892},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaoC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TseTL12,
author = {Anson H. T. Tse and
David B. Thomas and
Wayne Luk},
title = {Design Exploration of Quadrature Methods in Option Pricing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {818--826},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2128354},
doi = {10.1109/TVLSI.2011.2128354},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TseTL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TungLLH12,
author = {Hui{-}Hsiang Tung and
Rung{-}Bin Lin and
Mei{-}Chen Li and
Tsung{-}Han Heish},
title = {Standard Cell Like Via-Configurable Logic Blocks for Structured {ASIC}
in an Industrial Design Flow},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2184--2197},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2170712},
doi = {10.1109/TVLSI.2011.2170712},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TungLLH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TuunaNIT12,
author = {Sampo Tuuna and
Ethiopia Nigussie and
Jouni Isoaho and
Hannu Tenhunen},
title = {Modeling of Energy Dissipation in {RLC} Current-Mode Signaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1146--1151},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2140345},
doi = {10.1109/TVLSI.2011.2140345},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TuunaNIT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ValeroSLPLD12,
author = {Alejandro Valero and
Julio Sahuquillo and
Vicente Lorente and
Salvador Petit and
Pedro L{\'{o}}pez and
Jos{\'{e}} Duato},
title = {Impact on Performance and Energy of the Retention Time and Processor
Frequency in {L1} Macrocell-Based Data Caches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1108--1117},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2142202},
doi = {10.1109/TVLSI.2011.2142202},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ValeroSLPLD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangHZ12,
author = {Shuai Wang and
Jie S. Hu and
Sotirios G. Ziavras},
title = {Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {643--654},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2111469},
doi = {10.1109/TVLSI.2011.2111469},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangHZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangKJ12,
author = {Zhen Wang and
Mark G. Karpovsky and
Ajay Joshi},
title = {Secure Multipliers Resilient to Strong Fault-Injection Attacks Using
Multilinear Arithmetic Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1036--1048},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2147340},
doi = {10.1109/TVLSI.2011.2147340},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangKJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangKJ12a,
author = {Zhen Wang and
Mark G. Karpovsky and
Ajay Joshi},
title = {Nonlinear Multi-Error Correction Codes for Reliable {MLC} nand Flash
Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1221--1234},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2157183},
doi = {10.1109/TVLSI.2011.2157183},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangKJ12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangM12,
author = {Weixun Wang and
Prabhat Mishra},
title = {System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage
Scaling and Cache Reconfiguration in Multitasking Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {902--910},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2116814},
doi = {10.1109/TVLSI.2011.2116814},
timestamp = {Mon, 18 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangM12a,
author = {Mingyu Wang and
Hao Min},
title = {Applying Effective Dynamic Frequency Scaling Method in Contactless
Smart Card},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1828--1834},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2164560},
doi = {10.1109/TVLSI.2011.2164560},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangM12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangTGTW12,
author = {Xiaoxiao Wang and
Mohammad Tehranipoor and
Saji George and
Dat Tran and
LeRoy Winemberg},
title = {Design and Analysis of a Delay Sensor Applicable to Process/Environmental
Variations and Aging Measurements},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1405--1418},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2158124},
doi = {10.1109/TVLSI.2011.2158124},
timestamp = {Mon, 26 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangTGTW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WeiP12,
author = {Sheng Wei and
Miodrag Potkonjak},
title = {Scalable Hardware Trojan Diagnosis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1049--1057},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2147341},
doi = {10.1109/TVLSI.2011.2147341},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WeiP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WeiSCJ12,
author = {Cheng{-}Wen Wei and
Sheng{-}Jie Su and
Tian{-}Sheuan Chang and
Shyh{-}Jye Jou},
title = {Sub {\(\mathrm{\mu}\)}W Noise Reduction for {CIC} Hearing Aids},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {937--947},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2125805},
doi = {10.1109/TVLSI.2011.2125805},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WeiSCJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WeyW12,
author = {I{-}Chyn Wey and
Chun{-}Chien Wang},
title = {Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the
Dual-Group Minor Input Correction Vector to Lower Input Correction
Vector Compensation Error},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1923--1928},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2165228},
doi = {10.1109/TVLSI.2011.2165228},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WeyW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WimerK12,
author = {Shmuel Wimer and
Israel Koren},
title = {The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive
Gating},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1772--1780},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2162861},
doi = {10.1109/TVLSI.2011.2162861},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WimerK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WongWNH12,
author = {Ming Ming Wong and
M. L. Dennis Wong and
Asoke K. Nandi and
Ismat Hijazin},
title = {Construction of Optimum Composite Field Architecture for Compact High-Throughput
{AES} S-Boxes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1151--1155},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2141693},
doi = {10.1109/TVLSI.2011.2141693},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WongWNH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WootersCQWMCSB12,
author = {Stuart N. Wooters and
Adam C. Cabe and
Zhenyu Qi and
Jiajing Wang and
Randy W. Mann and
Benton H. Calhoun and
Mircea R. Stan and
Travis N. Blalock},
title = {Tracking On-Chip Age Using Distributed, Embedded Sensors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {1974--1985},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2168246},
doi = {10.1109/TVLSI.2011.2168246},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WootersCQWMCSB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuSL12,
author = {Wei Wu and
Dinesh Somasekhar and
Shih{-}Lien Lu},
title = {Direct Compare of Information Coded With Error-Correcting Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2147--2151},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2169094},
doi = {10.1109/TVLSI.2011.2169094},
timestamp = {Fri, 05 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuSL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuZNNLGRNX12,
author = {Xiaoxia Wu and
Wei Zhao and
Mark Nakamoto and
Chandra Nimmagadda and
Durodami Lisk and
Sam Gu and
Riko Radojcic and
Matt Nowak and
Yuan Xie},
title = {Electrical Characterization for Intertier Connections and Timing Analysis
for 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {186--191},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2090049},
doi = {10.1109/TVLSI.2010.2090049},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuZNNLGRNX12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XueDYWYY12,
author = {Jiying Xue and
Yangdong Deng and
Zuochang Ye and
Hongrui Wang and
Liu Yang and
Zhiping Yu},
title = {A Framework for Layout-Dependent {STI} Stress Analysis and Stress-Aware
Circuit Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {3},
pages = {498--511},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2102374},
doi = {10.1109/TVLSI.2010.2102374},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XueDYWYY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YanTZCS12,
author = {Boyuan Yan and
Sheldon X.{-}D. Tan and
Lingfei Zhou and
Jie Chen and
Ruijing Shen},
title = {Decentralized and Passive Model Order Reduction of Linear Networks
With Massive Ports},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {5},
pages = {865--877},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2126612},
doi = {10.1109/TVLSI.2011.2126612},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YanTZCS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangCCHL12,
author = {Hao{-}Yu Yang and
Chi{-}Min Chang and
Mango Chia{-}Tso Chao and
Rei{-}Fu Huang and
Shih{-}Chin Lin},
title = {Testing Methodology of Embedded DRAMs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1715--1728},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161785},
doi = {10.1109/TVLSI.2011.2161785},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangCCHL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangEC12,
author = {Chengen Yang and
Yunus Emre and
Chaitali Chakrabarti},
title = {Product Code Schemes for Error Correction in {MLC} {NAND} Flash Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2302--2314},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2174389},
doi = {10.1109/TVLSI.2011.2174389},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangEC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangHL12,
author = {Shun{-}Hsun Yang and
Yu{-}Jen Huang and
Jin{-}Fu Li},
title = {A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1909--1913},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2163205},
doi = {10.1109/TVLSI.2011.2163205},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YangHL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangVN12,
author = {Yu{-}Shen Yang and
Andreas G. Veneris and
Nicola Nicolici},
title = {Automating Data Analysis and Acquisition Setup in a Silicon Debug
Environment},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1118--1131},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2142407},
doi = {10.1109/TVLSI.2011.2142407},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangVN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YaoSHP12,
author = {Wei Yao and
Yiyu Shi and
Lei He and
Sudhakar Pamarti},
title = {Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude
Noise in High-Speed Differential Link},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {89--97},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2090544},
doi = {10.1109/TVLSI.2010.2090544},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YaoSHP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YehCW12,
author = {Chingwei Yeh and
Yuan{-}Chang Chen and
Jinn{-}Shyan Wang},
title = {Towards Process Variation-Aware Power Gating},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {1929--1937},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2169435},
doi = {10.1109/TVLSI.2011.2169435},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YehCW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YehW12,
author = {Tung{-}Hua Yeh and
Sying{-}Jyan Wang},
title = {Power-Aware High-Level Synthesis With Clock Skew Management},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {167--171},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2091292},
doi = {10.1109/TVLSI.2010.2091292},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YehW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YiYISKF12,
author = {Hyunbean Yi and
Tomokazu Yoneda and
Michiko Inoue and
Yasuo Sato and
Seiji Kajihara and
Hideo Fujiwara},
title = {A Failure Prediction Strategy for Transistor Aging},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {1951--1959},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2165304},
doi = {10.1109/TVLSI.2011.2165304},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YiYISKF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YiannacourasSR12,
author = {Peter Yiannacouras and
J. Gregory Steffan and
Jonathan Rose},
title = {Portable, Flexible, and Scalable Soft Vector Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1429--1442},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160463},
doi = {10.1109/TVLSI.2011.2160463},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YiannacourasSR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YinC12,
author = {Jee Khoi Yin and
Pak Kwong Chan},
title = {Jitter Analysis of Polyphase Filter-Based Multiphase Clock in Frequency
Multiplier},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1373--1382},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2159633},
doi = {10.1109/TVLSI.2011.2159633},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YinC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuA12,
author = {Qiaoyan Yu and
Paul Ampadu},
title = {Dual-Layer Adaptive Error Control for Network-on-Chip Links},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1304--1317},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2156436},
doi = {10.1109/TVLSI.2011.2156436},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YuA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuLX12,
author = {Haile Yu and
Philip Heng Wai Leong and
Qiang Xu},
title = {An {FPGA} Chip Identification Generator Using Configurable Ring Oscillators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {12},
pages = {2198--2207},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2173770},
doi = {10.1109/TVLSI.2011.2173770},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YuLX12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuSLLW12,
author = {Chi Wai Yu and
Alastair M. Smith and
Wayne Luk and
Philip Heng Wai Leong and
Steven J. E. Wilton},
title = {Optimizing Floating Point Units in Hybrid FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1295--1303},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2153883},
doi = {10.1109/TVLSI.2011.2153883},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YuSLLW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuYL12,
author = {Chien{-}Ying Yu and
Jui{-}Yuan Yu and
Chen{-}Yi Lee},
title = {A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference
Modeling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {9},
pages = {1615--1620},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160301},
doi = {10.1109/TVLSI.2011.2160301},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YuYL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuZS12,
author = {Hang Yu and
Lin Zhong and
Ashutosh Sabharwal},
title = {Power Management of {MIMO} Network Interfaces on Mobile Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1175--1186},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2157369},
doi = {10.1109/TVLSI.2011.2157369},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YuZS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangCL12,
author = {Xinmiao Zhang and
Fang Cai and
Shu Lin},
title = {Low-Complexity Reliability-Based Message-Passing Decoder Architectures
for Non-Binary {LDPC} Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {1938--1950},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2164951},
doi = {10.1109/TVLSI.2011.2164951},
timestamp = {Wed, 16 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangCL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangIFTS12,
author = {Xin Zhang and
Koichi Ishida and
Hiroshi Fuketa and
Makoto Takamiya and
Takayasu Sakurai},
title = {On-Chip Measurement System for Within-Die Delay Variation of Individual
Standard Cells in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1876--1880},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2162257},
doi = {10.1109/TVLSI.2011.2162257},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangIFTS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangWGC12,
author = {Zhaobo Zhang and
Zhanglei Wang and
Xinli Gu and
Krishnendu Chakrabarty},
title = {Physical-Defect Modeling and Optimization for Fault-Insertion Test},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {723--736},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2114681},
doi = {10.1109/TVLSI.2011.2114681},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangWGC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangWM12,
author = {Qi Zhang and
Roger F. Woods and
Alan Marshall},
title = {An On-Demand Queue Management Architecture for a Programmable Traffic
Manager},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1849--1862},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2162084},
doi = {10.1109/TVLSI.2011.2162084},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangWM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangWZZ12,
author = {Xinmiao Zhang and
Yingquan Wu and
Jiangli Zhu and
Yu Zheng},
title = {Novel Interpolation and Polynomial Selection for Low-Complexity Chase
Soft-Decision Reed-Solomon Decoding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1318--1322},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2150254},
doi = {10.1109/TVLSI.2011.2150254},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangWZZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaoCSP12,
author = {Yang Zhao and
Krishnendu Chakrabarty and
Ryan Sturmer and
Vamsee K. Pamula},
title = {Optimization Techniques for the Synchronization of Concurrent Fluidic
Operations in Pin-Constrained Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1132--1145},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2145397},
doi = {10.1109/TVLSI.2011.2145397},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoCSP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhengCL12,
author = {Yanqi Zheng and
Hua Chen and
Ka Nang Leung},
title = {A Fast-Response Pseudo-PWM Buck Converter With PLL-Based Hysteresis
Control},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {7},
pages = {1167--1174},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2156437},
doi = {10.1109/TVLSI.2011.2156437},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhengCL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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