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@article{DBLP:journals/integration/SiddanathGJGK24,
  author       = {Ravi S. Siddanath and
                  Mohit Gupta and
                  Chaitanya Joshi and
                  Manish Goswami and
                  Kavindra Kandpal},
  title        = {A 10T {SRAM} architecture with 40 {\%} enhanced throughput for {IMC}
                  applications benchmarked with {CIFAR-10} dataset},
  journal      = {Integr.},
  volume       = {98},
  pages        = {102225},
  year         = {2024},
  url          = {https://doi.org/10.1016/j.vlsi.2024.102225},
  doi          = {10.1016/J.VLSI.2024.102225},
  timestamp    = {Fri, 19 Jul 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/SiddanathGJGK24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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