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export results for "A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS."

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@inproceedings{DBLP:conf/vlsic/LeeKGKUCF14,
  author       = {Chang{-}Hyeon Lee and
                  Lindel Kabalican and
                  Yan Ge and
                  Hendra Kwantono and
                  Greg Unruh and
                  Mark Chambers and
                  Ichiro Fujimori},
  title        = {A 2.7GHz to 7GHz fractional-N {LCPLL} utilizing multimetal layer SoC
                  technology in 28nm {CMOS}},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
                  Honolulu, HI, USA, June 10-13, 2014},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/VLSIC.2014.6858390},
  doi          = {10.1109/VLSIC.2014.6858390},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/LeeKGKUCF14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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