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export results for "An interconnect optimized floorplanning of a scalar product macrocell."

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@inproceedings{DBLP:conf/iscas/GuCY02,
  author       = {Jiangmin Gu and
                  Chip{-}Hong Chang and
                  Kiat Seng Yeo},
  title        = {An interconnect optimized floorplanning of a scalar product macrocell},
  booktitle    = {Proceedings of the 2002 International Symposium on Circuits and Systems,
                  {ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
  pages        = {465--468},
  publisher    = {{IEEE}},
  year         = {2002},
  url          = {https://doi.org/10.1109/ISCAS.2002.1009878},
  doi          = {10.1109/ISCAS.2002.1009878},
  timestamp    = {Sun, 25 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/GuCY02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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