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export results for "Andrew R. Pleszkun"
@inproceedings{DBLP:conf/mss/AikenGPW03, author = {Stephen Aiken and Dirk Grunwald and Andrew R. Pleszkun and Jesse Willek}, title = {A Performance Analysis of the iSCSI Protocol}, booktitle = {20th IEEE/11th {NASA} Goddard Conference on Mass Storage Systems and Technologies, {MSS} 2003, San Diego, California, USA, April 7-10, 2003}, pages = {123--134}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.org/10.1109/MASS.2003.1194849}, doi = {10.1109/MASS.2003.1194849}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/mss/AikenGPW03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/GrunwaldKMP98, author = {Dirk Grunwald and Artur Klauser and Srilatha Manne and Andrew R. Pleszkun}, editor = {Mateo Valero and Gurindar S. Sohi and Doug DeGroot}, title = {Confidence Estimation for Speculation Control}, booktitle = {Proceedings of the 25th Annual International Symposium on Computer Architecture, {ISCA} 1998, Barcelona, Spain, June 27 - July 1, 1998}, pages = {122--131}, publisher = {{IEEE} Computer Society}, year = {1998}, url = {https://doi.org/10.1109/ISCA.1998.694768}, doi = {10.1109/ISCA.1998.694768}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/GrunwaldKMP98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/SmithP98, author = {James E. Smith and Andrew R. Pleszkun}, editor = {Gurindar S. Sohi}, title = {Implementation of Precise Interupts in Pipelined Processors}, booktitle = {25 Years of the International Symposia on Computer Architecture (Selected Papers)}, pages = {291--299}, publisher = {{ACM}}, year = {1998}, url = {https://doi.org/10.1145/285930.285988}, doi = {10.1145/285930.285988}, timestamp = {Tue, 29 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isca/SmithP98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ijpp/TysonFMP97, author = {Gary S. Tyson and Matthew K. Farrens and John Matthews and Andrew R. Pleszkun}, title = {Managing data caches using selective cache line replacement}, journal = {Int. J. Parallel Program.}, volume = {25}, number = {3}, pages = {213--242}, year = {1997}, url = {https://doi.org/10.1007/BF02700036}, doi = {10.1007/BF02700036}, timestamp = {Wed, 01 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ijpp/TysonFMP97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/isca/1997, editor = {Andrew R. Pleszkun and Trevor N. Mudge}, title = {Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997}, publisher = {{ACM}}, year = {1997}, url = {https://doi.org/10.1145/264107}, doi = {10.1145/264107}, isbn = {0-89791-901-7}, timestamp = {Fri, 09 Jul 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isca/1997.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/TysonFMP95, author = {Gary S. Tyson and Matthew K. Farrens and John Matthews and Andrew R. Pleszkun}, editor = {Trevor N. Mudge and Kemal Ebcioglu}, title = {A modified approach to data cache management}, booktitle = {Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29 - December 1, 1995}, pages = {93--103}, publisher = {{ACM} / {IEEE} Computer Society}, year = {1995}, url = {https://doi.org/10.1109/MICRO.1995.476816}, doi = {10.1109/MICRO.1995.476816}, timestamp = {Tue, 31 May 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/TysonFMP95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/FarrensTP94, author = {Matthew K. Farrens and Gary S. Tyson and Andrew R. Pleszkun}, editor = {David A. Patterson}, title = {A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors}, booktitle = {Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, IL, USA, April 1994}, pages = {338--347}, publisher = {{IEEE} Computer Society}, year = {1994}, url = {https://doi.org/10.1109/ISCA.1994.288137}, doi = {10.1109/ISCA.1994.288137}, timestamp = {Thu, 13 Apr 2023 19:55:42 +0200}, biburl = {https://dblp.org/rec/conf/isca/FarrensTP94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/Pleszkun94, author = {Andrew R. Pleszkun}, editor = {Hans Mulder and Matthew K. Farrens}, title = {Techniques for compressing program address traces}, booktitle = {Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994}, pages = {32--39}, publisher = {{ACM} / {IEEE} Computer Society}, year = {1994}, url = {https://doi.org/10.1109/MICRO.1994.717407}, doi = {10.1109/MICRO.1994.717407}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/micro/Pleszkun94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/TysonFP92, author = {Gary S. Tyson and Matthew K. Farrens and Andrew R. Pleszkun}, editor = {Wen{-}mei W. Hwu}, title = {{MISC:} a Multiple Instruction Stream Computer}, booktitle = {Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon, USA, November 1992}, pages = {193--196}, publisher = {{ACM} / {IEEE} Computer Society}, year = {1992}, url = {https://doi.org/10.1109/MICRO.1992.697016}, doi = {10.1109/MICRO.1992.697016}, timestamp = {Tue, 31 May 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/TysonFP92.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/computer/FarrensP91, author = {Matthew K. Farrens and Andrew R. Pleszkun}, title = {Implementation of the {PIPE} Processor}, journal = {Computer}, volume = {24}, number = {1}, pages = {65--69}, year = {1991}, url = {https://doi.org/10.1109/2.67195}, doi = {10.1109/2.67195}, timestamp = {Wed, 12 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/computer/FarrensP91.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/FarrensP91a, author = {Matthew K. Farrens and Andrew R. Pleszkun}, editor = {Zvonko G. Vranesic}, title = {Strategies for Achieving Improved Processor Throughput}, booktitle = {Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, Canada, May, 27-30 1991}, pages = {362--369}, publisher = {{ACM}}, year = {1991}, url = {https://doi.org/10.1145/115952.115988}, doi = {10.1145/115952.115988}, timestamp = {Fri, 09 Jul 2021 15:51:20 +0200}, biburl = {https://dblp.org/rec/conf/isca/FarrensP91a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/FarrensP90, author = {Matthew K. Farrens and Andrew R. Pleszkun}, editor = {Christos A. Papachristou and Vicki H. Allan}, title = {An evaluation of functional unit lengths for single-chip processors}, booktitle = {Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990}, pages = {209--215}, publisher = {{ACM/IEEE}}, year = {1990}, url = {https://dl.acm.org/citation.cfm?id=255278}, timestamp = {Wed, 13 Feb 2019 11:42:26 +0100}, biburl = {https://dblp.org/rec/conf/micro/FarrensP90.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/FarrensP89, author = {Matthew K. Farrens and Andrew R. Pleszkun}, editor = {Jean{-}Claude Syre}, title = {Improving Performance of Small On-Chip Instruction Caches}, booktitle = {Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989}, pages = {234--241}, publisher = {{ACM}}, year = {1989}, url = {https://doi.org/10.1145/74925.74952}, doi = {10.1145/74925.74952}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/FarrensP89.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/SmithP88, author = {James E. Smith and Andrew R. Pleszkun}, title = {Implementing Precise Interrupts in Pipelined Processors}, journal = {{IEEE} Trans. Computers}, volume = {37}, number = {5}, pages = {562--573}, year = {1988}, url = {https://doi.org/10.1109/12.4607}, doi = {10.1109/12.4607}, timestamp = {Wed, 14 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tc/SmithP88.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/PleszkunS88, author = {Andrew R. Pleszkun and Gurindar S. Sohi}, editor = {Howard Jay Siegel}, title = {The Performance Potential of Multiple Functional Unit Processors}, booktitle = {Proceedings of the 15th Annual International Symposium on Computer Architecture, Honolulu, Hawaii, USA, May-June 1988}, pages = {37--44}, publisher = {{IEEE} Computer Society}, year = {1988}, url = {https://doi.org/10.1109/ISCA.1988.5208}, doi = {10.1109/ISCA.1988.5208}, timestamp = {Thu, 08 Jul 2021 16:04:01 +0200}, biburl = {https://dblp.org/rec/conf/isca/PleszkunS88.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/PleszkunS88, author = {Andrew R. Pleszkun and Gurindar S. Sohi}, editor = {Yale N. Patt}, title = {Multiple instruction issue and single-chip processors}, booktitle = {Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988}, pages = {64--66}, publisher = {{ACM/IEEE}}, year = {1988}, url = {https://dl.acm.org/citation.cfm?id=62537}, timestamp = {Wed, 13 Feb 2019 11:42:26 +0100}, biburl = {https://dblp.org/rec/conf/micro/PleszkunS88.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/computer/PleszkunT87, author = {Andrew R. Pleszkun and Matthew Thazhuthaveetil}, title = {The Architecture of Lisp Machines}, journal = {Computer}, volume = {20}, number = {3}, pages = {35--44}, year = {1987}, url = {https://doi.org/10.1109/MC.1987.1663507}, doi = {10.1109/MC.1987.1663507}, timestamp = {Wed, 12 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/computer/PleszkunT87.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ipl/ThazhuthaveetilP87, author = {Matthew Thazhuthaveetil and Andrew R. Pleszkun}, title = {On the Structural Locality of Reference in {LISP} List Access Streams}, journal = {Inf. Process. Lett.}, volume = {26}, number = {2}, pages = {105--110}, year = {1987}, url = {https://doi.org/10.1016/0020-0190(87)90046-9}, doi = {10.1016/0020-0190(87)90046-9}, timestamp = {Fri, 26 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ipl/ThazhuthaveetilP87.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/PleszkunGHJBWS87, author = {Andrew R. Pleszkun and James R. Goodman and Wei{-}Chung Hsu and R. T. Joersz and George E. Bier and Philip J. Woest and P. B. Schechter}, editor = {Daniel C. St. Clair}, title = {{WISQ:} {A} Restartable Architecture Using Queues}, booktitle = {Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, PA, USA, June 1987}, pages = {290--299}, year = {1987}, url = {https://doi.org/10.1145/30350.30383}, doi = {10.1145/30350.30383}, timestamp = {Fri, 09 Jul 2021 15:51:20 +0200}, biburl = {https://dblp.org/rec/conf/isca/PleszkunGHJBWS87.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/compcon/PleszkunSKD86, author = {Andrew R. Pleszkun and Gurindar S. Sohi and Bassam Z. Kahhaleh and Edward S. Davidson}, title = {Features of the Structured Memory Access {(SMA)} Architecture}, booktitle = {Spring COMPCON'86, Digest of Papers, Thirty-First {IEEE} Computer Society International Conference, San Francisco, California, USA, March 3-6, 1986}, pages = {259--265}, publisher = {{IEEE} Computer Society}, year = {1986}, timestamp = {Wed, 28 Jun 2006 09:47:20 +0200}, biburl = {https://dblp.org/rec/conf/compcon/PleszkunSKD86.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/PleszkunT86, author = {Andrew R. Pleszkun and Matthew Thazhuthaveetil}, editor = {Hideo Aiso}, title = {An Architecture for Efficient Lisp List Access}, booktitle = {Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986}, pages = {191--198}, publisher = {{IEEE} Computer Society}, year = {1986}, url = {https://doi.org/10.1145/17356.17378}, doi = {10.1145/17356.17378}, timestamp = {Mon, 12 Jul 2021 17:55:24 +0200}, biburl = {https://dblp.org/rec/conf/isca/PleszkunT86.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/BierP85, author = {George E. Bier and Andrew R. Pleszkun}, editor = {Hillel Ofek and Lawrence A. O'Neill}, title = {An algorithm for design rule checking on a multiprocessor}, booktitle = {Proceedings of the 22nd {ACM/IEEE} conference on Design automation, {DAC} 1985, Las Vegas, Nevada, USA, 1985}, pages = {299--304}, publisher = {{ACM}}, year = {1985}, url = {https://doi.org/10.1145/317825.317874}, doi = {10.1145/317825.317874}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/BierP85.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/GoodmanHLPSY85, author = {James R. Goodman and Jian{-}tu Hsieh and Koujuch Liou and Andrew R. Pleszkun and P. B. Schechter and Honesty C. Young}, editor = {Thomas F. Gannon and Tilak Agerwala and Charles V. Freiman}, title = {{PIPE:} {A} {VLSI} Decoupled Architecture}, booktitle = {Proceedings of the 12th Annual Symposium on Computer Architecture, Boston, MA, USA, June 1985}, pages = {20--27}, publisher = {{IEEE} Computer Society}, year = {1985}, url = {https://doi.org/10.1145/327070.327117}, doi = {10.1145/327070.327117}, timestamp = {Tue, 31 Aug 2021 17:59:20 +0200}, biburl = {https://dblp.org/rec/conf/isca/GoodmanHLPSY85.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/SmithP85, author = {James E. Smith and Andrew R. Pleszkun}, editor = {Thomas F. Gannon and Tilak Agerwala and Charles V. Freiman}, title = {Implementation of Precise Interrupts in Pipelined Processors}, booktitle = {Proceedings of the 12th Annual Symposium on Computer Architecture, Boston, MA, USA, June 1985}, pages = {36--44}, publisher = {{IEEE} Computer Society}, year = {1985}, url = {https://doi.org/10.1145/327070.327125}, doi = {10.1145/327070.327125}, timestamp = {Tue, 29 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isca/SmithP85.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/icpp/PleszkunD83, author = {Andrew R. Pleszkun and Edward S. Davidson}, title = {Structured Memory Access Architecture}, booktitle = {International Conference on Parallel Processing, ICPP'83, Columbus, Ohio, USA, August 1983}, pages = {461--471}, publisher = {{IEEE} Computer Society}, year = {1983}, timestamp = {Wed, 04 Dec 2002 14:34:54 +0100}, biburl = {https://dblp.org/rec/conf/icpp/PleszkunD83.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@phdthesis{DBLP:phd/us/Pleszkun82, author = {Andrew R. Pleszkun}, title = {A Structured Memory Access Architecture}, school = {University of Illinois Urbana-Champaign, {USA}}, year = {1982}, url = {https://hdl.handle.net/2142/69242}, timestamp = {Thu, 14 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/phd/us/Pleszkun82.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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