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@inproceedings{DBLP:conf/vlsi/Abdel-KhalekB10,
author = {Rawan Abdel{-}Khalek and
Valeria Bertacco},
title = {SoCGuard: {A} runtime verification solution for the functional correctness
of SoCs},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {49--54},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642622},
doi = {10.1109/VLSISOC.2010.5642622},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Abdel-KhalekB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AbdelsalamWADI10,
author = {Mohamed Abdelsalam and
M. Wahba and
M. Abdelmoneum and
David Duarte and
Yehia Ismail},
title = {Supporting circuitry for a fully integrated micro electro mechanical
{(MEMS)} oscillator in 45 nm {CMOS} technology},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {259--263},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642670},
doi = {10.1109/VLSISOC.2010.5642670},
timestamp = {Fri, 11 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AbdelsalamWADI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AghamirzaieRZN10,
author = {Delasa Aghamirzaie and
Seyyed Ahmad Razavi and
Morteza Saheb Zamani and
Mahdi Nabiyouni},
title = {Reduction of process variation effect on FPGAs using multiple configurations},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {85--90},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642616},
doi = {10.1109/VLSISOC.2010.5642616},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AghamirzaieRZN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AkinCEKH10,
author = {Abdulkadir Akin and
Mert Cetin and
Burak Erbagci and
Ozgur Karakaya and
Ilker Hamzaoglu},
title = {An adaptive bilateral motion estimation algorithm and its hardware
architecture},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {207--212},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642661},
doi = {10.1109/VLSISOC.2010.5642661},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AkinCEKH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AlonsoFCSD10,
author = {Oscar Alonso and
Lluis Freixas and
Joan Canals and
Ekawahyu Susilo and
{\'{A}}ngel Dieguez},
title = {Control electronics integration toward endoscopic capsule robot performing
legged locomotion and illumination},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {241--246},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642667},
doi = {10.1109/VLSISOC.2010.5642667},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AlonsoFCSD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AltermannCB10,
author = {Jo{\~{a}}o S. Altermann and
Eduardo A. C. da Costa and
Sergio Bampi},
title = {Fast forward and inverse transforms for the {H.264/AVC} standard using
hierarchical adder compressors},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {310--315},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642679},
doi = {10.1109/VLSISOC.2010.5642679},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AltermannCB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AnuarTS10,
author = {Nazrul Anuar and
Yasuhiro Takahashi and
Toshikazu Sekine},
title = {4{\texttimes}4-bit array two phase clocked adiabatic static {CMOS}
logic multiplier with new {XOR}},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {364--368},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642688},
doi = {10.1109/VLSISOC.2010.5642688},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/AnuarTS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BaloukasPPSM10,
author = {Christos Baloukas and
Lazaros Papadopoulos and
Robert Pyka and
Dimitrios Soudris and
Peter Marwedel},
title = {An automatic framework for dynamic data structures optimization in
{C}},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {155--160},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642605},
doi = {10.1109/VLSISOC.2010.5642605},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BaloukasPPSM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BattezzatiSVD10,
author = {Niccol{\`{o}} Battezzati and
Luca Sterpone and
Massimo Violante and
Filomena Decuzzi},
title = {A new software tool for static analysis of {SET} sensitiveness in
Flash-based FPGAs},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {79--84},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642619},
doi = {10.1109/VLSISOC.2010.5642619},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BattezzatiSVD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BenkeserBH10,
author = {Christian Benkeser and
Andreas Bubenhofer and
Qiuting Huang},
title = {A 1mm\({}^{\mbox{2}}\) 1.3mW {GSM/EDGE} digital baseband receiver
{ASIC} in 0.13 {\(\mathrm{\mu}\)}m {CMOS}},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {183--188},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642592},
doi = {10.1109/VLSISOC.2010.5642592},
timestamp = {Thu, 09 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BenkeserBH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Berg10,
author = {Yngvar Berg},
title = {Ultra low voltage and high speed {CMOS} flip-flop using floating-gates},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {111--114},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642613},
doi = {10.1109/VLSISOC.2010.5642613},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Berg10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Berg10a,
author = {Yngvar Berg},
title = {Static ultra-low-voltage high-speed {CMOS} logic and latches},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {115--118},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642610},
doi = {10.1109/VLSISOC.2010.5642610},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Berg10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Berg10b,
author = {Yngvar Berg},
title = {Novel ultra low-voltage and high speed domino {CMOS} logic},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {225--228},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642664},
doi = {10.1109/VLSISOC.2010.5642664},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Berg10b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BermanGK10,
author = {Amit Berman and
Ran Ginosar and
Idit Keidar},
title = {Order is power: Selective Packet Interleaving for energy efficient
Networks-on-Chip},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {37--42},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642624},
doi = {10.1109/VLSISOC.2010.5642624},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BermanGK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BernasconiC10,
author = {Anna Bernasconi and
Valentina Ciriani},
title = {Logic synthesis and testability of D-reducible functions},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {280--285},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642674},
doi = {10.1109/VLSISOC.2010.5642674},
timestamp = {Sat, 23 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BernasconiC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BombieriFG10,
author = {Nicola Bombieri and
Franco Fummi and
Valerio Guarnieri},
title = {Model checking on {TLM-2.0} IPs through automatic TLM-to-RTL synthesis},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {61--66},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642620},
doi = {10.1109/VLSISOC.2010.5642620},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BombieriFG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BonannoBMM10,
author = {Alberto Bonanno and
Alberto Bocca and
Alberto Macii and
Enrico Macii},
title = {Power-aware partitioning of data converters},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {358--363},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642687},
doi = {10.1109/VLSISOC.2010.5642687},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BonannoBMM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BotelhoKLCC10,
author = {Mariza Botelho and
Fernanda Lima Kastensmidt and
Marcelo Lubaszewski and
{\'{E}}rika F. Cota and
Luigi Carro},
title = {A broad strategy to detect crosstalk faults in network-on-chip interconnects},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {298--303},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642677},
doi = {10.1109/VLSISOC.2010.5642677},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BotelhoKLCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CaffarenaC10,
author = {Gabriel Caffarena and
Carlos Carreras},
title = {Architectural synthesis of {DSP} circuits under simultaneous error
and time constraints},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {322--327},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642681},
doi = {10.1109/VLSISOC.2010.5642681},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CaffarenaC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CaffarenaCLH10,
author = {Gabriel Caffarena and
Carlos Carreras and
Juan A. L{\'{o}}pez and
Angel Fernandez Herrero},
title = {Fast fixed-point optimization of {DSP} algorithms},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {195--200},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642659},
doi = {10.1109/VLSISOC.2010.5642659},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CaffarenaCLH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CarduFGSCPSC10,
author = {Roberto Cardu and
Eleonora Franchi and
Roberto Guerrieri and
Mauro Scandiuzzo and
Salvatore Cani and
Luca Perugini and
Simone Spolzino and
Roberto Canegallo},
title = {Characterization of chip-to-chip wireless interconnections based on
capacitive coupling},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {375--380},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642690},
doi = {10.1109/VLSISOC.2010.5642690},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CarduFGSCPSC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ClaesenVLMNWRF10,
author = {Luc Claesen and
Peter Vandoren and
Tom Van Laerhoven and
Andy Motten and
Domien Nowicki and
Tom De Weyer and
Frank Van Reeth and
Eddy Flerackers},
title = {Smart camera SoC system for interactive real-time real-brush based
digital painting systems},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {247--252},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642668},
doi = {10.1109/VLSISOC.2010.5642668},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ClaesenVLMNWRF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DoBDYC10,
author = {Aaron V. T. Do and
Chirn Chye Boon and
Manh Anh Do and
Kiat Seng Yeo and
Alper Cabuk},
title = {A 1-V {CMOS} ultralow-power receiver front end for the {IEEE} 802.15.4
standard using tuned passive mixer output pole},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {381--386},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642691},
doi = {10.1109/VLSISOC.2010.5642691},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DoBDYC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ElissatiYRF10,
author = {Oussama Elissati and
Eslam Yahya and
S{\'{e}}bastien Rieubon and
Laurent Fesquet},
title = {A high-speed high-resolution low-phase noise oscillator using self-timed
rings},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {173--178},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642600},
doi = {10.1109/VLSISOC.2010.5642600},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ElissatiYRF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FranciscoPS10,
author = {Bruno Francisco and
Frederico Pratas and
Leonel Sousa},
title = {Unifying stream based and reconfigurable computing to design application
accelerators},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {408--413},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642696},
doi = {10.1109/VLSISOC.2010.5642696},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FranciscoPS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Gioiosa10,
author = {Roberto Gioiosa},
title = {Towards sustainable exascale computing},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {270--275},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642672},
doi = {10.1109/VLSISOC.2010.5642672},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Gioiosa10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GuoLY10,
author = {Jing Guo and
Bing Liu and
George Jie Yuan},
title = {A highly linear wide dynamic range detector for cell recording with
microelectrode arrays},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {179--182},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642601},
doi = {10.1109/VLSISOC.2010.5642601},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GuoLY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HamwiH10,
author = {Khawla Hamwi and
Omar Hammami},
title = {Design and implementation of MPSoC single chip with butterfly network},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {143--148},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642607},
doi = {10.1109/VLSISOC.2010.5642607},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HamwiH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HoL10,
author = {Tsung{-}Yi Ho and
Sheng{-}Hung Liu},
title = {Fast legalization for standard cell placement with simultaneous wirelength
and displacement minimization},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {369--374},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642689},
doi = {10.1109/VLSISOC.2010.5642689},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HoL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HongC10,
author = {Kuo{-}Che Hong and
Herming Chiueh},
title = {A 36-mW continuous-time sigma-delta modulator with 74db dynamic range
and 10-MHz bandwidth},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {392--395},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642693},
doi = {10.1109/VLSISOC.2010.5642693},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HongC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HusemannMGSRL10,
author = {Ronaldo Husemann and
Mariano Majolo and
Victor Guimar{\~{a}}es and
Altamiro Amadeu Susin and
Valter Roesler and
Jos{\'{e}} Valdeni de Lima},
title = {Hardware integrated quantization solution for improvement of computational
{H.264} encoder module},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {316--321},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642680},
doi = {10.1109/VLSISOC.2010.5642680},
timestamp = {Sun, 19 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HusemannMGSRL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JaccottetCAFM10,
author = {Diego Jaccottet and
Eduardo Costa and
Levent Aksoy and
Paulo F. Flores and
Jos{\'{e}} Monteiro},
title = {Design of low-complexity and high-speed digital Finite Impulse Response
filters},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {292--297},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642676},
doi = {10.1109/VLSISOC.2010.5642676},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JaccottetCAFM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JiaoK10,
author = {Hailong Jiao and
Volkan Kursun},
title = {Reactivation noise suppression with threshold voltage tuning in sequential
{MTCMOS} circuits},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {347--351},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642685},
doi = {10.1109/VLSISOC.2010.5642685},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JiaoK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JimenezGKCCBBV10,
author = {V{\'{\i}}ctor Jim{\'{e}}nez and
Roberto Gioiosa and
Eren Kursun and
Francisco J. Cazorla and
Chen{-}Yong Cher and
Alper Buyuktosunoglu and
Pradip Bose and
Mateo Valero},
title = {Trends and techniques for energy efficient architectures},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {276--279},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642673},
doi = {10.1109/VLSISOC.2010.5642673},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JimenezGKCCBBV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JridiA10,
author = {Maher Jridi and
Ayman Alfalou},
title = {A low-power, high-speed {DCT} architecture for image compression:
Principle and implementation},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {304--309},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642678},
doi = {10.1109/VLSISOC.2010.5642678},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JridiA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JungKK10,
author = {Jongpil Jung and
Seonpil Kim and
Chong{-}Min Kyung},
title = {Latency-aware Utility-based {NUCA} Cache Partitioning in 3D-stacked
multi-processor systems},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {125--130},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642608},
doi = {10.1109/VLSISOC.2010.5642608},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JungKK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KarimiS10,
author = {Zohreh Karimi and
Majid Sarrafzadeh},
title = {Fine-grained post placement voltage assignment considering level shifter
overhead},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {73--78},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642618},
doi = {10.1109/VLSISOC.2010.5642618},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KarimiS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KhereddineASMC10,
author = {Rafik Khereddine and
Louay Abdallah and
Emmanuel Simeu and
Salvador Mir and
Fabio Cenni},
title = {Adaptive logical control of {RF} {LNA} performances for efficient
energy consumption},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {161--166},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642602},
doi = {10.1109/VLSISOC.2010.5642602},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KhereddineASMC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KiladaDS10,
author = {Eliyah Kilada and
Shomit Das and
Kenneth S. Stevens},
title = {Synchronous elasticization: Considerations for correct implementation
and MiniMIPS case study},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {7--12},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642631},
doi = {10.1109/VLSISOC.2010.5642631},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KiladaDS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KongL10,
author = {Ji Kong and
Peilin Liu},
title = {A novel reconfigurable scratchpad memory for audio applications on
cost-effective SoC},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {402--407},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642695},
doi = {10.1109/VLSISOC.2010.5642695},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KongL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KrishnaXDBYD10,
author = {Manthena Vamshi Krishna and
Juan Xie and
Manh Anh Do and
Chirn Chye Boon and
Kiat Seng Yeo and
Aaron V. T. Do},
title = {A 1.8-V 3.6-mW 2.4-GHz fully integrated {CMOS} frequency synthesizer
for {IEEE} 802.15.4},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {387--391},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642692},
doi = {10.1109/VLSISOC.2010.5642692},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KrishnaXDBYD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeKK10,
author = {Seunghan Lee and
Kyungsu Kang and
Chong{-}Min Kyung},
title = {Temperature- and bus traffic- aware data placement in 3D-stacked cache},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {352--357},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642686},
doi = {10.1109/VLSISOC.2010.5642686},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeKK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LinCL10,
author = {Kuan Jen Lin and
Yu Chan Chiu and
Tzu{-}Hao Lin},
title = {A decimal squarer with efficient partial product generation},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {213--218},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642662},
doi = {10.1109/VLSISOC.2010.5642662},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LinCL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LinLC10,
author = {Ding{-}Guo Lin and
Bing{-}Hsun Lu and
Herming Chiueh},
title = {An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching
detector},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {101--104},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642615},
doi = {10.1109/VLSISOC.2010.5642615},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LinLC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MagnoLBSB10,
author = {Michele Magno and
Alessandro Lanza and
Davide Brunelli and
Luigi Di Stefano and
Luca Benini},
title = {Energy aware multimodal embedded video surveillance},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {264--269},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642671},
doi = {10.1109/VLSISOC.2010.5642671},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MagnoLBSB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MathewBRPMJ10,
author = {Jimson Mathew and
Savita Banerjee and
Hafizur Rahaman and
Dhiraj K. Pradhan and
Saraju P. Mohanty and
Abusaleh M. Jabir},
title = {On the synthesis of attack tolerant cryptographic hardware},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {286--291},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642675},
doi = {10.1109/VLSISOC.2010.5642675},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MathewBRPMJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MatosCCS10,
author = {Debora Matos and
Miklecio Costa and
Luigi Carro and
Altamiro Amadeu Susin},
title = {Network interface to synchronize multiple packets on NoC-based Systems-on-Chip},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {31--36},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642627},
doi = {10.1109/VLSISOC.2010.5642627},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MatosCCS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Meher10,
author = {Pramod Kumar Meher},
title = {An optimized lookup-table for the evaluation of sigmoid function for
artificial neural networks},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {91--95},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642617},
doi = {10.1109/VLSISOC.2010.5642617},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Meher10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Meher10a,
author = {Pramod Kumar Meher},
title = {Novel input coding technique for high-precision LUT-based multiplication
for {DSP} applications},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {201--206},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642660},
doi = {10.1109/VLSISOC.2010.5642660},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Meher10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MeloniSR10,
author = {Paolo Meloni and
Simone Secchi and
Luigi Raffo},
title = {Enabling fast Network-on-Chip topology selection: an FPGA-based runtime
reconfigurable prototyper},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {43--48},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642625},
doi = {10.1109/VLSISOC.2010.5642625},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MeloniSR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MottenC10,
author = {Andy Motten and
Luc Claesen},
title = {A binary adaptable window SoC architecture for a stereo vision based
depth field processor},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {25--30},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642626},
doi = {10.1109/VLSISOC.2010.5642626},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MottenC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NageswaranRDK10,
author = {Jayram Moorkanikara Nageswaran and
Micah Richert and
Nikil D. Dutt and
Jeffrey L. Krichmar},
title = {Towards reverse engineering the brain: Modeling abstractions and simulation
frameworks},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {1--6},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642630},
doi = {10.1109/VLSISOC.2010.5642630},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NageswaranRDK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NishidaEAIKS10,
author = {Shoichi Nishida and
Jyunya Eto and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Power-aware {FPGA} routing fabrics and design tools},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {67--72},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642621},
doi = {10.1109/VLSISOC.2010.5642621},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NishidaEAIKS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PandaVB10,
author = {Preeti Ranjan Panda and
Anant Vishnoi and
M. Balakrishnan},
title = {Enhancing post-silicon processor debug with Incremental Cache state
Dumping},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {55--60},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642623},
doi = {10.1109/VLSISOC.2010.5642623},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PandaVB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PanellaSRCS10,
author = {Alessandro Panella and
Marco D. Santambrogio and
Francesco Redaelli and
Fabio Cancare and
Donatella Sciuto},
title = {A design workflow for dynamically reconfigurable multi-FPGA systems},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {414--419},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642697},
doi = {10.1109/VLSISOC.2010.5642697},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PanellaSRCS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PettenghiCSA10,
author = {H{\'{e}}ctor Pettenghi and
Ricardo Chaves and
Leonel Sousa and
Maria J. Avedillo},
title = {An improved {RNS} generator 2\({}^{\mbox{n}}\) +/- k based on threshold
logic},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {119--124},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642611},
doi = {10.1109/VLSISOC.2010.5642611},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PettenghiCSA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PlyaskinMGCH10,
author = {Roman Plyaskin and
Alejandro Masrur and
Martin Geier and
Samarjit Chakraborty and
Andreas Herkersdorf},
title = {High-level timing analysis of concurrent applications on MPSoC platforms
using memory-aware trace-driven simulations},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {229--234},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642665},
doi = {10.1109/VLSISOC.2010.5642665},
timestamp = {Tue, 02 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PlyaskinMGCH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PonsMRAVG10,
author = {Marc Pons and
Francesc Moll and
Antonio Rubio and
Jaume Abella and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {{VCTA:} {A} Via-Configurable Transistor Array regular fabric},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {335--340},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642683},
doi = {10.1109/VLSISOC.2010.5642683},
timestamp = {Tue, 11 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PonsMRAVG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PoucheretBBTMR10,
author = {Fran{\c{c}}ois Poucheret and
Lyonel Barthe and
Pascal Benoit and
Lionel Torres and
Philippe Maurine and
Michel Robert},
title = {Spatial {EM} jamming: {A} countermeasure against {EM} Analysis?},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {105--110},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642612},
doi = {10.1109/VLSISOC.2010.5642612},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PoucheretBBTMR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RodriguesAO10,
author = {Joachim Neves Rodrigues and
Omer Can Akgun and
Viktor {\"{O}}wall},
title = {A {\textless} 1 pJ sub-VT cardiac event detector in 65 nm {LL-HVT}
{CMOS}},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {253--258},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642669},
doi = {10.1109/VLSISOC.2010.5642669},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RodriguesAO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ShaoTK10,
author = {Hui Shao and
Chi{-}Ying Tsui and
Wing{-}Hung Ki},
title = {A single inductor {DIDO} {DC-DC} converter for solar energy harvesting
applications using band-band control},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {167--172},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642603},
doi = {10.1109/VLSISOC.2010.5642603},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ShaoTK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SoferNM10,
author = {Sergey Sofer and
Valery Neiman and
Eyal Melamed{-}Cohen},
title = {Synchronous duty cycle correction circuit},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {96--100},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642614},
doi = {10.1109/VLSISOC.2010.5642614},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SoferNM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/StanisavljevicSL10,
author = {Milos Stanisavljevic and
Alexandre Schmid and
Yusuf Leblebici},
title = {Output probability density functions of logic circuits: Modeling and
fault-tolerance evaluation},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {328--334},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642682},
doi = {10.1109/VLSISOC.2010.5642682},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/StanisavljevicSL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SunCAL10,
author = {Fengda Sun and
Alessandro Cevrero and
Panagiotis Athanasopoulos and
Yusuf Leblebici},
title = {Design and feasibility of multi-Gb/s quasi-serial vertical interconnects
based on TSVs for 3D ICs},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {149--154},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642604},
doi = {10.1109/VLSISOC.2010.5642604},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SunCAL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TalapatraR10,
author = {Somsubhra Talapatra and
Hafizur Rahaman},
title = {Low complexity montgomery multiplication architecture for elliptic
curve cryptography over GF(p\({}^{\mbox{m}}\))},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {219--224},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642663},
doi = {10.1109/VLSISOC.2010.5642663},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TalapatraR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsaiCCH10,
author = {Wen{-}Chung Tsai and
Kuo{-}Chih Chu and
Sao{-}Jie Chen and
Yu Hen Hu},
title = {{TM-FAR:} Turn-Model based Fully Adaptive Routing for Networks on
Chip},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {19--24},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642629},
doi = {10.1109/VLSISOC.2010.5642629},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TsaiCCH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TsengXZHS10,
author = {Wei{-}Che Tseng and
Chun Jason Xue and
Qingfeng Zhuge and
Jingtong Hu and
Edwin Hsing{-}Mean Sha},
title = {Optimal scheduling to minimize non-volatile memory access time with
hardware cache},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {131--136},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642609},
doi = {10.1109/VLSISOC.2010.5642609},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TsengXZHS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TtofisPTMD10,
author = {Christos Ttofis and
Agathoklis Papadopoulos and
Theocharis Theocharides and
Maria K. Michael and
Demosthenes Doumenis},
title = {A reconfigurable MPSoC-based {QAM} modulation architecture},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {137--142},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642606},
doi = {10.1109/VLSISOC.2010.5642606},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TtofisPTMD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ValinatajM10,
author = {Mojtaba Valinataj and
Siamak Mohammadi},
title = {A fault-aware, reconfigurable and adaptive routing algorithm for NoC
applications},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {13--18},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642628},
doi = {10.1109/VLSISOC.2010.5642628},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ValinatajM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/VentrouxSDBGB10,
author = {Nicolas Ventroux and
Tanguy Sassolas and
Rapha{\"{e}}l David and
Guillaume Blanc and
Alexandre Guerre and
Charly Bechara},
title = {{SESAM} extension for fast MPSoC architectural exploration and dynamic
streaming applications},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {341--346},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642684},
doi = {10.1109/VLSISOC.2010.5642684},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/VentrouxSDBGB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WenkBBS10,
author = {Markus Wenk and
Lukas Bruderer and
Andreas Burg and
Christoph Studer},
title = {Area- and throughput-optimized {VLSI} architecture of sphere decoding},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {189--194},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642593},
doi = {10.1109/VLSISOC.2010.5642593},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WenkBBS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YangO10,
author = {Chengmo Yang and
Alex Orailoglu},
title = {Fully adaptive multicore architectures through statically-directed
dynamic execution reconfigurations},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {396--401},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642694},
doi = {10.1109/VLSISOC.2010.5642694},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/YangO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/YangXO10,
author = {Chengmo Yang and
Chun Jason Xue and
Alex Orailoglu},
title = {Fine-grained adaptive {CMP} cache sharing through access history exploitation},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {420--425},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642698},
doi = {10.1109/VLSISOC.2010.5642698},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/YangXO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZattDAB10,
author = {Bruno Zatt and
Cl{\'{a}}udio Machado Diniz and
Luciano Volcan Agostini and
Sergio Bampi},
title = {Timing and interface communication analysis of {H.264/AVC} encoder
using SystemC model},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {235--240},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642666},
doi = {10.1109/VLSISOC.2010.5642666},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZattDAB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2010soc,
title = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
publisher = {{IEEE}},
year = {2010},
timestamp = {Wed, 24 Nov 2010 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/2010soc.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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