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  e.g., sig matches "SIGIR" as well as "signal"
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  e.g., graph$ matches "graph", but not "graphics"
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Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 37 matches

• 2024
• 
  Kuntal Chakraborty, Alak Majumder, Abir J. Mondal:
  Time Domain and Area Efficient Smart Temperature Sensor Exploiting Channel Length Modulation Coefficient. J. Circuits Syst. Comput. 33(13): 2450238:1-2450238:18 (2024)
• 
  Anirban Tarafdar, Azharuddin Sheikh, Pinki Majumder, Abhijit Baidya, Alak Majumder, Bidyut K. Bhattacharyya, Uttam Kumar Bera:
  Enhancing intrusion detection using wireless sensor networks: A novel ahp-madm aggregated multiple type 3 fuzzy logic-based k-barriers prediction system. Peer Peer Netw. Appl. 17(3): 1732-1749 (2024)
• 
  Pritam Bhattacharjee, Alak Majumder:
  Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile. VLSID 2024: 587-592
• 2023
• 
  Jyoti Kandpal, Tika Ram Pokhrel, Shalu Saini, Alak Majumder:
  A variation resilient keeper design for high performance domino logic applications. Integr. 88: 1-9 (2023)
• 
  Tika Ram Pokhrel, Alak Majumder:
  Double Gate JLT Based New TIGFET for Dynamic C²MOS Application. APCCAS 2023: 246-250
• 
  Pritam Bhattacharjee, G. Naveen Goud, Vipin K. Singh, Vijay P. Yadav, Abir J. Mondal, Alak Majumder:
  Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS. RADIOELEKTRONIKA 2023: 1-6
• 
  Barnali Chowdhury, Shashank Awasthi, Mohammad Arif Bin Jalil, Alak Majumder, Sanjeev Kumar Metya:
  Ti:LiNbO3 Based EO-MZI Count Optimized Design of Reversible Peres Gate. RADIOELEKTRONIKA 2023: 1-5
• 2022
• 
  Mithilesh Kumar, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya:
  A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link. Integr. 87: 364-377 (2022)
• 
  Mithilesh Kumar, Alak Majumder, Abir J. Mondal:
  Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current. J. Circuits Syst. Comput. 31(16): 2250276:1-2250276:30 (2022)
• 
  Pritam Bhattacharjee, Prerna Rana, Bidyut K. Bhattacharyya, Alak Majumder:
  Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1704-1715 (2022)
• 2021
• 
  Pritam Bhattacharjee, Bidyut K. Bhattacharyya, Alak Majumder:
  A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time. Circuits Syst. Signal Process. 40(4): 1569-1588 (2021)
• 2020
• 
  Madhusudan Maiti, Alak Majumder, Shubhro Chakrabartty, Hanjung Song, Bidyut K. Bhattacharyya:
  Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range. Microelectron. J. 98: 104752 (2020)
• 
  Shashank Awasthi, Saurav Sharma, Sanjeev Kumar Metya, Alak Majumder:
  Electro-optic Reversible Toffoli Gate with Optimal Count of LiNbO3 Mach-Zehnder Interferometers. NorCAS 2020: 1-7
• 
  Madhusudan Maiti, Shubhro Chakrabartty, Alaaddin Al-Shidaifat, Hanjung Song, Bidyut K. Bhattacharyya, Alak Majumder:
  A 90nm PVT Tolerant Current Mode Frequency Divider with Wide Locking Range. NorCAS 2020: 1-5
• 2019
• 
  Pritam Bhattacharjee, Alak Majumder:
  A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application. J. Circuits Syst. Comput. 28(7): 1950108:1-1950108:26 (2019)
• 
  Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya:
  Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1231-1244 (2019)
• 2018
• 
  Nivedita Laskar, Suman Debnath, Alak Majumder, Bidyut K. Bhattacharyya:
  A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%. J. Circuits Syst. Comput. 27(3): 1850049:1-1850049:20 (2018)
• 
  Alak Majumder, Pritam Bhattacharjee, Tushar Dhabal Das:
  A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips. J. Circuits Syst. Comput. 27(9): 1850146:1-1850146:9 (2018)
• 
  Pritam Bhattacharjee, Bipasha Nath, Alak Majumder:
  LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications. CoRR abs/1805.07409 (2018)
• 
  Dhiraj Sarkar, Pritam Bhattacharjee, Alak Majumder:
  Data-Dependent Clock Gating approach for Low Power Sequential System. CoRR abs/1806.02271 (2018)
• 2017
• 
  Shirsha Ghosh, Alak Majumder, Joyeeta Goswami, Abhishek Kumar, Saraju P. Mohanty, Bidyut K. Bhattacharyya:
  Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment. IEEE Consumer Electron. Mag. 6(1): 82-93 (2017)
• 
  Alak Majumder, Joyeeta Goswami, Shirsha Ghosh, Rishu Shrivastawa, Saraju P. Mohanty, Bidyut K. Bhattacharyya:
  Pay-Cloak: A Biometric Back Cover for Smartphones: Facilitating secure contactless payments and identity virtualization at low cost to end users. IEEE Consumer Electron. Mag. 6(2): 78-88 (2017)
• 
  Alak Majumder, Bidyut K. Bhattacharyya:
  Reconstruction of a single square pulse originally having 40 ps width coming from a lossy and noisy channel in a point to point interconnect. Turkish J. Electr. Eng. Comput. Sci. 25: 2055-2065 (2017)
• 
  Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya:
  Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect. Integr. 58: 348-355 (2017)
• 
  Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya:
  A mathematical formulation to design and implementation of a low voltage swing transceiver circuit. Integr. 58: 356-368 (2017)
• 
  Alak Majumder:
  Gated Clock Tree Circuit to Reduce the Noise in Silicon Chip. J. Low Power Electron. 13(4): 576-579 (2017)
• 
  Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya:
  A 65 nm Design of 0.6 V/8.98 μW Process-Voltage-Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications. J. Low Power Electron. 13(3): 511-519 (2017)
• 
  Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya:
  A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. iNIS 2017: 210-214
• 
  Alak Majumder, Pritam Bhattacharjee:
  Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip. iNIS 2017: 224-228
• 
  Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya:
  A Design Methodology for MOS Current Mode Logic VCO. iNIS 2017: 206-209

skipping 7 more matches