• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 22 matches

• 2020
• 
  Samir Wadhwa, Prakashkumar D. Suthar, Vivek Sangwan:
  Simulation Study to Test Feasibility of a Planar Teleoperated Linkage for Qualitative Stiffness Sensing with Communication Delays. BioRob 2020: 358-363
• 2018
• 
  Matthias Kampmann, Sybille Hellebrand:
  Design for Small Delay Test - A Simulation Study. Microelectron. Reliab. 80: 124-133 (2018)
• 2014
• 
  Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel:
  Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay. J. Electron. Test. 30(1): 125-147 (2014)
• 2013
• 
  S. Jayanthy, M. C. Bhuvaneswari, M. Prabhu:
  Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits. Int. J. Comput. Appl. Technol. 48(3): 241-252 (2013)
• 
  Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja:
  Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. Asian Test Symposium 2013: 79-84
• 2011
• 
  Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
  Fault simulation and test generation for clock delay faults. ASP-DAC 2011: 799-805
• 2008
• 
  Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi:
  SoC Symbolic Simulation: a case study on delay fault testing. DDECS 2008: 320-325
• 
  I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta:
  On Accelerating Path Delay Fault Simulation of Long Test Sequences. ITC 2008: 1-9
• 2007
• 
  Wangqi Qiu:
  Fault simulation and test generation for small delay faults. Texas A&M University, College Station, USA, 2007
• 
  Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara:
  Fast and effective fault simulation for path delay faults based on selected testable paths. ITC 2007: 1-10
• 2006
• 
  Irith Pomeranz, Sudhakar M. Reddy:
  A delay fault model for at-speed fault simulation and test generation. ICCAD 2006: 89-95
• 2004
• 
  Li-C. Wang:
  Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation. DATE 2004: 692-695
• 2003
• 
  Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano:
  Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology. IEEE J. Solid State Circuits 38(5): 702-708 (2003)
• 
  Nabil M. Abdulrazzaq, Sandeep K. Gupta:
  Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. VTS 2003: 186-196
• 2002
• 
  Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita:
  Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. Asian Test Symposium 2002: 176-181
• 2000
• 
  Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi:
  False-Path Removal Using Delay Fault Simulation. J. Electron. Test. 16(5): 463-476 (2000)
• 1998
• 
  Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell:
  False-Path Removal Using Delay Fault Simulation. Asian Test Symposium 1998: 82-87
• 
  Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu:
  Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation. Asian Test Symposium 1998: 108-112
• 1993
• 
  Kanji Hirabayashi:
  Delay fault simulation of sequential circuits. J. Electron. Test. 4(2): 131-135 (1993)
• 
  Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
  Delay fault testability evaluation through timing simulation. Great Lakes Symposium on VLSI 1993: 18-21
• 1992
• 
  Yukiko Izuta, Fumiyasu Hirose:
  Test pattern generation system for delay faults using a high speed simulation processor 'SP'. VTS 1992: 13-18
• 1977
• 
  Thomas M. Storey, J. W. Barry:
  Delay test simulation. DAC 1977: 492-494