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Publication search results
found 10 matches
- 2019
- Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto:
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS. ISSCC 2019: 482-484 - 2017
- Shuai Chen, Luke Wang, Hong Zhang, Rosanah Murugesu, Dustin Dunwell, Anthony Chan Carusone:
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2552-2560 (2017) - 2014
- Mike Bichan, Dustin Dunwell, Qiwei Wang, Anthony Chan Carusone:
A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC. ISCAS 2014: 1320-1323 - 2013
- Dustin Dunwell, Anthony Chan Carusone:
Modeling Oscillator Injection Locking Using the Phase Domain Response. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2823-2833 (2013) - Dustin Dunwell, Atul Gupta, Anthony Chan Carusone:
Channel characterization using jitter measurements. ISCAS 2013: 2666-2669 - 2012
- Dustin Dunwell, Anthony Chan Carusone, Jared Zerbe, Brian S. Leibowitz, Barry Daly, John C. Eble:
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on. CICC 2012: 1-4 - 2010
- Dustin Dunwell, Anthony Chan Carusone:
Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver. CICC 2010: 1-4 - Dustin Dunwell, Anthony Chan Carusone:
A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS. ISCAS 2010: 205-208 - 2007
- Michael Bale, Brady Laska, Dustin Dunwell, François Chan, Hamid Jafarkhani:
Computer design of super-orthogonal space-time trellis codes. IEEE Trans. Wirel. Commun. 6(2): 463-467 (2007) - 2006
- Dustin Dunwell, Brian Frank:
24 GHz Low-Noise Amplifiers using High Q Series-Stub Transmission Lines in 0.18µm CMOS. CCECE 2006: 1918-1921
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