• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 9 matches

• 2022
• 
  Hyunjin Shin, Sangkyung Won, Dohui Kim, Byunghun Choi, Gyusung Kim, Myeonghee Oh, Jaeseung Choi, Jongwook Kye:
  A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm² at 0.85V. VLSI Technology and Circuits 2022: 132-133
• 
  Giyoung Yang, Hakchul Jung, Jinyoung Lim, Jaewoo Seo, Ingyum Kim, Jisu Yu, Hyeoungyu You, Jeongsoon Kong, Garoom Kim, Minjae Jeong, Chanhee Park, Sera An, Woojin Rim, Hayoung Kim, Dalhee Lee, Sanghoon Baek, Jonghoon Jung, Taejoong Song, Jongwook Kye:
  Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process. VLSI Technology and Circuits 2022: 363-364
• 2021
• 
  Taejoong Song, Woojin Rim, Hoonki Kim, Keun Hwi Cho, Taeyeong Kim, Taejung Lee, Geumjong Bae, Dong-Won Kim, S. D. Kwon, Sanghoon Baek, Jonghoon Jung, Jongwook Kye, Hakchul Jung, Hyungtae Kim, Soon-Moon Jung, Jaehong Park:
  24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit. ISSCC 2021: 338-340
• 
  Sangyeop Baeck, Inhak Lee, Hoyoung Tang, Dongwook Seo, Jaeseung Choi, Taejoong Song, Jongwook Kye:
  5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application. VLSI Circuits 2021: 1-2
• 
  Hyunjin Shin, Myeonghee Oh, Jaeseung Choi, Taejoong Song, Jongwook Kye:
  A 28nm Embedded Flash Memory with 100MHz Read Operation and 7.42Mb/mm2 at 0.85V featuring for Automotive Application. VLSI Circuits 2021: 1-2
• 2020
• 
  El Mehdi Boujamaa, Samsudeen Mohamed Ali, Steve Ngueya Wandji, Alexandra Gourio, Suk-Soo Pyo, Gwanhyeob Koh, Yoonjong Song, Taejoong Song, Jongwook Kye, Jean-Christophe Vial, Andrew Sowden, Manuj Rathor, Cyrille Dray:
  A 14.7Mb/mm² 28nm FDSOI STT-MRAM with Current Starved Read Path, 52Ω/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference. VLSI Circuits 2020: 1-2
• 2016
• 
  Motoi Ichihashi, Jia Zeng, Cole Zemke, Irene Lin, Greg Northrop, Ning Jin, Jongwook Kye:
  Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology. SoCC 2016: 271-274
• 2012
• 
  Jongwook Kye, Yuansheng Ma, Lei Yuan, Yunfei Deng, Harry J. Levinson:
  Lithography and design integration - New paradigm for the technology architecture development. CICC 2012: 1-4
• 
  Hongbo Zhang, Yunfei Deng, Jongwook Kye, Martin D. F. Wong:
  Impact of lithography retargeting process on low level interconnect in 20nm technology. SLIP 2012: 3-10