• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
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  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 96 matches

• 2024
• 
  Yuncheng Zhang, Kenichi Okada:
  Design of Synthesizable Digital Phase Locked Loops. IPSJ Trans. Syst. LSI Des. Methodol. 17: 44-54 (2024)
• 2023
• 
  Huang Luohua Locke, Kai Ting Keshia Yap, Joseph Chu Ken Yu, Hock Yao Chua:
  QEX: Automated Testing Observability and QA Developer Experience Framework. ICST 2023: 454-460
• 2021
• 
  Shenggang Dong, Ibukunoluwa Momson, Sandeep Kshattry, Pavan Yelleswarapu, Wooyeol Choi, Kenneth K. O:
  A 10-Gb/s 180-GHz Phase-Locked-Loop Minimum Shift Keying Receiver. IEEE J. Solid State Circuits 56(3): 681-693 (2021)
• 
  Emmett D. Goodman, Krishna K. Patel, Yilun Zhang, William Locke, Chris J. Kennedy, Rohan Mehrotra, Stephen Ren, Melody Y. Guan, Maren Downing, Hao Wei Chen, Jevin Z. Clark, Gabriel A. Brat, Serena Yeung:
  A real-time spatiotemporal AI model analyzes skill in open surgical videos. CoRR abs/2112.07219 (2021)
• 2020
• 
  Kenneth A. Sudduth, M. Jennifer Woodward-Greene, Bryan W. Penning, Martin A. Locke, Adam R. Rivers, Kristen S. Veum:
  AI Down on the Farm. IT Prof. 22(3): 22-26 (2020)
• 
  Yoji Yabe, Hisa-Aki Tanaka, Hiroo Sekiya, Masaki Nakagawa, Fumito Mori, Kensuke Utsunomiya, Akira Keida:
  Locking Range Maximization in Injection-Locked Class-E Oscillator - A Case Study for Optimizing Synchronizability. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1762-1774 (2020)
• 
  Yuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, Kiyoshi Yanagisawa, Junjun Qiu, Yun Wang, Jian Pang, Atsushi Shirane, Kenichi Okada:
  A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL. VLSI Circuits 2020: 1-2
• 2019
• 
  Hanli Liu, Atsushi Shirane, Kenichi Okada, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya:
  A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. IEEE J. Solid State Circuits 54(12): 3478-3492 (2019)
• 
  Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada:
  A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. ISSCC 2019: 256-258
• 
  Songtao Liu, Daehwan Jung, Justin C. Norman, M. J. Kennedy, Arthur C. Gossard, John E. Bowers:
  A Low-Noise High-Channel-Count 20 GHz Passively Mode Locked Quantum Dot Laser Grown on Si. OFC 2019: 1-3
• 
  Xinru Wu, Songtao Liu, Daehwan Jung, Justin C. Norman, M. J. Kennedy, Hon Ki Tsang, Arthur C. Gossard, John E. Bowers:
  Terabit Interconnects with a 20-GHz O-Band Passively Mode Locked Quantum Dot Laser Grown Directly on Silicon. OFC 2019: 1-3
• 
  Haosheng Zhang, Aravind Tharayil Narayanan, Hans Herdian, Bangan Liu, Yun Wang, Atsushi Shirane, Kenichi Okada:
  0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur. VLSI Circuits 2019: 38-
• 2018
• 
  Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa:
  A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC 2018: 1-4
• 
  Songtao Liu, Justin C. Norman, Daehwan Jung, M. J. Kennedy, Arthur C. Gossard, John E. Bowers:
  9 GHz passively mode locked quantum dot lasers directly grown on Si. DRC 2018: 1-2
• 
  Stanley Chen, Lei Zhou, Ian Zhuang, Jay Im, Didem Turkur Melek, Jinyung Namkoong, Mayank Raj, Jaewook Shin, Yohan Frans, Ken Chang:
  A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET. ISSCC 2018: 390-392
• 
  Ting-Kuei Kuan, Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
  A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS. VLSI Circuits 2018: 179-180
• 2017
• 
  John E. Laird, Kevin A. Gluck, John R. Anderson, Kenneth D. Forbus, Odest Chadwicke Jenkins, Christian Lebiere, Dario D. Salvucci, Matthias Scheutz, Andrea Thomaz, J. Gregory Trafton, Robert E. Wray, Shiwali Mohan, James R. Kirk:
  Interactive Task Learning. IEEE Intell. Syst. 32(4): 6-21 (2017)
• 
  Ken Kashiwagi, Hajime Inaba:
  Fixed point variations of a frequency comb generated by a passively mode-locked fiber laser. IEICE Electron. Express 14(19): 20170710 (2017)
• 
  Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa:
  A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. IEICE Trans. Electron. 100-C(3): 259-267 (2017)
• 
  Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
  An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC 2017: 13-14
• 
  Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa:
  8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. ISSCC 2017: 150-151
• 2016
• 
  Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa:
  A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. IEEE J. Solid State Circuits 51(5): 1246-1260 (2016)
• 
  Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
  An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ASP-DAC 2016: 1-2
• 
  Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
  An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC 2016: 197-200
• 
  Dawei Mai, Hongjia Mo, Michael Peter Kennedy:
  Comments on "folding of phase noise spectra in charge-pump phase-locked loops induced by frequency division". ICECS 2016: 612-615
• 
  Ahmed Elkholy, Ahmed Elmallah, Mohamed Elzeftawi, Ken Chang, Pavan Kumar Hanumolu:
  10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS. ISSCC 2016: 192-193
• 2015
• 
  Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Rui Wu, Bangan Liu, Kenichi Okada, Akira Matsuzawa:
  A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. IEICE Electron. Express 12(15): 20150531 (2015)
• 
  Masaomi Tsuru, Kengo Kawasaki, Koji Tsutsumi, Eiji Taniguchi:
  Adaptively Phase-Shift Controlled Self-Injection Locked VCO. IEICE Trans. Electron. 98-C(7): 677-684 (2015)
• 
  Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa:
  A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. ASP-DAC 2015: 42-43
• 2014
• 
  Hongming Chen, Song Ma, Liu Wang, Hao Zhang, Kenyi Pan, Yuhua Cheng:
  A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller. Sci. China Inf. Sci. 57(12): 1-8 (2014)

skipping 66 more matches