• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 16 matches

• 2022
• 
  Masoomeh Karami, Mohammad Hashem Haghbayan, Masoumeh Ebrahimi, Antonio Miele, Juha Plosila:
  Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor Systems. DFT 2022: 1-4
• 
  Tiziano Munaro, Irina Muntean:
  Early Assessment of System-Level Safety Mechanisms through Co-Simulation-based Fault Injection. IV 2022: 1703-1708
• 2021
• 
  Trokon Johnson, Herman Lam:
  Incorporating Fault-Tolerance Awareness into System-Level Modeling and Simulation. CLUSTER 2021: 829-830
• 
  Trokon Johnson, Herman Lam:
  Incorporating Fault-Tolerance Awareness into System-Level Modeling and Simulation. FTXS@SC 2021: 31-40
• 2011
• 
  Rafal Baranowski, Stefano Di Carlo, Nadereh Hatami, Michael E. Imhof, Michael A. Kochte, Paolo Prinetto, Hans-Joachim Wunderlich, Christian G. Zoellin:
  Efficient multi-level fault simulation of HW/SW systems for structural faults. Sci. China Inf. Sci. 54(9): 1784-1796 (2011)
• 2010
• 
  Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto:
  Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. Asian Test Symposium 2010: 3-8
• 
  Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto:
  System reliability evaluation using concurrent multi-level simulation of structural faults. ITC 2010: 817
• 2004
• 
  Bill Eklow, Anoosh Hosseini, Chi Khuong, Shyam Pullela, Toai Vo, Hien Chau:
  Simulation Based System Level Fault Insertion Using Co-verification Tools. ITC 2004: 704-710
• 2003
• 
  Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi:
  Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment. Embedded Systems and Applications 2003: 139-143
• 2002
• 
  Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik:
  Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. DELTA 2002: 86-91
• 2000
• 
  Sule Ozev, Alex Orailoglu:
  Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems. VTS 2000: 149-156
• 1999
• 
  Marcelino B. Santos, João Paulo Teixeira:
  Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL. DATE 1999: 549-
• 1997
• 
  Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas:
  SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. DAC 1997: 281-286
• 1996
• 
  Pablo Sanchez, Isabel Hidalgo:
  System Level Fault Simulation. ITC 1996: 732-740
• 1990
• 
  Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham:
  Hierarchical multi-level fault simulation of large systems. J. Electron. Test. 1(2): 139-149 (1990)
• 1975
• 
  Edward W. Thompson, Stephen A. Szygenda:
  Three levels of accuracy for the simulation of different fault types in digital systems. DAC 1975: 105-113