• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 12 matches

• 2023
• 
  James Brown, Kean Hong Tok, Rui Gao, Zhigang Ji, Weidong Zhang, John S. Marsland, Thomas Chiarella, Jacopo Franco, Ben Kaczer, Dimitri Linten, Jianfu Zhang:
  A Pragmatic Model to Predict Future Device Aging. IEEE Access 11: 127725-127736 (2023)
• 
  Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo, P. Wong, A. Sepulveda Marquez, B. T. Chan, Jérôme Mitard, S. Subramanian, S. Demuynck, E. Dentoni Litta, N. Horiguchi, S. Samavedam, S. Biesemans:
  Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. VLSI Technology and Circuits 2023: 1-2
• 2021
• 
  Gerhard Rzepa, Markus Karner, Oskar Baumgartner, Georg Strof, Franz Schanovsky, Ferdinand Mitterbauer, Christian Kernstock, Hui-Wen Karner, Pieter Weckx, Geert Hellings, Dieter Claes, Zhicheng Wu, Yang Xiang, Thomas Chiarella, Bertrand Parvais, Jérôme Mitard, Jacopo Franco, Ben Kaczer, Dimitri Linten, Zlatan Stanojevic:
  Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies. IRPS 2021: 1-6
• 2019
• 
  Shih-Hung Chen, Dimitri Linten, Geert Hellings, Marko Simicic, Ben Kaczer, Thomas Chiarella, Hans Mertens, Jérôme Mitard, Anda Mocuta, N. Horiguchi:
  CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies. IRPS 2019: 1-7
• 2017
• 
  Fabian M. Bufler, Kenichi Miyaguchi, Thomas Chiarella, N. Horiguchi, Anda Mocuta:
  On the ballistic ratio in 14nm-Node FinFETs. ESSDERC 2017: 176-179
• 2016
• 
  Thomas Chiarella, Stefan Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, An De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean:
  Towards high performance sub-10nm finW bulk FinFET technology. ESSDERC 2016: 131-134
• 2015
• 
  Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean:
  Impact of fin shape variability on device performance towards 10nm node. ICICDT 2015: 1-4
• 
  Ankush Chaudhary, Ben Kaczer, Philippe J. Roussel, Thomas Chiarella, Naoto Horiguchi, Souvik Mahapatra:
  Time dependent variability in RMG-HKMG FinFETs: Impact of extraction scheme on stochastic NBTI. IRPS 2015: 3
• 
  Ben Kaczer, Jacopo Franco, M. Cho, Tibor Grasser, Philippe J. Roussel, Stanislav Tyaginov, M. Bina, Yannick Wimmer, Luis-Miguel Procel, Lionel Trojman, Felice Crupi, Gregory Pitner, Vamsi Putcha, Pieter Weckx, Erik Bury, Z. Ji, An De Keersgieter, Thomas Chiarella, Naoto Horiguchi, Guido Groeseneken, Aaron Thean:
  Origins and implications of increased channel hot carrier variability in nFinFETs. IRPS 2015: 3
• 2013
• 
  Doyoung Jang, Marie Garcia Bardon, Dmitry Yakimets, Kenichi Miyaguchi, An De Keersgieter, Thomas Chiarella, Romain Ritzenthaler, Morin Dehan, Abdelkarim Mercha:
  STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process. ESSDERC 2013: 159-162
• 2012
• 
  Christoph Kerner, Ivan Ciofi, Thomas Chiarella, Stefaan Van Huylenbroeck:
  Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques. ESSDERC 2012: 221-225
• 2009
• 
  Thomas Chiarella, Liesbeth Witters, Abdelkarim Mercha, Christoph Kerner, Rok Dittrich, Michal Rakowski, Claude Ortolland, Lars-Åke Ragnarsson, Bertrand Parvais, An De Keersgieter, Stefan Kubicek, Augusto Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, Philippe Absil, S. Biesemans, Thomas Y. Hoffmann:
  Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? ESSCIRC 2009: 84-87