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Publication search results
found 10 matches
- 2024
- Toshiyuki Mineta, Atsuko Miyaji, Hideaki Miyaji:
Proposal for Key-Value Commitments with Offline Batch Update. AsiaJCIS 2024: 129-136 - 2022
- Akihiro Koyama, Yusuke Sugita, Atsushi Isobe, Yudai Kamada, Munenori Degawa, Toshiyuki Mine, Takashi Kawamoto:
Leakage Sensor Placement Optimization Using Acoustic Attenuation Features in Water Mains. IEEE SENSORS 2022: 1-4 - 2014
- Tatsuya Minegishi, Toshiyuki Miyamoto:
Computational evaluation of hybrid method for car control and assignment problem in MCE systems. SMC 2014: 992-995 - 2013
- Tatsuya Minegishi, Toshiyuki Miyamoto:
A study of car control and assignment problem in MCE systems using hybrid method. GCCE 2013: 540-543 - 2009
- Takao Watanabe, Toshimichi Shintani, Kazuo Ono, Toshiyuki Mine:
A digital-data-preservation system featuring LED-light computer tomography. IEICE Electron. Express 6(22): 1569-1575 (2009) - 2004
- Tomoyuki Ishii, Taro Osabe, Toshiyuki Mine, Toshiaki Sano, Bryan Atwood, Norifumi Kameshiro, Takao Watanabe, Kazuo Yano:
SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memories. CICC 2004: 457-463 - Bryan Atwood, Tomoyuki Ishii, Takao Watanabe, Toshiyuki Mine, Norifumi Kameshiro, Toshiaki Sano, Kazuo Yano:
A cavity channel SESO embedded memory with low standby-power techniques. ESSCIRC 2004: 351-354 - 2002
- Toshiyuki Yorozuya, Koji Ohashi, Mineo Kaneko:
Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 819-826 (2002) - 1999
- Kazuo Yano, Tomoyuki Ishii, Toshiaki Sano, Toshiyuki Mine, Fumio Murai, Takashi Hashimoto, Takashi Kobayashi, Tokuo Kure, Koichi Seki:
Single-electron memory for giga-to-tera bit storage. Proc. IEEE 87(4): 633-651 (1999) - 1994
- Masaki Toyokura, Hisahi Kodama, Eiji Miyagoshi, Koyoshi Okamoto, Masahiro Gion, Takayuki Minemaru, Akihiko Ohtani, Toshiyuki Araki, Hiroshi Takeno, Toshihide Akiyama, Brent Wilson, Kunitoshi Aono:
A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC. IEEE J. Solid State Circuits 29(12): 1474-1481 (1994)
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