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Publication search results
found 47 matches
- 1989
- Anant Agarwal, Mathews Cherian:
Adaptive Backoff Synchronization Techniques. ISCA 1989: 396-406 - Manuel L. Anido, David J. Allerton, Ed Zaluska:
A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine. ISCA 1989: 354-361 - Marco Annaratone, Claude Pommerell, Roland Rühl:
Interprocessor Communication Speed and Performance in Distributed-memory Parallel Processors. ISCA 1989: 315-324 - Marco Annaratone, Roland Rühl:
Performance Measurements on a Commercial Multiprocessor Running Parallel Code. ISCA 1989: 307-314 - Yosi Ben-Asher, David Egozi, Assaf Schuster:
2-D SIMD Algorithms in the Perfect Shuffle Networks. ISCA 1989: 88-95 - Hans Benker, Jean-Michel Beacco, Sylvie Bescos, Michel Dorochevsky, Thomas Jeffré, Anita Pohlmann, Jacques Noyé, Bruno Poterie, Alan P. Sexton, Jean-Claude Syre, Oliver Thibault, Günter Watzlawik:
KCM: A Knowledge Crunching Machine. ISCA 1989: 186-194 - Chuen-Liang Chen, Chung-Kai Liao:
Analysis of Vector Access Performance on Skewed Interleaved Memory. ISCA 1989: 387-394 - Ming-Syan Chen, Kang G. Shin:
Task Migration in Hypercube Multiprocessors. ISCA 1989: 105-111 - David R. Cheriton, Hendrik A. Goosen, Patrick D. Boyle:
Multi-level Shared Caching Techniques for Scalability in VMP-M/C. ISCA 1989: 16-24 - Susan J. Eggers, Randy H. Katz:
Evaluating the Performance of Four Snooping Cache Coherency Protocols. ISCA 1989: 2-15 - Paul D. Ezhilchelvan, Santosh K. Shrivastava, Alan Tully:
Constructing Replicated Systems Using Processors with Point-to-Point Communication Links. ISCA 1989: 177-184 - Matthew K. Farrens, Andrew R. Pleszkun:
Improving Performance of Small On-Chip Instruction Caches. ISCA 1989: 234-241 - Tomoo Fukazawa, Takashi Kimura, Masaaki Tomizawa, Kazumitsu Takeda, Yoshitaka Itoh:
R256: A Research Parallel Processor for Scientific Computation. ISCA 1989: 344-351 - Dipak Ghosal, Satish K. Tripathi, Laxmi N. Bhuyan, Hong Jiang:
Analysis of Computation-Communication Issues in Dynamic Dataflow Architectures. ISCA 1989: 325-333 - Atsuhiro Goto, Akira Matsumoto, Evan Tick:
Design and Performance of a Coherent Cache for Parallel Logic Programming Architectures. ISCA 1989: 25-33 - V. Gerald Grafe, George S. Davidson, Jamie E. Hoch, V. P. Holmes:
The Epsilon Dataflow Processor. ISCA 1989: 36-45 - David T. Harper III, Darel A. Linebarger:
A Dynamic Storage Scheme for Conflict-Free Vector Access. ISCA 1989: 72-77 - Andy Hopper, Alan Jones, Dimitris Lioupis:
Multiple vs. Wide Shared Bus Multiprocessors. ISCA 1989: 300-306 - Wen-mei W. Hwu, Pohua P. Chang:
Achieving High Instruction Cache Performance with an Optimizing Compiler. ISCA 1989: 242-251 - Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang:
Comparing Software and Hardware Schemes For Reducing the Cost of Branches. ISCA 1989: 224-233 - Roland N. Ibbett, T. M. Hopkins, K. I. M. McKinnon:
Architectural Mechanisms to Support Sparse Vector Processing. ISCA 1989: 64-71 - Chris R. Jesshope, P. R. Miller, Jay T. Yantchev:
High Performance Communications in Processor Networks. ISCA 1989: 150-157 - Norman P. Jouppi:
Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU. ISCA 1989: 281-289 - Richard E. Kessler, Richard Jooss, Alvin R. Lebeck, Mark D. Hill:
Inexpensive Implementations of Set-Associativity. ISCA 1989: 131-139 - Kichul Kim, Viktor K. Prasanna:
Perfect Latin Squares and Parallel Array Access. ISCA 1989: 372-379 - Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar:
Logic Simulation on Massively Parallel Architectures. ISCA 1989: 336-343 - Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan:
Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks. ISCA 1989: 158-166 - M. Morioka:
S. Yamaguchi, T. Bandoh: Evaluation of Memory System for Integrated Prolog Processor IPP. ISCA 1989: 203-210 - Johannes M. Mulder, Robert J. Portier, A. Srivastava, R. in 't Velt:
An Architecture Framework for Application-Specific and Scalable Architectures. ISCA 1989: 362-369 - Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita:
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. ISCA 1989: 78-85
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