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Publication search results
found 87 matches
- 2015
- Saurabh Agarwal, Mark Ingels, Michal Rakowski, Marianna Pantouvaki, Michiel Steyaert, Philippe P. Absil, Joris Van Campenhout:
Wavelength locking of a Si ring modulator using an integrated drop-port OMA monitoring circuit. A-SSCC 2015: 1-4 - Fengwei An, Keisuke Mihara, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch:
Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors. A-SSCC 2015: 1-4 - Jan A. Angevare, Lorenzo Pedala, Ugur Sonmez, Fabio Sebastiano, Kofi A. A. Makinwa:
A 2800-μm2 thermal-diffusivity temperature sensor with VCO-based readout in 160-nm CMOS. A-SSCC 2015: 1-4 - Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong:
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. A-SSCC 2015: 1-4 - Joo-Hyung Chae, Gi-Moon Hong, Jihwan Park, Mino Kim, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim:
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. A-SSCC 2015: 1-4 - Li-Yang Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee:
CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS. A-SSCC 2015: 1-4 - Huan-Sheng Chen, Hung-Yu Tsai, Li-Xuan Chuo, Yu-Kai Tsai, Liang-Hung Lu:
A 5.2-GHz full-integrated RF front-end by T/R switch, LNA, and PA co-design with 3.2-dB NF and +25.9-dBm output power. A-SSCC 2015: 1-4 - Chi-Huan Chiang, Chang-Cheng Huang, Shen-Iuan Liu:
A digital bang-bang phase-locked loop with bandwidth calibration. A-SSCC 2015: 1-4 - Sangyeun Cho:
Fast memory and storage architectures for the big data era. A-SSCC 2015: 1-4 - Sungwook Choi, KyuTae Park, Marco Passerini, HeeJoung Park, DoYoung Kim, ChiHyun Kim, Kunwoo Park, Jinwoong Kim:
A cell current compensation scheme for 3D NAND FLASH memory. A-SSCC 2015: 1-4 - Li-Cheng Chu, Te-Fu Yang, Ru-Yu Huang, Yi-Ping Su, Chiun-He Lin, Chin-Long Wey, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai:
200nA low quiescent current deep-standby mode in 28nm DC-DC buck converter for active implantable medical devices. A-SSCC 2015: 1-4 - Y. J. Du, W. Su, S. Tolunay, L. Zhang, M. Kaynak, R. Scholz, Yong-Zhong Xiong:
220GHz wide-band MEMS switch in standard BiCMOS technology. A-SSCC 2015: 1-4 - Burak Erbagci, Fangfei Liu, Cagla Cakir, Nail Etkin Can Akkaya, Ruby B. Lee, Ken Mai:
A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS. A-SSCC 2015: 1-4 - Tsun-Yuan Fan, Tsung-Yi Chou, Wen-Hua Chang:
A 0.11mm⁁2 150mW 10GBase-T transmitter in 28nm CMOS process. A-SSCC 2015: 1-4 - Hideto Hidaka:
How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology. A-SSCC 2015: 1-4 - Injoon Hong, Seongwook Park, Junyoung Park, Hoi-Jun Yoo:
A 1.9nJ/pixel embedded deep neural network processor for high speed visual attention in a mobile vision recognition SoC. A-SSCC 2015: 1-4 - Chen-Kai Hsu, Tai-Cheng Lee:
A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology. A-SSCC 2015: 1-4 - Hai Huang, Ling Du, Yun Chiu:
A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer. A-SSCC 2015: 1-4 - Yi-Chieh Huang, Che-Fu Liang, Ping-Ying Wang:
A 1V fractional-N PLL with nonlinearity-insensitive modulator. A-SSCC 2015: 1-4 - Tomoya Ishii, Shogo Hachiya, Sheyang Ning, Masahiro Tanaka, Ken Takeuchi:
0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications. A-SSCC 2015: 1-4 - Sheng-Lyang Jang, Wen-Cheng Lai, Shune-Shing Tzeng, Ching-Wen Hsue:
A wide-band divide-by-3 injection-locked frequency divider using tunable MOS resistor. A-SSCC 2015: 1-5 - Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. A-SSCC 2015: 1-4 - Haikun Jia, Baoyong Chi, Lixue Kuang, Wei Zhu, Zhiping Wang, Feng Ma, Zhihua Wang:
A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS. A-SSCC 2015: 1-4 - Junfeng Jiang, Kofi A. A. Makinwa:
A multi-path CMOS Hall sensor with integrated ripple reduction loops. A-SSCC 2015: 1-4 - Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu:
Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs. A-SSCC 2015: 1-4 - Sung-Yong Kim, Xuefan Jin, Jung-Hoon Chun, Kee-Won Kwon:
A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy. A-SSCC 2015: 1-4 - Hyunki Kim, Kiseok Song, Taehwan Roh, Hoi-Jun Yoo:
A 95% accurate EEG-connectome processor for a mental health monitoring system. A-SSCC 2015: 1-4 - Chia-Chi Kuo, Chih-Cheng Hsieh:
A 132dB DR readout IC with pulse width modulation for IR focal plane arrays. A-SSCC 2015: 1-4 - Liang-Ting Kuo, Chun-Chih Hou, Meng-Hsuan Wu, Yun-Shiang Shu:
A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring. A-SSCC 2015: 1-4 - Jaehwa Kwak, Borivoje Nikolic:
A 550-2260MHz self-adjustable clock generator in 28nm FDSOI. A-SSCC 2015: 1-4
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