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Publication search results
found 65 matches
- 1998
- Selim J. Abou-Samra, P. A. Aisa, Alain Guyot, Bernard Courtois:
3D CMOS SOL for high performance computing. ISLPED 1998: 54-58 - Jay Abraham:
Power calculation and modeling in deep submicron. ISLPED 1998: 124-126 - Bryan D. Ackland, Chris Nicol:
High performance DSPs - what's hot and what's not? ISLPED 1998: 1-6 - Tamara I. Ahrens, Thomas H. Lee:
A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances. ISLPED 1998: 16-19 - Atila Alvandpour, Per Larsson-Edefors, Christer Svensson:
Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. ISLPED 1998: 245-249 - Stephan Avery, Marwan A. Jabri:
A three-port adiabatic register file suitable for embedded applications. ISLPED 1998: 288-292 - R. Iris Bahar, Gianluca Albera, Srilatha Manne:
Power and performance tradeoffs using various caching strategies. ISLPED 1998: 64-69 - Luca Benini, Alessandro Bogliolo, Stefano Cavallucci, Bruno Riccò:
Monitoring system activity for OS-directed dynamic power management. ISLPED 1998: 185-190 - Luca Benini, Robin Hodgson, Polly Siegel:
System-level power estimation and optimization. ISLPED 1998: 173-178 - Michael Benoit, Sandy Taylor, David Overhauser, Steffen Rochel:
Power distribution in high-performance design. ISLPED 1998: 274-278 - Rafael J. Betancourt-Zamora, Thomas H. Lee:
CMOS VCOs for frequency synthesis in wireless biotelemetry. ISLPED 1998: 91-94 - Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl:
Minimum supply voltage for bulk Si CMOS GSI. ISLPED 1998: 100-102 - David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards:
Emerging power management tools for processor design. ISLPED 1998: 143-148 - Michael Bolotski, Phillip Alvelda:
Low-power miniaturized information display systems. ISLPED 1998: 279-281 - J. Patrick Brennan, Alvar Dean, Stephan Kenyon, Sebastian Ventrone:
Low power methodology and design techniques for processor design. ISLPED 1998: 268-273 - Thomas Burger, Qiuting Huang:
On the optimum design of regulated cascode operational transconductance amplifiers. ISLPED 1998: 203-208 - L. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy:
Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits. ISLPED 1998: 106-108 - Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy:
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. ISLPED 1998: 239-244 - Chun-hong Chen, Chi-Ying Tsui:
Towards the capability of providing power-area-delay trade-off at the register transfer level. ISLPED 1998: 24-29 - Mauro Chinosi, Roberto Zafalon, Carlo Guardiani:
Automatic characterization and modeling of power consumption in static RAMs. ISLPED 1998: 112-114 - Eric Y. Chou, A. J. Budrys, Kit M. Cham:
Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture. ISLPED 1998: 42-47 - Ki-Seok Chung, C. L. Liu:
Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. ISLPED 1998: 215-220 - Sari L. Coumeri, Donald E. Thomas:
Memory modeling for system synthesis. ISLPED 1998: 179-184 - Abram P. Dancy, Anantha P. Chandrakasan:
A reconfigurable dual output low power digital PWM power converter. ISLPED 1998: 191-196 - Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram:
Improving sampling efficiency for system level power estimation. ISLPED 1998: 115-117 - Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano:
Power invariant vector compaction based on bit clustering and temporal partitioning. ISLPED 1998: 118-120 - Volker Dudek, Reinhard Grube, Bernd Höfflinger, Michael Schau:
0.5V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology. ISLPED 1998: 103-105 - David Garrett, Mircea R. Stan:
Low power architecture of the soft-output Viterbi algorithm. ISLPED 1998: 262-267 - Catherine H. Gebotys, Robert J. Gebotys:
An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. ISLPED 1998: 121-123 - Joonho Gil, Minkyu Je, Jongho Lee, Hyungcheol Shin:
A high speed and low power SOL inverter using active body-bias. ISLPED 1998: 59-63
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retrieved on 2024-04-25 11:01 CEST from data curated by the dblp team
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