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Publication search results
found 246 matches
- 2001
- Eyad Abou-Allam, John J. Nisbet, Michael C. Maliepaard:
Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology. IEEE J. Solid State Circuits 36(10): 1434-1443 (2001) - André Abrial, Jacky Bouvier, Marc Renaudin, Patrice Senn, Pascal Vivet:
A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller. IEEE J. Solid State Circuits 36(7): 1101-1107 (2001) - Ken-ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda:
A bitline leakage compensation scheme for low-voltage SRAMs. IEEE J. Solid State Circuits 36(5): 726-734 (2001) - Mohamed W. Allam, Mohamed I. Elmasry:
Dynamic current mode logic (DyCML): a new low-power high-performance logic style. IEEE J. Solid State Circuits 36(3): 550-558 (2001) - Josep Altet, Antonio Rubio, Emmanuel Schaub, Stefan Dilhaire, Wilfrid Claeys:
Thermal coupling in integrated circuits: application to thermal testing. IEEE J. Solid State Circuits 36(1): 81-91 (2001) - Bharadwaj S. Amrutur, Mark A. Horowitz:
Fast low-power decoders for RAMs. IEEE J. Solid State Circuits 36(10): 1506-1515 (2001) - Seema Butala Anand, Behzad Razavi:
A CMOS clock recovery circuit for 2.5-Gb/s NRZ data. IEEE J. Solid State Circuits 36(3): 432-439 (2001) - Philippe André, Sylvain Blayac, Philippe Berdaguer, Jean-Louis Benchimol, Jean Godin, Nicolas Kauffmann, Agnieszka Konczykowska, Abed-Elhak Kasbari, Muriel Riet:
InGaAs/InP DHBT technology and design methodology for over 40 Gb/s optical communication circuits. IEEE J. Solid State Circuits 36(9): 1321-1327 (2001) - Anne-Johan Annema, Govert J. G. M. Geelen, Peter C. de Jong:
5.5-V I/O in a 2.5-V 0.25-μm CMOS technology. IEEE J. Solid State Circuits 36(3): 528-538 (2001) - Peter H. Baechtold, Michael P. Beakes, Peter Buchmann, Rolf Clauberg, John F. Ewen, John F. Gilsdorf, Philippe Hauviller, Andreas Herkersdorf, Jean-Claude Le Garrec, Wolfram W. Lemppenau, Ben Parker, Dale J. Pearson, Joseph M. Pereira, Dominique Plassat, Scott K. Reynolds, Hans R. Schindler, André Steimle, David J. Webb, Albert X. Widmer:
Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution. IEEE J. Solid State Circuits 36(1): 74-80 (2001) - Ganesh Balamurugan, Naresh R. Shanbhag:
The twin-transistor noise-tolerant dynamic circuit technique. IEEE J. Solid State Circuits 36(2): 273-280 (2001) - Walter T. Bax, Miles A. Copeland:
A GMSK modulator using a ΔΣ frequency discriminator-based synthesizer. IEEE J. Solid State Circuits 36(8): 1218-1227 (2001) - Farbod Behbahani, Yoji Kishigami, John C. Leete, Asad A. Abidi:
CMOS mixers and polyphase filters for large image rejection. IEEE J. Solid State Circuits 36(6): 873-887 (2001) - Farbod Behbahani, Ali Karimi-Sanjaani, Wee-Guan Tan, Andreas Roithmeier, John C. Leete, Koichi Hoshino, Asad A. Abidi:
Adaptive analog IF signal processor for a wide-band CMOS wireless receiver. IEEE J. Solid State Circuits 36(8): 1205-1217 (2001) - Géraldine Bertrand, Christelle Delage, Marise Bafleur, Nicolas Nolhier, Jean-Marie Dorkel, Quang Nguyen, Nicolas Mauran, David Trémouilles, Philippe Perdu:
Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology. IEEE J. Solid State Circuits 36(9): 1373-1381 (2001) - Azeez J. Bhavnagarwala, Xinghai Tang, James D. Meindl:
The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Solid State Circuits 36(4): 658-665 (2001) - Travis N. Blalock, Neela B. Gaddis, Ken A. Nishimura, Thomas A. Knotts:
True color 1024×768 microdisplay with analog in-pixel pulsewidth modulation and retinal averaging offset correction. IEEE J. Solid State Circuits 36(5): 838-845 (2001) - Giacomino Bollati, Stefano Marchese, Marco Demicheli, Rinaldo Castello:
An eighth-order CMOS low-pass filter with 30-120 MHz tuning range and programmable boost. IEEE J. Solid State Circuits 36(7): 1056-1066 (2001) - Andrea Boni:
1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS. IEEE J. Solid State Circuits 36(6): 979-987 (2001) - Andrea Boni, Andrea Pierazzi, Carlo Morandi:
A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS. IEEE J. Solid State Circuits 36(2): 195-203 (2001) - Andrea Boni, Andrea Pierazzi, Davide Vecchi:
LVDS I/O interface for Gb/s-per-pin operation in 0.35-μ/m CMOS. IEEE J. Solid State Circuits 36(4): 706-711 (2001) - Michele Borgatti, Alessandro Rocchi, Marco Bisio, Monica Besana, Loris Navoni, Pier Luigi Rolandi:
A 64-min single-chip voice recorder/player using embedded 4-b/cell flash memory. IEEE J. Solid State Circuits 36(3): 516-521 (2001) - Anne Van den Bosch, Marc A. F. Borremans, Michel S. J. Steyaert, Willy Sansen:
A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter. IEEE J. Solid State Circuits 36(3): 315-324 (2001) - Bernhard E. Boser:
Editorial. IEEE J. Solid State Circuits 36(8): 1167 (2001) - Lucien J. Breems, Eise Carel Dijkmans, Johan H. Huijsing:
A quadrature data-dependent DEM algorithm to improve image rejection of a complex ΣΔ modulator. IEEE J. Solid State Circuits 36(12): 1879-1886 (2001) - Simona Brigati, Fabrizio Francesconi, Matteo Poletti, Daniela Fumagalli, Guido Grassi, Piero Malcovati:
A 147-dB dynamic range electronic attenuator for audiometric applications with on-chip 1-W power amplifier. IEEE J. Solid State Circuits 36(7): 1087-1093 (2001) - Tom P. E. Broekaert, Willie Ng, Joseph F. Jensen, Daniel Yap, David L. Persechini, S. Bourgholtzer, Charles H. Fields, Young K. Brown-Boegeman, Binqiang Shi, Robert H. Walden:
InP-HBT optoelectronic integrated circuits for photonic analog-to-digital conversion. IEEE J. Solid State Circuits 36(9): 1335-1342 (2001) - Federico Bruccoleri, Eric A. M. Klumperink, Bram Nauta:
Generating all two-MOS-transistor amplifiers leads to new wide-band LNAs. IEEE J. Solid State Circuits 36(7): 1032-1040 (2001) - Thomas Burger, Qiuting Huang:
A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSM dual-standard IF reception. IEEE J. Solid State Circuits 36(12): 1868-1878 (2001) - Jan Butas, Chiu-Sing Choy, Juraj Povazanec, Cheong-Fat Chan:
Asynchronous cross-pipelined multiplier. IEEE J. Solid State Circuits 36(8): 1272-1275 (2001)
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