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ORCIDVLSI-SoC 2015: Daejeon, South Korea
- 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015. IEEE 2015, ISBN 978-1-4673-9140-5
- Naehyuck Chang, Kiyoung Choi:
Message from the general chairs. VIII - Youngsoo Shin, Chi-Ying Tsui
:
Message from the technical program chairs. IX
CAD: Physical Design and Test
- Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
An Incremental Timing-Driven flow using quadratic formulation for detailed placement. 1-6 - Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
Flare reduction in EUV Lithography by perturbation of wire segments. 7-12 - Masahiro Fujita:
Analysis and testing on delays with two time frames. 13-18 - Lilian Bossuet, Viktor Fischer, Pierre Bayon:
Contactless transmission of intellectual property data to protect FPGA designs. 19-24
Embedded: Analysis and Optimization for Embedded Systems
- Michael Gautschi, Andreas Traber, Antonio Pullini, Luca Benini, Michele Scandale, Alessandro Di Federico, Michele Beretta, Giovanni Agosta:
Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores. 25-30 - Matthew M. Kim, Karl M. Fant, Paul Beckett:
Design of asynchronous RISC CPU register-file Write-Back queue. 31-36 - Manikantan Srinivasan, C. Siva Ram Murthy, Anusuya Balasubramanian:
Modular performance analysis of Multicore SoC-based small cell LTE base station. 37-42 - Manikandan Pandiyan, Geetha Mani:
Embedded low power analog CMOS Fuzzy Logic Controller chip for industrial applications. 43-48
Special Session A: The Brain-Inspired Computing: from Circuits to Software
- Jae-sun Seo, Mingoo Seok:
Digital CMOS neuromorphic processor design featuring unsupervised online learning. 49-51 - Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li:
An overview on memristor crossabr based neuromorphic circuit and architecture. 52-56
Low power: Power and Error Management
- Alberto Bocca, Alessandro Sassone, Donghwa Shin, Alberto Macii, Enrico Macii, Massimo Poncino:
An equation-based battery cycle life model for various battery chemistries. 57-62 - Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Power-management high-level synthesis. 63-68 - Jaemin Lee, Seungwon Kim, Youngmin Kim, Seokhyeong Kang:
An optimal operating point by using error monitoring circuits with an error-resilient technique. 69-73 - Pierre Nicolas-Nicolaz, Kiyoung Choi:
Dynamic error tracking and supply voltage adjustment for low power. 74-79
Special Session B: Directed Self Assembly Lithography
- Seongbo Shim, Youngsoo Shin:
Physical design and mask optimization for directed self-assembly lithography (DSAL). 80-85
Memory: Non Volatile Memory Architecture
- Chengmo Yang, Maria Ruiz Varela:
Qualifying non-volatile register files for embedded systems through compiler-directed write minimization and balancing. 86-91 - Yuan Xue, Patrick Cronin, Chengmo Yang, Jingtong Hu:
Non-volatile memories in FPGAs: Exploiting logic similarity to accelerate reconfiguration and increase programming cycles. 92-97 - Jaehyun Park, Donghwa Shin, Hyung Gyu Lee:
Prefetch-based dynamic row buffer management for LPDDR2-NVM devices. 98-103 - Jaehyun Park, Donghwa Shin, Hyung Gyu Lee:
Design space exploration of row buffer architecture for phase change memory with LPDDR2-NVM interface. 104-109
Architecture I: 3D Circuits and Architecture
- Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Architecture exploration of 3D FPGA to minimize internal layer connection. 110-115 - Bartosz Boguslawski, Hossam Sarhan, Frédéric Heitzmann, Fabrice Seguin, Sébastien Thuries, Olivier Billoint, Fabien Clermidy:
Compact interconnect approach for networks of neural cliques using 3D technology. 116-121 - Surajit Kumar Roy, Supriyo Mandal, Chandan Giri, Hafizur Rahaman:
A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs. 122-127 - Lin Wei, Lei Zhou:
An equilibrium partitioning method for multicast traffic in 3D NoC architecture. 128-133
Circuits & Systems I: System-on-Chips for Signal Processing and Communications
- Xabier Iturbe, Didier Keymeulen, Emre Ozer, Patrick Yiu, Daniel Berisford, Kevin P. Hand, Robert Carlson:
An integrated SoC for science data processing in next-generation space flight instruments avionics. 134-141 - Asim Khan, Muhammad Umar Karim Khan, Muhammad Bilal, Chong-Min Kyung:
Hardware architecture and optimization of sliding window based pedestrian detection on FPGA for high resolution images by varying local features. 142-148 - Hyungil Park, Ingi Lim, Sungweon Kang, Whan-woo Kim:
10Mbps human body communication SoC for BAN. 149-153 - Manikandan Pandiyan, Geetha Mani, Jovitha Jerome, Natarajan S.:
Integrating wearable low power CMOS ECG acquisition SoC with decision making system for WSBN applications. 154-158
Variability: Design and Test for Mitigating Variability and Reliability Issues
- Mini Jayakrishnan, Alan Chang, José Pineda de Gyvez, Tae-Hyoung Kim:
Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing. 159-164 - Víctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez:
Circuit performance optimization for local intra-die process variations using a gate selection metric. 165-170 - Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik:
Scalable algorithm for structural fault collapsing in digital circuits. 171-176 - Jing-Jia Liou, Meng-Ta Hsieh, Jun-Fei Cherng, Harry H. Chen:
Cost reduction of system-level tests with stressed structural tests and SVM. 177-182 - Namhyung Kim, Junwhan Ahn, Woong Seo, Kiyoung Choi:
Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. 183-188
Architecture II: CPU/GPU, Cache, and Interconnect
- Chun-Jen Tsai, Tsung-Han Wu, Hung-Cheng Su:
JAIP-MP: A four-core Java application processor. 189-194 - Hyunsun Park, Junwhan Ahn, Eunhyeok Park, Sungjoo Yoo:
Locality-aware vertex scheduling for GPU-based graph computation. 195-200 - Ramin Bashizade, Hamid Sarbazi-Azad:
Traffic-aware buffer reconfiguration in on-chip networks. 201-206
Circuits & Systems II: Circuits and Systems for Signal Processing and Communications
- Gain Kim, Raffaele Capoccia, Yusuf Leblebici:
Design optimization of polyphase digital down converters for extremely high frequency wireless communications. 207-212 - Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Dual-mode double precision / two-parallel single precision floating point multiplier architecture. 213-218 - Kerem Seyid, Sebastien Blanc, Yusuf Leblebici:
Hardware implementation of real-time multiple frame super-resolution. 219-224 - Shahzad Muzaffar, Ibrahim M. Elfadel:
Timing and robustness analysis of Pulsed-Index protocols for single-channel IoT communications. 225-230
Analog: Ultra-Low-Power Analog Circuits for loT Applications
- Anvesha Amaravati, Manan Chugh, Arijit Raychowdhury:
A time interleaved DAC sharing SAR Pipeline ADC for ultra-low power camera front ends. 231-236 - S. E. Kim, T. W. Kang, S. W. Kang, K. H. Park, M. A. Chung:
High-efficiency voltage regulation stage in energy harvesting systems. 237-240 - Hamed Abbasizadeh, Behnam Samadpoor Rikan, Kang-Yoon Lee:
A fully on-chip 25MHz PVT-compensation CMOS Relaxation Oscillator. 241-245
Prototyping: Modeling, Validation, and Debug
- Alessandro Danese, Francesca Filini, Graziano Pravadelli:
A time-window based approach for dynamic assertions mining on control signals. 246-251 - Jun Guo, Peng Liu, Weidong Wang:
Physical-based modeling and fast simulation of wireline links. 252-257 - Shridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
Trace signal selection methods for post silicon debugging. 258-263 - Samah Mohamed Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu:
Timing attack on NEMS relay based design of AES. 264-269
Posters
- Qiong Wei Low, Liter Siek, Mi Zhou:
A high efficiency rectifier for inductively power transfer application. 270-273 - Ananthanarayanan Parthasarathy:
Design and analysis of search algorithms for lower power consumption and faster convergence of DAC input of SAR-ADC in 65nm CMOS. 274-279 - Amir Masoud Gharehbaghi, Masahiro Fujita:
Efficient signature-based sub-circuit matching. 280-285 - Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler:
Reversible circuit rewriting with simulated annealing. 286-291 - Seongmo Park, Kyungjin Byun, Nak-Woong Eum:
A hybrid embedded compression codec engine for ultra HD video application. 292-296 - Andres F. Gomez, Víctor H. Champac:
A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging. 297-302 - Jae-Jin Lee, Chan Kim, Kyungjin Byun, Nak-Woong Eum:
Virtual prototype based on Aldebarn CPU core. 303-306 - Chadi Al Khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet:
A generic clock controller for low power systems: Experimentation on an AXI bus. 307-312 - Artur Quiring, Markus Olbrich, Erich Barke:
Fast global interconnnect driven 3D floorplanning. 313-318 - Hyunsun Park, Chanha Kim, Sungjoo Yoo, Chanik Park:
Filtering dirty data in DRAM to reduce PRAM writes. 319-324 - Tara Ghasempouri, Graziano Pravadelli:
On the estimation of assertion interestingness. 325-330 - Jia Wei Tang, Yuan Wen Hau, Muhammad N. Marsono:
Hardware/software partitioning of embedded System-on-Chip applications. 331-336 - Zoltán Endre Rákossy, Dominik Stengele, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay:
Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture. 337-342 - John Jose, Joe Augustine, Sijin Sebastian:
Dynamic migratory selection strategy for adaptive routing in mesh NoCs. 343-348 - Ying-Jung Chen, Shanq-Jang Ruan:
A cluster-based reliability- and thermal-aware 3D floorplanning using redundant STSVs. 349-354 - Yuanwen Huang, Anupam Chattopadhyay, Prabhat Mishra:
Trace Buffer Attack: Security versus observability study in post-silicon debug. 355-360
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